Signed-off-by: Walter Schweizer swwa@users.sourceforge.net ---
Changes in v2: None
board/Synology/ds109/kwbimage.cfg | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/board/Synology/ds109/kwbimage.cfg b/board/Synology/ds109/kwbimage.cfg index 19d77e3..d544af5 100644 --- a/board/Synology/ds109/kwbimage.cfg +++ b/board/Synology/ds109/kwbimage.cfg @@ -19,7 +19,10 @@ BOOT_FROM spi # Maximum KWBIMAGE_MAX_CONFIG configurations allowed
# Configure RGMII-0/1 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1b1b9b9b +DATA 0xFFD100e0 0x1b1b1b9b + +DATA 0xFFD20134 0xbbbbbbbb +DATA 0xFFD20138 0x00bbbbbb
#Dram initalization for SINGLE x16 CL=5 @ 400MHz DATA 0xFFD01400 0x43000c30 # DDR Configuration register @@ -30,7 +33,7 @@ DATA 0xFFD01400 0x43000c30 # DDR Configuration register # bit29-26: zero # bit31-30: 01
-DATA 0xFFD01404 0x37543000 # DDR Controller Control Low +DATA 0xFFD01404 0x39543000 # DDR Controller Control Low # bit 4: 0=addr/cmd in smame cycle # bit 5: 0=clk is driven during self refresh, we don't care for APX # bit 6: 0=use recommended falling edge of clk for addr/cmd @@ -52,14 +55,14 @@ DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) # bit27-24: TRRD # bit31-28: TRTP
-DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) +DATA 0xFFD0140C 0x00000833 # DDR Timing (High) # bit6-0: TRFC # bit8-7: TR2R # bit10-9: TR2W # bit12-11: TW2W # bit31-13: zero required
-DATA 0xFFD01410 0x000000cc # DDR Address Control +DATA 0xFFD01410 0x0000000d # DDR Address Control # bit1-0: 01, Cs0width=x8 # bit3-2: 10, Cs0size=1Gb # bit5-4: 01, Cs1width=x8 @@ -92,7 +95,7 @@ DATA 0xFFD0141C 0x00000C52 # DDR Mode # bit12: 0, PD must be zero # bit31-13: 0 required
-DATA 0xFFD01420 0x00000040 # DDR Extended Mode +DATA 0xFFD01420 0x00000042 # DDR Extended Mode # bit0: 0, DDR DLL enabled # bit1: 0, DDR drive strenght normal # bit2: 0, DDR ODT control lsd (disabled) @@ -104,7 +107,7 @@ DATA 0xFFD01420 0x00000040 # DDR Extended Mode # bit12: 0, DDR output buffer enabled # bit31-13: 0 required
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High # bit2-0: 111, required # bit3 : 1 , MBUS Burst Chop disabled # bit6-4: 111, required @@ -120,26 +123,28 @@ DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size # bit0: 1, Window enabled # bit1: 0, Write Protect disabled # bit3-2: 00, CS0 hit selected # bit23-4: ones, required -# bit31-24: 0x0F, Size (i.e. 256MB) +# bit31-24: 0x07, Size (i.e. 128MB)
DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb -DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01510 0x20000000 # CS[2]n Base address to 256Mb DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD01518 0x30000000 # CS[3]n Base address to 256Mb DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) +DATA 0xFFD01494 0x003C0000 # DDR ODT Control (Low) DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) # bit1-0: 00, ODT0 controlled by ODT Control (low) register above # bit3-2: 01, ODT1 active NEVER! # bit31-4: zero, required
-DATA 0xFFD0149C 0x0000E803 # CPU ODT Control +DATA 0xFFD0149C 0x0000F80F # CPU ODT Control DATA 0xFFD01480 0x00000001 # DDR Initialization Control #bit0=1, enable DDR init upon this register write