Implement macro SOCFPGA_RESET(name), which produces an abstract reset number. Implement macros which allow extracting the reset offset in permodrstN register and which permodrstN register the reset is located in from this abstract reset number. Use these macros throughout the reset manager.
Signed-off-by: Marek Vasut marex@denx.de --- arch/arm/mach-socfpga/include/mach/reset_manager.h | 47 ++++++++++++++++++---- arch/arm/mach-socfpga/reset_manager.c | 22 +++++----- 2 files changed, 50 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 7e803f7..fff4c96 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -38,13 +38,44 @@ struct socfpga_reset_manager { #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 #endif
-#define RSTMGR_PERMODRST_EMAC0_LSB 0 -#define RSTMGR_PERMODRST_EMAC1_LSB 1 -#define RSTMGR_PERMODRST_L4WD0_LSB 6 -#define RSTMGR_PERMODRST_OSC1TIMER0_LSB 8 -#define RSTMGR_PERMODRST_UART0_LSB 16 -#define RSTMGR_PERMODRST_SPIM0_LSB 18 -#define RSTMGR_PERMODRST_SPIM1_LSB 19 -#define RSTMGR_PERMODRST_SDR_LSB 29 +/* + * Define a reset identifier, from which a permodrst bank ID + * and reset ID can be extracted using the subsequent macros + * RSTMGR_RESET() and RSTMGR_BANK(). + */ +#define RSTMGR_BANK_OFFSET 8 +#define RSTMGR_BANK_MASK 0x7 +#define RSTMGR_RESET_OFFSET 0 +#define RSTMGR_RESET_MASK 0x1f +#define RSTMGR_DEFINE(_bank, _offset) \ + ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET) + +/* Extract reset ID from the reset identifier. */ +#define RSTMGR_RESET(_reset) \ + (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK) + +/* Extract bank ID from the reset identifier. */ +#define RSTMGR_BANK(_reset) \ + (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK) + +/* + * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows: + * 0 ... mpumodrst + * 1 ... permodrst + * 2 ... per2modrst + * 3 ... brgmodrst + * 4 ... miscmodrst + */ +#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) +#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) +#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) +#define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) +#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) +#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) +#define RSTMGR_SDR RSTMGR_DEFINE(1, 29) + +/* Create a human-readable reference to SoCFPGA reset. */ +#define SOCFPGA_RESET(_name) RSTMGR_##_name
#endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c index 45b352b..8ede779 100644 --- a/arch/arm/mach-socfpga/reset_manager.c +++ b/arch/arm/mach-socfpga/reset_manager.c @@ -20,11 +20,11 @@ void socfpga_watchdog_reset(void) { /* assert reset for watchdog */ setbits_le32(&reset_manager_base->per_mod_reset, - 1 << RSTMGR_PERMODRST_L4WD0_LSB); + 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)));
/* deassert watchdog from reset (watchdog in not running state) */ clrbits_le32(&reset_manager_base->per_mod_reset, - 1 << RSTMGR_PERMODRST_L4WD0_LSB); + 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0))); }
/* @@ -94,13 +94,13 @@ void socfpga_emac_reset(int enable) const void *reset = &reset_manager_base->per_mod_reset;
if (enable) { - setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB); - setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB); + setbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC0))); + setbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC1))); } else { #if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS) - clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB); + clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC0))); #elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS) - clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB); + clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC1))); #endif } } @@ -110,8 +110,8 @@ void socfpga_spim_enable(void) { const void *reset = &reset_manager_base->per_mod_reset;
- clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) | - (1 << RSTMGR_PERMODRST_SPIM1_LSB)); + clrbits_le32(reset, (1 << RSTMGR_RESET(SOCFPGA_RESET(SPIM0))) | + (1 << RSTMGR_RESET(SOCFPGA_RESET(SPIM1)))); }
/* Bring UART0 out of reset. */ @@ -119,7 +119,7 @@ void socfpga_uart0_enable(void) { const void *reset = &reset_manager_base->per_mod_reset;
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_UART0_LSB); + clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(UART0))); }
/* Bring SDRAM controller out of reset. */ @@ -127,7 +127,7 @@ void socfpga_sdram_enable(void) { const void *reset = &reset_manager_base->per_mod_reset;
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SDR_LSB); + clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(SDR))); }
/* Bring OSC1 timer out of reset. */ @@ -135,5 +135,5 @@ void socfpga_osc1timer_enable(void) { const void *reset = &reset_manager_base->per_mod_reset;
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_OSC1TIMER0_LSB); + clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(OSC1TIMER0))); }