[U-Boot] [PATCH v4 5/8] riscv: ax25: add imply v5l2 cache controller

From: Rick Chen rick@andestech.com

Select the v5l2 UCLASS_CACHE driver for ax25.

Signed-off-by: Rick Chen rick@andestech.com Cc: KC Lin kclin@andestech.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- arch/riscv/cpu/ax25/Kconfig | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 6b4b92e..49be775 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -4,6 +4,7 @@ config RISCV_NDS imply CPU imply CPU_RISCV imply RISCV_TIMER + imply V5L2_CACHE imply ANDES_PLIC if RISCV_MMODE imply ANDES_PLMT if RISCV_MMODE help