Don't use hardcoded clock IDs, use the IDs from the dt-bindings to be compatible with upstream.
Taken from kernel tag v6.7
Reviewed-by: Neil Armstrong neil.armstrong@linaro.org Signed-off-by: Caleb Connolly caleb.connolly@linaro.org --- arch/arm/dts/dragonboard820c.dts | 5 +++-- drivers/clk/qcom/clock-apq8096.c | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts index 86b7f83d36d6..282c37e28f42 100644 --- a/arch/arm/dts/dragonboard820c.dts +++ b/arch/arm/dts/dragonboard820c.dts @@ -8,6 +8,7 @@ /dts-v1/;
#include "skeleton64.dtsi" +#include <dt-bindings/clock/qcom,gcc-msm8996.h>
/ { model = "Qualcomm Technologies, Inc. DB820c"; @@ -78,7 +79,7 @@ blsp2_uart2: serial@75b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x75b0000 0x1000>; - clocks = <&gcc 4>; + clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>; clock-names = "core"; pinctrl-names = "uart"; pinctrl-0 = <&blsp8_uart>; @@ -89,7 +90,7 @@ reg = <0x74a4900 0x314>, <0x74a4000 0x800>; index = <0x0>; bus-width = <4>; - clock = <&gcc 0>; + clock = <&gcc GCC_SDCC1_APPS_CLK>; clock-frequency = <200000000>; };
diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index 1e6fdb5cd42d..a4731613c5e0 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -13,6 +13,7 @@ #include <errno.h> #include <asm/io.h> #include <linux/bitops.h> +#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include "clock-qcom.h"
@@ -107,10 +108,10 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate) struct msm_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) { - case 0: /* SDC1 */ + case GCC_SDCC1_APPS_CLK: /* SDC1 */ return clk_init_sdc(priv, rate); break; - case 4: /*UART2*/ + case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/ return clk_init_uart(priv); default: return 0;