26 Apr
2007
26 Apr
'07
4:36 p.m.
Timur Tabi wrote:
Well, that's odd. I just got a revision 3.1 board here that, when I follow those steps (don't define CFG_DDR_SDRAM_CLK_CNTL and don't set sdram_clk_cntl to 0), it works when before it didn't.
I have a revision 1.0 board here (I think... The silkscreen in the middle of the board reads "MPC8349E-mITX REV1.0"). Is there any chance the revision can explain the disparity in behavior? -Michael