On 11/29/22 12:41, Ashok Reddy Soma wrote:
cadence_qspi_apb_enable_linear_mode() has a weak function defined, so no need to gaurd this under if (CONFIG_IS_ENABLED(ARCH_VERSAL)).
In cadence_qspi_apb_write_execute(), enable linear mode is called twice by mistake, remove extra one.
Signed-off-by: Ashok Reddy Soma ashok.reddy.soma@amd.com
drivers/spi/cadence_qspi_apb.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index cfae5dcbda..d1f89138ef 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -735,8 +735,7 @@ int cadence_qspi_apb_read_execute(struct cadence_spi_priv *priv, void *buf = op->data.buf.in; size_t len = op->data.nbytes;
- if (CONFIG_IS_ENABLED(ARCH_VERSAL))
cadence_qspi_apb_enable_linear_mode(true);
cadence_qspi_apb_enable_linear_mode(true);
if (priv->use_dac_mode && (from + len < priv->ahbsize)) { if (len < 256 ||
@@ -905,9 +904,6 @@ int cadence_qspi_apb_write_execute(struct cadence_spi_priv *priv, const void *buf = op->data.buf.out; size_t len = op->data.nbytes;
- if (CONFIG_IS_ENABLED(ARCH_VERSAL))
cadence_qspi_apb_enable_linear_mode(true);- /*
- Some flashes like the Cypress Semper flash expect a dummy 4-byte
- address (all 0s) with the read status register command in DTR mode.
Applied. M