[U-Boot] [PATCH V3 01/12] Blackfin: Bf60x: new processor header files

14 Nov 2012

Add header files for blackfin new processor bf60x.
Signed-off-by: Bob Liu lliubbo@gmail.com
---
 arch/blackfin/include/asm/blackfin_cdef.h         |    3 +
 arch/blackfin/include/asm/blackfin_def.h          |    5 +
 arch/blackfin/include/asm/blackfin_local.h        |    3 +
 arch/blackfin/include/asm/mach-bf609/BF609_cdef.h |  543 +++
 arch/blackfin/include/asm/mach-bf609/BF609_def.h  | 3758 +++++++++++++++++++++
 arch/blackfin/include/asm/mach-bf609/anomaly.h    |  128 +
 arch/blackfin/include/asm/mach-bf609/def_local.h  |    5 +
 arch/blackfin/include/asm/mach-bf609/portmux.h    |  257 ++
 arch/blackfin/include/asm/mach-bf609/ports.h      |  103 +
 arch/blackfin/include/asm/mach-common/bits/cgu.h  |   80 +
 arch/blackfin/include/asm/mach-common/bits/dde.h  |   88 +
 arch/blackfin/include/asm/mach-common/bits/mpu.h  |    6 +-
 arch/blackfin/include/asm/mach-common/bits/pll.h  |    5 +
 13 files changed, 4983 insertions(+), 1 deletion(-)
 create mode 100644 arch/blackfin/include/asm/mach-bf609/BF609_cdef.h
 create mode 100644 arch/blackfin/include/asm/mach-bf609/BF609_def.h
 create mode 100644 arch/blackfin/include/asm/mach-bf609/anomaly.h
 create mode 100644 arch/blackfin/include/asm/mach-bf609/def_local.h
 create mode 100644 arch/blackfin/include/asm/mach-bf609/portmux.h
 create mode 100644 arch/blackfin/include/asm/mach-bf609/ports.h
 create mode 100644 arch/blackfin/include/asm/mach-common/bits/cgu.h
 create mode 100644 arch/blackfin/include/asm/mach-common/bits/dde.h

diff --git a/arch/blackfin/include/asm/blackfin_cdef.h b/arch/blackfin/include/asm/blackfin_cdef.h
index a19f0f7..8608711 100644
--- a/arch/blackfin/include/asm/blackfin_cdef.h
+++ b/arch/blackfin/include/asm/blackfin_cdef.h
@@ -84,5 +84,8 @@
 #ifdef __ADSPBF561__
 # include "mach-bf561/BF561_cdef.h"
 #endif
+#ifdef __ADSPBF609__
+# include "mach-bf609/BF609_cdef.h"
+#endif
#endif /* __MACH_CDEF_BLACKFIN__ */
diff --git a/arch/blackfin/include/asm/blackfin_def.h b/arch/blackfin/include/asm/blackfin_def.h
index f06d1f1..c96a3ec 100644
--- a/arch/blackfin/include/asm/blackfin_def.h
+++ b/arch/blackfin/include/asm/blackfin_def.h
@@ -136,5 +136,10 @@
 # include "mach-bf561/anomaly.h"
 # include "mach-bf561/def_local.h"
 #endif
+#ifdef __ADSPBF609__
+# include "mach-bf609/BF609_def.h"
+# include "mach-bf609/anomaly.h"
+# include "mach-bf609/def_local.h"
+#endif
#endif /* __MACH_DEF_BLACKFIN__ */
diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h
index 49d0c9e..fc46ef4 100644
--- a/arch/blackfin/include/asm/blackfin_local.h
+++ b/arch/blackfin/include/asm/blackfin_local.h
@@ -61,6 +61,9 @@
 extern u_long get_vco(void);
 extern u_long get_cclk(void);
 extern u_long get_sclk(void);
+extern u_long get_sclk0(void);
+extern u_long get_sclk1(void);
+extern u_long get_dclk(void);
# define bfin_revid() (bfin_read_CHIPID() >> 28)
diff --git a/arch/bla new file mode 100644 index 0000000..a8c0773 --- /dev/null +++ b/arch/blackfin/i @@ -0,0 +1,543 @@ +/* DO NOT EDIT THIS FILE + * Automatically + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_CDEF_ADSP_BF504_proc__ +#define __BFIN_CDEF_ADSP_BF504_proc__ + +#include "../ma + +#define bfin_read_CGU_STAT() +#define bfin_read_CGU_CLKOUTSEL() +#define bfin_read_CGU_CTL() +#define bfin_write_CGU_CTL(val) +#define bfin_read_CGU_DIV() +#define bfin_write_CGU_DIV(val) + +#define bfin_read_RCU0_CTL() +#define bfin_write_RCU0_CTL(val) + +#define bfin_read_CH +#define bfin_write_C + +#define bfin_read_DMC0_CFG() +#define bfin_write_DMC0_CFG(val) +#define bfin_read_DMC0_TR0() +#define bfin_write_DMC0_TR0(val) +#define bfin_read_DMC0_TR1() +#define bfin_write_DMC0_TR1(val) +#define bfin_read_DMC0_TR2() +#define bfin_write_DMC0_TR2(val) +#define bfin_read_DMC0_MR() +#define bfin_write_DMC0_MR(val) +#define bfin_read_DMC0_EMR1() +#define bfin_write_DMC0_EMR1(val) +#define bfin_read_DMC0_CTL() +#define bfin_write_DMC0_CTL(val) +#define bfin_read_DMC0_STAT() +#define bfin_write_DMC0_STAT(val) +#define bfin_read_DMC0_DLLCTL() +#define bfin_write_D + +#define bfin_read_SE +#define bfin_write_S +#define bfin_read_SE +#define bfin_write_S + +#define bfin_read_SE +#define bfin_write_S +#define bfin_read_SE +#define bfin_write_SEC_SCTL(sid, + +#define bfin_read_SMC_GCTL() +#define bfin_write_SMC_GCTL(val) +#define bfin_read_SMC_GSTAT() +#define bfin_read_SMC_B0CTL() +#define bfin_write_SMC_B0CTL(val) +#define bfin_read_SMC_B0TIM() +#define bfin_write_SMC_B0TIM(val) +#define bfin_read_SMC_B0ETIM() +#define bfin_write_S +#define bfin_read_SMC_B1CTL() +#define bfin_write_SMC_B1CTL(val) +#define bfin_read_SMC_B1TIM() +#define bfin_write_SMC_B1TIM(val) +#define bfin_read_SMC_B1ETIM() +#define bfin_write_S +#define bfin_read_SMC_B2CTL() +#define bfin_write_SMC_B2CTL(val) +#define bfin_read_SMC_B2TIM() +#define bfin_write_SMC_B2TIM(val) +#define bfin_read_SMC_B2ETIM() +#define bfin_write_S +#define bfin_read_SMC_B3CTL() +#define bfin_write_SMC_B3CTL(val) +#define bfin_read_SMC_B3TIM() +#define bfin_write_SMC_B3TIM(val) +#define bfin_read_SMC_B3ETIM() +#define bfin_write_S + +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DMA0_CONFIG() +#define bfin_write_D +#define bfin_read_DMA0_X_COUNT() +#define bfin_write_D +#define bfin_read_DMA0_X_MODIFY() +#define bfin_write_D +#define bfin_read_DMA0_Y_COUNT() +#define bfin_write_D +#define bfin_read_DMA0_Y_MODIFY() +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DMA1_CONFIG() +#define bfin_write_D +#define bfin_read_DMA1_X_COUNT() +#define bfin_write_D +#define bfin_read_DMA1_X_MODIFY() +#define bfin_write_D +#define bfin_read_DMA1_Y_COUNT() +#define bfin_write_D +#define bfin_read_DMA1_Y_MODIFY() +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DMA2_CONFIG() +#define bfin_write_D +#define bfin_read_DMA2_X_COUNT() +#define bfin_write_D +#define bfin_read_DMA2_X_MODIFY() +#define bfin_write_D +#define bfin_read_DMA2_Y_COUNT() +#define bfin_write_D +#define bfin_read_DMA2_Y_MODIFY() +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DMA3_CONFIG() +#define bfin_write_D +#define bfin_read_DMA3_X_COUNT() +#define bfin_write_D +#define bfin_read_DMA3_X_MODIFY() +#define bfin_write_D +#define bfin_read_DMA3_Y_COUNT() +#define bfin_write_D +#define bfin_read_DMA3_Y_MODIFY() +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DMA4_CONFIG() +#define bfin_write_D +#define bfin_read_DMA4_X_COUNT() +#define bfin_write_D +#define bfin_read_DMA4_X_MODIFY() +#define bfin_write_D +#define bfin_read_DMA4_Y_COUNT() +#define bfin_write_D +#define bfin_read_DMA4_Y_MODIFY() +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DMA5_CONFIG() +#define bfin_write_D +#define bfin_read_DMA5_X_COUNT() +#define bfin_write_D +#define bfin_read_DMA5_X_MODIFY() +#define bfin_write_D +#define bfin_read_DMA5_Y_COUNT() +#define bfin_write_D +#define bfin_read_DMA5_Y_MODIFY() +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DMA6_CONFIG() +#define bfin_write_D +#define bfin_read_DMA6_X_COUNT() +#define bfin_write_D +#define bfin_read_DMA6_X_MODIFY() +#define bfin_write_D +#define bfin_read_DMA6_Y_COUNT() +#define bfin_write_D +#define bfin_read_DMA6_Y_MODIFY() +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DMA7_CONFIG() +#define bfin_write_D +#define bfin_read_DMA7_X_COUNT() +#define bfin_write_D +#define bfin_read_DMA7_X_MODIFY() +#define bfin_write_D +#define bfin_read_DMA7_Y_COUNT() +#define bfin_write_D +#define bfin_read_DMA7_Y_MODIFY() +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DMA8_CONFIG() +#define bfin_write_D +#define bfin_read_DMA8_X_COUNT() +#define bfin_write_D +#define bfin_read_DMA8_X_MODIFY() +#define bfin_write_D +#define bfin_read_DMA8_Y_COUNT() +#define bfin_write_D +#define bfin_read_DMA8_Y_MODIFY() +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DMA9_CONFIG() +#define bfin_write_D +#define bfin_read_DMA9_X_COUNT() +#define bfin_write_D +#define bfin_read_DMA9_X_MODIFY() +#define bfin_write_D +#define bfin_read_DMA9_Y_COUNT() +#define bfin_write_D +#define bfin_read_DMA9_Y_MODIFY() +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DMA10_CONFIG() +#define bfin_write_D +#define bfin_read_DMA10_X_COUNT() +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DMA10_Y_COUNT() +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DMA11_CONFIG() +#define bfin_write_D +#define bfin_read_DMA11_X_COUNT() +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DMA11_Y_COUNT() +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_DM +#define bfin_write_D +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M +#define bfin_read_MD +#define bfin_write_M + +#define bfin_read_WDOG_CNT() +#define bfin_write_WDOG_CNT(val) +#define bfin_read_WDOG_CTL() +#define bfin_write_WDOG_CTL(val) +#define bfin_read_WDOG_STAT() +#define bfin_write_WDOG_STAT(val) +#define bfin_read_SPI_BAUD() +#define bfin_write_SPI_BAUD(val) + +#define bfin_read_PORTD_FER() +#define bfin_write_P +#define bfin_write_P +#define bfin_read_PORTD_MUX() +#define bfin_write_PORTD_MUX(val) +#define bfin_read_PORTG_FER() +#define bfin_write_P +#define bfin_write_P +#define bfin_read_PORTG_MUX() +#define bfin_write_PORTG_MUX(val) + +#define bfin_read_RS +#define bfin_write_R +#define bfin_read_RSI_ARGUMENT() +#define bfin_write_R +#define bfin_read_RSI_COMMAND() +#define bfin_write_R +#define bfin_read_RSI_RESP_CMD() +#define bfin_write_R +#define bfin_read_RSI_RESPONSE0() +#define bfin_write_R +#define bfin_read_RSI_RESPONSE1() +#define bfin_write_R +#define bfin_read_RSI_RESPONSE2() +#define bfin_write_R +#define bfin_read_RSI_RESPONSE3() +#define bfin_write_R +#define bfin_read_RS +#define bfin_write_R +#define bfin_read_RSI_DATA_LGTH() +#define bfin_write_R +#define bfin_read_RS +#define bfin_write_R +#define bfin_read_RSI_DATA_CNT() +#define bfin_write_R +#define bfin_read_RSI_STATUS() +#define bfin_write_R +#define bfin_read_RSI_STATUSCL() +#define bfin_write_R +#define bfin_read_RSI_MASK0() +#define bfin_write_RSI_MASK0(val) +#define bfin_read_RSI_MASK1() +#define bfin_write_RSI_MASK1(val) +#define bfin_read_RSI_FIFO_CNT() +#define bfin_write_R +#define bfin_read_RS +#define bfin_write_R +#define bfin_read_RSI_BLKSZ() +#define bfin_write_RSI_BLKSZ(val) +#define bfin_read_RSI_FIFO() +#define bfin_write_RSI_FIFO(val) +#define bfin_read_RSI_ESTAT() +#define bfin_write_RSI_ESTAT(val) +#define bfin_read_RSI_EMASK() +#define bfin_write_RSI_EMASK(val) +#define bfin_read_RSI_CONFIG() +#define bfin_write_R +#define bfin_read_RS +#define bfin_write_R +#define bfin_read_RSI_PID0() +#define bfin_write_RSI_PID0(val) +#define bfin_read_RSI_PID1() +#define bfin_write_RSI_PID1(val) +#define bfin_read_RSI_PID2() +#define bfin_write_RSI_PID2(val) +#define bfin_read_RSI_PID3() +#define bfin_write_RSI_PID3(val) + +#endif /* __BFIN_CDE diff --git a/arch/bla new file mode 100644 index 0000000..9c92a6b --- /dev/null +++ b/arch/blackfin/i @@ -0,0 +1,3758 @@ +/* DO NOT EDIT THIS FILE + * Automatically + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_DEF_ADSP_BF504_proc__ +#define __BFIN_DEF_ADSP_BF504_proc__ + +#include "../ma + +#define CNT_CFG +#define CNT_IMSK +#define CNT_STAT +#define CNT_CMD +#define CNT_DEBNCE +#define CNT_CNTR +#define CNT_MAX +#define CNT_MIN + +#define RSI_CLK_CONTROL +#define RSI_ARGUMENT +#define RSI_COMMAND +#define RSI_RESP_CMD +#define RSI_RESPONSE0 +#define RSI_RESPONSE1 +#define RSI_RESPONSE2 +#define RSI_RESPONSE3 +#define RSI_DATA_TIMER +#define RSI_DATA_LGTH +#define RSI_DATA_CONTROL +#define RSI_DATA_CNT +#define RSI_STATUS +#define RSI_STATUSCL +#define RSI_IMSK0 +#define RSI_IMSK1 +#define RSI_FIFO_CNT +#define RSI_CEATA_CONTROL +#define RSI_BOOT_TCNTR +#define RSI_BACK_TOUT +#define RSI_SLP_WKUP_TOUT +#define RSI_BLKSZ +#define RSI_FIFO +#define RSI_ESTAT +#define RSI_EMASK +#define RSI_CONFIG +#define RSI_RD_WAIT_EN +#define RSI_PID0 +#define RSI_PID1 +#define RSI_PID2 +#define RSI_PID3 + +#define CAN0_MC1 +#define CAN0_MD1 +#define CAN0_TRS1 +#define CAN0_TRR1 +#define CAN0_TA1 +#define CAN0_AA1 +#define CAN0_RMP1 +#define CAN0_RML1 +#define CAN0_MBTIF1 +#define CAN0_MBRIF1 +#define CAN0_MBIM1 +#define CAN0_RFH1 +#define CAN0_OPSS1 +#define CAN0_MC2 +#define CAN0_MD2 +#define CAN0_TRS2 +#define CAN0_TRR2 +#define CAN0_TA2 +#define CAN0_AA2 +#define CAN0_RMP2 +#define CAN0_RML2 +#define CAN0_MBTIF2 +#define CAN0_MBRIF2 +#define CAN0_MBIM2 +#define CAN0_RFH2 +#define CAN0_OPSS2 +#define CAN0_CLK +#define CAN0_TIMING +#define CAN0_DBG +#define CAN0_STAT +#define CAN0_CEC +#define CAN0_GIS +#define CAN0_GIM +#define CAN0_GIF +#define CAN0_CTL +#define CAN0_INT +#define CAN0_MBTD +#define CAN0_EWR +#define CAN0_ESR +#define CAN0_UCCNT +#define CAN0_UCRC +#define CAN0_UCCNF +#define CAN0_AM00L +#define CAN0_AM01L +#define CAN0_AM02L +#define CAN0_AM03L +#define CAN0_AM04L +#define CAN0_AM05L +#define CAN0_AM06L +#define CAN0_AM07L +#define CAN0_AM08L +#define CAN0_AM09L +#define CAN0_AM10L +#define CAN0_AM11L +#define CAN0_AM12L +#define CAN0_AM13L +#define CAN0_AM14L +#define CAN0_AM15L +#define CAN0_AM16L +#define CAN0_AM17L +#define CAN0_AM18L +#define CAN0_AM19L +#define CAN0_AM20L +#define CAN0_AM21L +#define CAN0_AM22L +#define CAN0_AM23L +#define CAN0_AM24L +#define CAN0_AM25L +#define CAN0_AM26L +#define CAN0_AM27L +#define CAN0_AM28L +#define CAN0_AM29L +#define CAN0_AM30L +#define CAN0_AM31L +#define CAN0_AM00H +#define CAN0_AM01H +#define CAN0_AM02H +#define CAN0_AM03H +#define CAN0_AM04H +#define CAN0_AM05H +#define CAN0_AM06H +#define CAN0_AM07H +#define CAN0_AM08H +#define CAN0_AM09H +#define CAN0_AM10H +#define CAN0_AM11H +#define CAN0_AM12H +#define CAN0_AM13H +#define CAN0_AM14H +#define CAN0_AM15H +#define CAN0_AM16H +#define CAN0_AM17H +#define CAN0_AM18H +#define CAN0_AM19H +#define CAN0_AM20H +#define CAN0_AM21H +#define CAN0_AM22H +#define CAN0_AM23H +#define CAN0_AM24H +#define CAN0_AM25H +#define CAN0_AM26H +#define CAN0_AM27H +#define CAN0_AM28H +#define CAN0_AM29H +#define CAN0_AM30H +#define CAN0_AM31H +#define CAN0_MB00_DATA0 +#define CAN0_MB01_DATA0 +#define CAN0_MB02_DATA0 +#define CAN0_MB03_DATA0 +#define CAN0_MB04_DATA0 +#define CAN0_MB05_DATA0 +#define CAN0_MB06_DATA0 +#define CAN0_MB07_DATA0 +#define CAN0_MB08_DATA0 +#define CAN0_MB09_DATA0 +#define CAN0_MB10_DATA0 +#define CAN0_MB11_DATA0 +#define CAN0_MB12_DATA0 +#define CAN0_MB13_DATA0 +#define CAN0_MB14_DATA0 +#define CAN0_MB15_DATA0 +#define CAN0_MB16_DATA0 +#define CAN0_MB17_DATA0 +#define CAN0_MB18_DATA0 +#define CAN0_MB19_DATA0 +#define CAN0_MB20_DATA0 +#define CAN0_MB21_DATA0 +#define CAN0_MB22_DATA0 +#define CAN0_MB23_DATA0 +#define CAN0_MB24_DATA0 +#define CAN0_MB25_DATA0 +#define CAN0_MB26_DATA0 +#define CAN0_MB27_DATA0 +#define CAN0_MB28_DATA0 +#define CAN0_MB29_DATA0 +#define CAN0_MB30_DATA0 +#define CAN0_MB31_DATA0 +#define CAN0_MB00_DATA1 +#define CAN0_MB01_DATA1 +#define CAN0_MB02_DATA1 +#define CAN0_MB03_DATA1 +#define CAN0_MB04_DATA1 +#define CAN0_MB05_DATA1 +#define CAN0_MB06_DATA1 +#define CAN0_MB07_DATA1 +#define CAN0_MB08_DATA1 +#define CAN0_MB09_DATA1 +#define CAN0_MB10_DATA1 +#define CAN0_MB11_DATA1 +#define CAN0_MB12_DATA1 +#define CAN0_MB13_DATA1 +#define CAN0_MB14_DATA1 +#define CAN0_MB15_DATA1 +#define CAN0_MB16_DATA1 +#define CAN0_MB17_DATA1 +#define CAN0_MB18_DATA1 +#define CAN0_MB19_DATA1 +#define CAN0_MB20_DATA1 +#define CAN0_MB21_DATA1 +#define CAN0_MB22_DATA1 +#define CAN0_MB23_DATA1 +#define CAN0_MB24_DATA1 +#define CAN0_MB25_DATA1 +#define CAN0_MB26_DATA1 +#define CAN0_MB27_DATA1 +#define CAN0_MB28_DATA1 +#define CAN0_MB29_DATA1 +#define CAN0_MB30_DATA1 +#define CAN0_MB31_DATA1 +#define CAN0_MB00_DATA2 +#define CAN0_MB01_DATA2 +#define CAN0_MB02_DATA2 +#define CAN0_MB03_DATA2 +#define CAN0_MB04_DATA2 +#define CAN0_MB05_DATA2 +#define CAN0_MB06_DATA2 +#define CAN0_MB07_DATA2 +#define CAN0_MB08_DATA2 +#define CAN0_MB09_DATA2 +#define CAN0_MB10_DATA2 +#define CAN0_MB11_DATA2 +#define CAN0_MB12_DATA2 +#define CAN0_MB13_DATA2 +#define CAN0_MB14_DATA2 +#define CAN0_MB15_DATA2 +#define CAN0_MB16_DATA2 +#define CAN0_MB17_DATA2 +#define CAN0_MB18_DATA2 +#define CAN0_MB19_DATA2 +#define CAN0_MB20_DATA2 +#define CAN0_MB21_DATA2 +#define CAN0_MB22_DATA2 +#define CAN0_MB23_DATA2 +#define CAN0_MB24_DATA2 +#define CAN0_MB25_DATA2 +#define CAN0_MB26_DATA2 +#define CAN0_MB27_DATA2 +#define CAN0_MB28_DATA2 +#define CAN0_MB29_DATA2 +#define CAN0_MB30_DATA2 +#define CAN0_MB31_DATA2 +#define CAN0_MB00_DATA3 +#define CAN0_MB01_DATA3 +#define CAN0_MB02_DATA3 +#define CAN0_MB03_DATA3 +#define CAN0_MB04_DATA3 +#define CAN0_MB05_DATA3 +#define CAN0_MB06_DATA3 +#define CAN0_MB07_DATA3 +#define CAN0_MB08_DATA3 +#define CAN0_MB09_DATA3 +#define CAN0_MB10_DATA3 +#define CAN0_MB11_DATA3 +#define CAN0_MB12_DATA3 +#define CAN0_MB13_DATA3 +#define CAN0_MB14_DATA3 +#define CAN0_MB15_DATA3 +#define CAN0_MB16_DATA3 +#define CAN0_MB17_DATA3 +#define CAN0_MB18_DATA3 +#define CAN0_MB19_DATA3 +#define CAN0_MB20_DATA3 +#define CAN0_MB21_DATA3 +#define CAN0_MB22_DATA3 +#define CAN0_MB23_DATA3 +#define CAN0_MB24_DATA3 +#define CAN0_MB25_DATA3 +#define CAN0_MB26_DATA3 +#define CAN0_MB27_DATA3 +#define CAN0_MB28_DATA3 +#define CAN0_MB29_DATA3 +#define CAN0_MB30_DATA3 +#define CAN0_MB31_DATA3 +#define CAN0_MB00_LENGTH +#define CAN0_MB01_LENGTH +#define CAN0_MB02_LENGTH +#define CAN0_MB03_LENGTH +#define CAN0_MB04_LENGTH +#define CAN0_MB05_LENGTH +#define CAN0_MB06_LENGTH +#define CAN0_MB07_LENGTH +#define CAN0_MB08_LENGTH +#define CAN0_MB09_LENGTH +#define CAN0_MB10_LENGTH +#define CAN0_MB11_LENGTH +#define CAN0_MB12_LENGTH +#define CAN0_MB13_LENGTH +#define CAN0_MB14_LENGTH +#define CAN0_MB15_LENGTH +#define CAN0_MB16_LENGTH +#define CAN0_MB17_LENGTH +#define CAN0_MB18_LENGTH +#define CAN0_MB19_LENGTH +#define CAN0_MB20_LENGTH +#define CAN0_MB21_LENGTH +#define CAN0_MB22_LENGTH +#define CAN0_MB23_LENGTH +#define CAN0_MB24_LENGTH +#define CAN0_MB25_LENGTH +#define CAN0_MB26_LENGTH +#define CAN0_MB27_LENGTH +#define CAN0_MB28_LENGTH +#define CAN0_MB29_LENGTH +#define CAN0_MB30_LENGTH +#define CAN0_MB31_LENGTH +#define CAN0_MB00_TIMESTAMP +#define CAN0_MB01_TIMESTAMP +#define CAN0_MB02_TIMESTAMP +#define CAN0_MB03_TIMESTAMP +#define CAN0_MB04_TIMESTAMP +#define CAN0_MB05_TIMESTAMP +#define CAN0_MB06_TIMESTAMP +#define CAN0_MB07_TIMESTAMP +#define CAN0_MB08_TIMESTAMP +#define CAN0_MB09_TIMESTAMP +#define CAN0_MB10_TIMESTAMP +#define CAN0_MB11_TIMESTAMP +#define CAN0_MB12_TIMESTAMP +#define CAN0_MB13_TIMESTAMP +#define CAN0_MB14_TIMESTAMP +#define CAN0_MB15_TIMESTAMP +#define CAN0_MB16_TIMESTAMP +#define CAN0_MB17_TIMESTAMP +#define CAN0_MB18_TIMESTAMP +#define CAN0_MB19_TIMESTAMP +#define CAN0_MB20_TIMESTAMP +#define CAN0_MB21_TIMESTAMP +#define CAN0_MB22_TIMESTAMP +#define CAN0_MB23_TIMESTAMP +#define CAN0_MB24_TIMESTAMP +#define CAN0_MB25_TIMESTAMP +#define CAN0_MB26_TIMESTAMP +#define CAN0_MB27_TIMESTAMP +#define CAN0_MB28_TIMESTAMP +#define CAN0_MB29_TIMESTAMP +#define CAN0_MB30_TIMESTAMP +#define CAN0_MB31_TIMESTAMP +#define CAN0_MB00_ID0 +#define CAN0_MB01_ID0 +#define CAN0_MB02_ID0 +#define CAN0_MB03_ID0 +#define CAN0_MB04_ID0 +#define CAN0_MB05_ID0 +#define CAN0_MB06_ID0 +#define CAN0_MB07_ID0 +#define CAN0_MB08_ID0 +#define CAN0_MB09_ID0 +#define CAN0_MB10_ID0 +#define CAN0_MB11_ID0 +#define CAN0_MB12_ID0 +#define CAN0_MB13_ID0 +#define CAN0_MB14_ID0 +#define CAN0_MB15_ID0 +#define CAN0_MB16_ID0 +#define CAN0_MB17_ID0 +#define CAN0_MB18_ID0 +#define CAN0_MB19_ID0 +#define CAN0_MB20_ID0 +#define CAN0_MB21_ID0 +#define CAN0_MB22_ID0 +#define CAN0_MB23_ID0 +#define CAN0_MB24_ID0 +#define CAN0_MB25_ID0 +#define CAN0_MB26_ID0 +#define CAN0_MB27_ID0 +#define CAN0_MB28_ID0 +#define CAN0_MB29_ID0 +#define CAN0_MB30_ID0 +#define CAN0_MB31_ID0 +#define CAN0_MB00_ID1 +#define CAN0_MB01_ID1 +#define CAN0_MB02_ID1 +#define CAN0_MB03_ID1 +#define CAN0_MB04_ID1 +#define CAN0_MB05_ID1 +#define CAN0_MB06_ID1 +#define CAN0_MB07_ID1 +#define CAN0_MB08_ID1 +#define CAN0_MB09_ID1 +#define CAN0_MB10_ID1 +#define CAN0_MB11_ID1 +#define CAN0_MB12_ID1 +#define CAN0_MB13_ID1 +#define CAN0_MB14_ID1 +#define CAN0_MB15_ID1 +#define CAN0_MB16_ID1 +#define CAN0_MB17_ID1 +#define CAN0_MB18_ID1 +#define CAN0_MB19_ID1 +#define CAN0_MB20_ID1 +#define CAN0_MB21_ID1 +#define CAN0_MB22_ID1 +#define CAN0_MB23_ID1 +#define CAN0_MB24_ID1 +#define CAN0_MB25_ID1 +#define CAN0_MB26_ID1 +#define CAN0_MB27_ID1 +#define CAN0_MB28_ID1 +#define CAN0_MB29_ID1 +#define CAN0_MB30_ID1 +#define CAN0_MB31_ID1 +#define LP0_CTL +#define LP0_STAT +#define LP0_DIV +#define LP0_CNT +#define LP0_TX +#define LP0_RX +#define LP0_TXIN_SHDW +#define LP0_TXOUT_SHDW +#define LP1_CTL +#define LP1_STAT +#define LP1_DIV +#define LP1_CNT +#define LP1_TX +#define LP1_RX +#define LP1_TXIN_SHDW +#define LP1_TXOUT_SHDW +#define LP2_CTL +#define LP2_STAT +#define LP2_DIV +#define LP2_CNT +#define LP2_TX +#define LP2_RX +#define LP2_TXIN_SHDW +#define LP2_TXOUT_SHDW +#define LP3_CTL +#define LP3_STAT +#define LP3_DIV +#define LP3_CNT +#define LP3_TX +#define LP3_RX +#define LP3_TXIN_SHDW +#define LP3_TXOUT_SHDW +#define TIMER0_REVID +#define TIMER0_RUN +#define TIMER0_RUN_SET +#define TIMER0_RUN_CLR +#define TIMER0_STOP_CFG +#define TIMER0_STOP_CFG_SET +#define TIMER0_STOP_CFG_CLR +#define TIMER0_DATA_IMSK +#define TIMER0_STAT_IMSK +#define TIMER0_TRG_MSK +#define TIMER0_TRG_IE +#define TIMER0_DATA_ILAT +#define TIMER0_STAT_ILAT +#define TIMER0_ERR_TYPE +#define TIMER0_BCAST_PER +#define TIMER0_BCAST_WID +#define TIMER0_BCAST_DLY +#define TIMER0_TMR0_CFG +#define TIMER0_TMR1_CFG +#define TIMER0_TMR2_CFG +#define TIMER0_TMR3_CFG +#define TIMER0_TMR4_CFG +#define TIMER0_TMR5_CFG +#define TIMER0_TMR6_CFG +#define TIMER0_TMR7_CFG +#define TIMER0_TMR0_CNT +#define TIMER0_TMR1_CNT +#define TIMER0_TMR2_CNT +#define TIMER0_TMR3_CNT +#define TIMER0_TMR4_CNT +#define TIMER0_TMR5_CNT +#define TIMER0_TMR6_CNT +#define TIMER0_TMR7_CNT +#define TIMER0_TMR0_PER +#define TIMER0_TMR1_PER +#define TIMER0_TMR2_PER +#define TIMER0_TMR3_PER +#define TIMER0_TMR4_PER +#define TIMER0_TMR5_PER +#define TIMER0_TMR6_PER +#define TIMER0_TMR7_PER +#define TIMER0_TMR0_WID +#define TIMER0_TMR1_WID +#define TIMER0_TMR2_WID +#define TIMER0_TMR3_WID +#define TIMER0_TMR4_WID +#define TIMER0_TMR5_WID +#define TIMER0_TMR6_WID +#define TIMER0_TMR7_WID +#define TIMER0_TMR0_DLY +#define TIMER0_TMR1_DLY +#define TIMER0_TMR2_DLY +#define TIMER0_TMR3_DLY +#define TIMER0_TMR4_DLY +#define TIMER0_TMR5_DLY +#define TIMER0_TMR6_DLY +#define TIMER0_TMR7_DLY +#define CRC0_CTL +#define CRC0_DCNT +#define CRC0_DCNTRLD +#define CRC0_COMP +#define CRC0_FILLVAL +#define CRC0_DFIFO +#define CRC0_INEN +#define CRC0_INEN_SET +#define CRC0_INEN_CLR +#define CRC0_POLY +#define CRC0_STAT +#define CRC0_DCNTCAP +#define CRC0_RESULT_FIN +#define CRC0_RESULT_CUR +#define CRC0_REVID +#define CRC0_LUT0 +#define CRC0_LUT1 +#define CRC0_LUT2 +#define CRC0_LUT3 +#define CRC0_LUT4 +#define CRC0_LUT5 +#define CRC0_LUT6 +#define CRC0_LUT7 +#define CRC0_LUT8 +#define CRC0_LUT9 +#define CRC0_LUT10 +#define CRC0_LUT11 +#define CRC0_LUT12 +#define CRC0_LUT13 +#define CRC0_LUT14 +#define CRC0_LUT15 +#define CRC1_CTL +#define CRC1_DCNT +#define CRC1_DCNTRLD +#define CRC1_COMP +#define CRC1_FILLVAL +#define CRC1_DFIFO +#define CRC1_INEN +#define CRC1_INEN_SET +#define CRC1_INEN_CLR +#define CRC1_POLY +#define CRC1_STAT +#define CRC1_DCNTCAP +#define CRC1_RESULT_FIN +#define CRC1_RESULT_CUR +#define CRC1_REVID +#define CRC1_LUT0 +#define CRC1_LUT1 +#define CRC1_LUT2 +#define CRC1_LUT3 +#define CRC1_LUT4 +#define CRC1_LUT5 +#define CRC1_LUT6 +#define CRC1_LUT7 +#define CRC1_LUT8 +#define CRC1_LUT9 +#define CRC1_LUT10 +#define CRC1_LUT11 +#define CRC1_LUT12 +#define CRC1_LUT13 +#define CRC1_LUT14 +#define CRC1_LUT15 +#define TWI0_CLKDIV +#define TWI0_CTL +#define TWI0_SLVCTL +#define TWI0_SLVSTAT +#define TWI0_SLVADDR +#define TWI0_MSTRCTL +#define TWI0_MSTRSTAT +#define TWI0_MSTRADDR +#define TWI0_ISTAT +#define TWI0_IMSK +#define TWI0_FIFOCTL +#define TWI0_FIFOSTAT +#define TWI0_TXDATA8 +#define TWI0_TXDATA16 +#define TWI0_RXDATA8 +#define TWI0_RXDATA16 +#define TWI1_CLKDIV +#define TWI1_CTL +#define TWI1_SLVCTL +#define TWI1_SLVSTAT +#define TWI1_SLVADDR +#define TWI1_MSTRCTL +#define TWI1_MSTRSTAT +#define TWI1_MSTRADDR +#define TWI1_ISTAT +#define TWI1_IMSK +#define TWI1_FIFOCTL +#define TWI1_FIFOSTAT +#define TWI1_TXDATA8 +#define TWI1_TXDATA16 +#define TWI1_RXDATA8 +#define TWI1_RXDATA16 +#define UART0_REVID +#define UART0_CTL +#define UART0_STAT +#define UART0_SCR +#define UART0_CLK +#define UART0_IMSK +#define UART0_IMSK_SET +#define UART0_IMSK_CLR +#define UART0_RBR +#define UART0_THR +#define UART0_TAIP +#define UART0_TSR +#define UART0_RSR +#define UART0_TXCNT +#define UART0_RXCNT +#define UART1_REVID +#define UART1_CTL +#define UART1_STAT +#define UART1_SCR +#define UART1_CLK +#define UART1_IMSK +#define UART1_IMSK_SET +#define UART1_IMSK_CLR +#define UART1_RBR +#define UART1_THR +#define UART1_TAIP +#define UART1_TSR +#define UART1_RSR +#define UART1_TXCNT +#define UART1_RXCNT +#define PORTA_FER +#define PORTA_FER_SET +#define PORTA_FER_CLR +#define PORTA_DATA +#define PORTA_DATA_SET +#define PORTA_DATA_CLR +#define PORTA_DIR +#define PORTA_DIR_SET +#define PORTA_DIR_CLR +#define PORTA_INEN +#define PORTA_INEN_SET +#define PORTA_INEN_CLR +#define PORTA_MUX +#define PORTA_DATA_TGL +#define PORTA_POL +#define PORTA_POL_SET +#define PORTA_POL_CLR +#define PORTA_LOCK +#define PORTA_REVID +#define PORTB_FER +#define PORTB_FER_SET +#define PORTB_FER_CLR +#define PORTB_DATA +#define PORTB_DATA_SET +#define PORTB_DATA_CLR +#define PORTB_DIR +#define PORTB_DIR_SET +#define PORTB_DIR_CLR +#define PORTB_INEN +#define PORTB_INEN_SET +#define PORTB_INEN_CLR +#define PORTB_MUX +#define PORTB_DATA_TGL +#define PORTB_POL +#define PORTB_POL_SET +#define PORTB_POL_CLR +#define PORTB_LOCK +#define PORTB_REVID +#define PORTC_FER +#define PORTC_FER_SET +#define PORTC_FER_CLR +#define PORTC_DATA +#define PORTC_DATA_SET +#define PORTC_DATA_CLR +#define PORTC_DIR +#define PORTC_DIR_SET +#define PORTC_DIR_CLR +#define PORTC_INEN +#define PORTC_INEN_SET +#define PORTC_INEN_CLR +#define PORTC_MUX +#define PORTC_DATA_TGL +#define PORTC_POL +#define PORTC_POL_SET +#define PORTC_POL_CLR +#define PORTC_LOCK +#define PORTC_REVID +#define PORTD_FER +#define PORTD_FER_SET +#define PORTD_FER_CLR +#define PORTD_DATA +#define PORTD_DATA_SET +#define PORTD_DATA_CLR +#define PORTD_DIR +#define PORTD_DIR_SET +#define PORTD_DIR_CLR +#define PORTD_INEN +#define PORTD_INEN_SET +#define PORTD_INEN_CLR +#define PORTD_MUX +#define PORTD_DATA_TGL +#define PORTD_POL +#define PORTD_POL_SET +#define PORTD_POL_CLR +#define PORTD_LOCK +#define PORTD_REVID +#define PORTE_FER +#define PORTE_FER_SET +#define PORTE_FER_CLR +#define PORTE_DATA +#define PORTE_DATA_SET +#define PORTE_DATA_CLR +#define PORTE_DIR +#define PORTE_DIR_SET +#define PORTE_DIR_CLR +#define PORTE_INEN +#define PORTE_INEN_SET +#define PORTE_INEN_CLR +#define PORTE_MUX +#define PORTE_DATA_TGL +#define PORTE_POL +#define PORTE_POL_SET +#define PORTE_POL_CLR +#define PORTE_LOCK +#define PORTE_REVID +#define PORTF_FER +#define PORTF_FER_SET +#define PORTF_FER_CLR +#define PORTF_DATA +#define PORTF_DATA_SET +#define PORTF_DATA_CLR +#define PORTF_DIR +#define PORTF_DIR_SET +#define PORTF_DIR_CLR +#define PORTF_INEN +#define PORTF_INEN_SET +#define PORTF_INEN_CLR +#define PORTF_MUX +#define PORTF_DATA_TGL +#define PORTF_POL +#define PORTF_POL_SET +#define PORTF_POL_CLR +#define PORTF_LOCK +#define PORTF_REVID +#define PORTG_FER +#define PORTG_FER_SET +#define PORTG_FER_CLR +#define PORTG_DATA +#define PORTG_DATA_SET +#define PORTG_DATA_CLR +#define PORTG_DIR +#define PORTG_DIR_SET +#define PORTG_DIR_CLR +#define PORTG_INEN +#define PORTG_INEN_SET +#define PORTG_INEN_CLR +#define PORTG_MUX +#define PORTG_DATA_TGL +#define PORTG_POL +#define PORTG_POL_SET +#define PORTG_POL_CLR +#define PORTG_LOCK +#define PORTG_REVID +#define PADS0_EMAC_PTP_CLKSEL +#define PADS0_TWI_VSEL +#define PADS0_PORTS_DS +#define PADS0_NONPORTS_DS +#define PADS0_PORTS_HYST +#define PINT0_MSK_SET +#define PINT0_MSK_CLR +#define PINT0_REQ +#define PINT0_ASSIGN +#define PINT0_EDGE_SET +#define PINT0_EDGE_CLR +#define PINT0_INV_SET +#define PINT0_INV_CLR +#define PINT0_PINSTATE +#define PINT0_LATCH +#define PINT1_MSK_SET +#define PINT1_MSK_CLR +#define PINT1_REQ +#define PINT1_ASSIGN +#define PINT1_EDGE_SET +#define PINT1_EDGE_CLR +#define PINT1_INV_SET +#define PINT1_INV_CLR +#define PINT1_PINSTATE +#define PINT1_LATCH +#define PINT2_MSK_SET +#define PINT2_MSK_CLR +#define PINT2_REQ +#define PINT2_ASSIGN +#define PINT2_EDGE_SET +#define PINT2_EDGE_CLR +#define PINT2_INV_SET +#define PINT2_INV_CLR +#define PINT2_PINSTATE +#define PINT2_LATCH +#define PINT3_MSK_SET +#define PINT3_MSK_CLR +#define PINT3_REQ +#define PINT3_ASSIGN +#define PINT3_EDGE_SET +#define PINT3_EDGE_CLR +#define PINT3_INV_SET +#define PINT3_INV_CLR +#define PINT3_PINSTATE +#define PINT3_LATCH +#define PINT4_MSK_SET +#define PINT4_MSK_CLR +#define PINT4_REQ +#define PINT4_ASSIGN +#define PINT4_EDGE_SET +#define PINT4_EDGE_CLR +#define PINT4_INV_SET +#define PINT4_INV_CLR +#define PINT4_PINSTATE +#define PINT4_LATCH +#define PINT5_MSK_SET +#define PINT5_MSK_CLR +#define PINT5_REQ +#define PINT5_ASSIGN +#define PINT5_EDGE_SET +#define PINT5_EDGE_CLR +#define PINT5_INV_SET +#define PINT5_INV_CLR +#define PINT5_PINSTATE +#define PINT5_LATCH +#define SMC_GCTL +#define SMC_GSTAT +#define SMC_B0CTL +#define SMC_B0TIM +#define SMC_B0ETIM +#define SMC_B1CTL +#define SMC_B1TIM +#define SMC_B1ETIM +#define SMC_B2CTL +#define SMC_B2TIM +#define SMC_B2ETIM +#define SMC_B3CTL +#define SMC_B3TIM +#define SMC_B3ETIM +#define WDOG_CTL +#define WDOG_CNT +#define WDOG_STAT +#define WDOG1_CTL +#define WDOG1_CNT +#define WDOG1_STAT +#define EPPI0_STAT +#define EPPI0_HCNT +#define EPPI0_HDLY +#define EPPI0_VCNT +#define EPPI0_VDLY +#define EPPI0_FRAME +#define EPPI0_LINE +#define EPPI0_CLKDIV +#define EPPI0_CTL +#define EPPI0_FS1_WLHB +#define EPPI0_FS1_PASPL +#define EPPI0_FS2_WLVB +#define EPPI0_FS2_PALPF +#define EPPI0_IMSK +#define EPPI0_ODDCLIP +#define EPPI0_EVENCLIP +#define EPPI0_FS1_DLY +#define EPPI0_FS2_DLY +#define EPPI0_CTL2 +#define EPPI1_STAT +#define EPPI1_HCNT +#define EPPI1_HDLY +#define EPPI1_VCNT +#define EPPI1_VDLY +#define EPPI1_FRAME +#define EPPI1_LINE +#define EPPI1_CLKDIV +#define EPPI1_CTL +#define EPPI1_FS1_WLHB +#define EPPI1_FS1_PASPL +#define EPPI1_FS2_WLVB +#define EPPI1_FS2_PALPF +#define EPPI1_IMSK +#define EPPI1_ODDCLIP +#define EPPI1_EVENCLIP +#define EPPI1_FS1_DLY +#define EPPI1_FS2_DLY +#define EPPI1_CTL2 +#define EPPI2_STAT +#define EPPI2_HCNT +#define EPPI2_HDLY +#define EPPI2_VCNT +#define EPPI2_VDLY +#define EPPI2_FRAME +#define EPPI2_LINE +#define EPPI2_CLKDIV +#define EPPI2_CTL +#define EPPI2_FS1_WLHB +#define EPPI2_FS1_PASPL +#define EPPI2_FS2_WLVB +#define EPPI2_FS2_PALPF +#define EPPI2_IMSK +#define EPPI2_ODDCLIP +#define EPPI2_EVENCLIP +#define EPPI2_FS1_DLY +#define EPPI2_FS2_DLY +#define EPPI2_CTL2 +#define PIXC0_CTL +#define PIXC0_PPL +#define PIXC0_LPF +#define PIXC0_HSTART_A +#define PIXC0_HEND_A +#define PIXC0_VSTART_A +#define PIXC0_VEND_A +#define PIXC0_TRANSP_A +#define PIXC0_HSTART_B +#define PIXC0_HEND_B +#define PIXC0_VSTART_B +#define PIXC0_VEND_B +#define PIXC0_TRANSP_B +#define PIXC0_IRQSTAT +#define PIXC0_CONRY +#define PIXC0_CONGU +#define PIXC0_CONBV +#define PIXC0_CCBIAS +#define PIXC0_TC +#define PIXC0_REVID +#define PVP0_REVID +#define PVP0_CTL +#define PVP0_IMSK0 +#define PVP0_IMSK1 +#define PVP0_STAT +#define PVP0_ILAT +#define PVP0_IREQ0 +#define PVP0_IREQ1 +#define PVP0_OPF0_CFG +#define PVP0_OPF1_CFG +#define PVP0_OPF2_CFG +#define PVP0_OPF0_CTL +#define PVP0_OPF1_CTL +#define PVP0_OPF2_CTL +#define PVP0_OPF3_CFG +#define PVP0_OPF3_CTL +#define PVP0_PEC_CFG +#define PVP0_PEC_CTL +#define PVP0_PEC_D1TH0 +#define PVP0_PEC_D1TH1 +#define PVP0_PEC_D2TH0 +#define PVP0_PEC_D2TH1 +#define PVP0_IIM0_CFG +#define PVP0_IIM1_CFG +#define PVP0_IIM0_CTL +#define PVP0_IIM1_CTL +#define PVP0_IIM0_SCALE +#define PVP0_IIM1_SCALE +#define PVP0_IIM0_SOVF_STAT +#define PVP0_IIM1_SOVF_STAT +#define PVP0_IIM0_UOVF_STAT +#define PVP0_IIM1_UOVF_STAT +#define PVP0_ACU_CFG +#define PVP0_ACU_CTL +#define PVP0_ACU_OFFSET +#define PVP0_ACU_FACTOR +#define PVP0_ACU_SHIFT +#define PVP0_ACU_MIN +#define PVP0_ACU_MAX +#define PVP0_UDS_CFG +#define PVP0_UDS_CTL +#define PVP0_UDS_OHCNT +#define PVP0_UDS_OVCNT +#define PVP0_UDS_HAVG +#define PVP0_UDS_VAVG +#define PVP0_IPF0_CFG +#define PVP0_IPF0_PIPECTL +#define PVP0_IPF1_PIPECTL +#define PVP0_IPF0_CTL +#define PVP0_IPF1_CTL +#define PVP0_IPF0_TAG +#define PVP0_IPF1_TAG +#define PVP0_IPF0_FCNT +#define PVP0_IPF1_FCNT +#define PVP0_IPF0_HCNT +#define PVP0_IPF1_HCNT +#define PVP0_IPF0_VCNT +#define PVP0_IPF1_VCNT +#define PVP0_IPF0_HPOS +#define PVP0_IPF0_VPOS +#define PVP0_IPF0_TAG_STAT +#define PVP0_IPF1_TAG_STAT +#define PVP0_IPF1_CFG +#define PVP0_CNV0_CFG +#define PVP0_CNV1_CFG +#define PVP0_CNV2_CFG +#define PVP0_CNV3_CFG +#define PVP0_CNV0_CTL +#define PVP0_CNV1_CTL +#define PVP0_CNV2_CTL +#define PVP0_CNV3_CTL +#define PVP0_CNV0_C00C01 +#define PVP0_CNV1_C00C01 +#define PVP0_CNV2_C00C01 +#define PVP0_CNV3_C00C01 +#define PVP0_CNV0_C02C03 +#define PVP0_CNV1_C02C03 +#define PVP0_CNV2_C02C03 +#define PVP0_CNV3_C02C03 +#define PVP0_CNV0_C04 +#define PVP0_CNV1_C04 +#define PVP0_CNV2_C04 +#define PVP0_CNV3_C04 +#define PVP0_CNV0_C10C11 +#define PVP0_CNV1_C10C11 +#define PVP0_CNV2_C10C11 +#define PVP0_CNV3_C10C11 +#define PVP0_CNV0_C12C13 +#define PVP0_CNV1_C12C13 +#define PVP0_CNV2_C12C13 +#define PVP0_CNV3_C12C13 +#define PVP0_CNV0_C14 +#define PVP0_CNV1_C14 +#define PVP0_CNV2_C14 +#define PVP0_CNV3_C14 +#define PVP0_CNV0_C20C21 +#define PVP0_CNV1_C20C21 +#define PVP0_CNV2_C20C21 +#define PVP0_CNV3_C20C21 +#define PVP0_CNV0_C22C23 +#define PVP0_CNV1_C22C23 +#define PVP0_CNV2_C22C23 +#define PVP0_CNV3_C22C23 +#define PVP0_CNV0_C24 +#define PVP0_CNV1_C24 +#define PVP0_CNV2_C24 +#define PVP0_CNV3_C24 +#define PVP0_CNV0_C30C31 +#define PVP0_CNV1_C30C31 +#define PVP0_CNV2_C30C31 +#define PVP0_CNV3_C30C31 +#define PVP0_CNV0_C32C33 +#define PVP0_CNV1_C32C33 +#define PVP0_CNV2_C32C33 +#define PVP0_CNV3_C32C33 +#define PVP0_CNV0_C34 +#define PVP0_CNV1_C34 +#define PVP0_CNV2_C34 +#define PVP0_CNV3_C34 +#define PVP0_CNV0_C40C41 +#define PVP0_CNV1_C40C41 +#define PVP0_CNV2_C40C41 +#define PVP0_CNV3_C40C41 +#define PVP0_CNV0_C42C43 +#define PVP0_CNV1_C42C43 +#define PVP0_CNV2_C42C43 +#define PVP0_CNV3_C42C43 +#define PVP0_CNV0_C44 +#define PVP0_CNV1_C44 +#define PVP0_CNV2_C44 +#define PVP0_CNV3_C44 +#define PVP0_CNV0_SCALE +#define PVP0_CNV1_SCALE +#define PVP0_CNV2_SCALE +#define PVP0_CNV3_SCALE +#define PVP0_THC0_CFG +#define PVP0_THC1_CFG +#define PVP0_THC0_CTL +#define PVP0_THC1_CTL +#define PVP0_THC0_HFCNT +#define PVP0_THC1_HFCNT +#define PVP0_THC0_RMAXREP +#define PVP0_THC1_RMAXREP +#define PVP0_THC0_CMINVAL +#define PVP0_THC1_CMINVAL +#define PVP0_THC0_CMINTH +#define PVP0_THC1_CMINTH +#define PVP0_THC0_CMAXTH +#define PVP0_THC1_CMAXTH +#define PVP0_THC0_CMAXVAL +#define PVP0_THC1_CMAXVAL +#define PVP0_THC0_TH0 +#define PVP0_THC1_TH0 +#define PVP0_THC0_TH1 +#define PVP0_THC1_TH1 +#define PVP0_THC0_TH2 +#define PVP0_THC1_TH2 +#define PVP0_THC0_TH3 +#define PVP0_THC1_TH3 +#define PVP0_THC0_TH4 +#define PVP0_THC1_TH4 +#define PVP0_THC0_TH5 +#define PVP0_THC1_TH5 +#define PVP0_THC0_TH6 +#define PVP0_THC1_TH6 +#define PVP0_THC0_TH7 +#define PVP0_THC1_TH7 +#define PVP0_THC0_TH8 +#define PVP0_THC1_TH8 +#define PVP0_THC0_TH9 +#define PVP0_THC1_TH9 +#define PVP0_THC0_TH10 +#define PVP0_THC1_TH10 +#define PVP0_THC0_TH11 +#define PVP0_THC1_TH11 +#define PVP0_THC0_TH12 +#define PVP0_THC1_TH12 +#define PVP0_THC0_TH13 +#define PVP0_THC1_TH13 +#define PVP0_THC0_TH14 +#define PVP0_THC1_TH14 +#define PVP0_THC0_TH15 +#define PVP0_THC1_TH15 +#define PVP0_THC0_HHPOS +#define PVP0_THC1_HHPOS +#define PVP0_THC0_HVPOS +#define PVP0_THC1_HVPOS +#define PVP0_THC0_HHCNT +#define PVP0_THC1_HHCNT +#define PVP0_THC0_HVCNT +#define PVP0_THC1_HVCNT +#define PVP0_THC0_RHPOS +#define PVP0_THC1_RHPOS +#define PVP0_THC0_RVPOS +#define PVP0_THC1_RVPOS +#define PVP0_THC0_RHCNT +#define PVP0_THC1_RHCNT +#define PVP0_THC0_RVCNT +#define PVP0_THC1_RVCNT +#define PVP0_THC0_HFCNT_STAT +#define PVP0_THC1_HFCNT_STAT +#define PVP0_THC0_HCNT0_STAT +#define PVP0_THC1_HCNT0_STAT +#define PVP0_THC0_HCNT1_STAT +#define PVP0_THC1_HCNT1_STAT +#define PVP0_THC0_HCNT2_STAT +#define PVP0_THC1_HCNT2_STAT +#define PVP0_THC0_HCNT3_STAT +#define PVP0_THC1_HCNT3_STAT +#define PVP0_THC0_HCNT4_STAT +#define PVP0_THC1_HCNT4_STAT +#define PVP0_THC0_HCNT5_STAT +#define PVP0_THC1_HCNT5_STAT +#define PVP0_THC0_HCNT6_STAT +#define PVP0_THC1_HCNT6_STAT +#define PVP0_THC0_HCNT7_STAT +#define PVP0_THC1_HCNT7_STAT +#define PVP0_THC0_HCNT8_STAT +#define PVP0_THC1_HCNT8_STAT +#define PVP0_THC0_HCNT9_STAT +#define PVP0_THC1_HCNT9_STAT +#define PVP0_THC0_HCNT10_STAT +#define PVP0_THC1_HCNT10_STAT +#define PVP0_THC0_HCNT11_STAT +#define PVP0_THC1_HCNT11_STAT +#define PVP0_THC0_HCNT12_STAT +#define PVP0_THC1_HCNT12_STAT +#define PVP0_THC0_HCNT13_STAT +#define PVP0_THC1_HCNT13_STAT +#define PVP0_THC0_HCNT14_STAT +#define PVP0_THC1_HCNT14_STAT +#define PVP0_THC0_HCNT15_STAT +#define PVP0_THC1_HCNT15_STAT +#define PVP0_THC0_RREP_STAT +#define PVP0_THC1_RREP_STAT +#define PVP0_PMA_CFG +#define PWM0_CTL +#define PWM0_CHANCFG +#define PWM0_TRIPCFG +#define PWM0_STAT +#define PWM0_IMSK +#define PWM0_ILAT +#define PWM0_CHOPCFG +#define PWM0_DT +#define PWM0_SYNC_WID +#define PWM0_TM0 +#define PWM0_TM1 +#define PWM0_TM2 +#define PWM0_TM3 +#define PWM0_TM4 +#define PWM0_DLYA +#define PWM0_DLYB +#define PWM0_DLYC +#define PWM0_DLYD +#define PWM0_ACTL +#define PWM0_AH0 +#define PWM0_AH1 +#define PWM0_AH0_HP +#define PWM0_AH1_HP +#define PWM0_AL0 +#define PWM0_AL1 +#define PWM0_BCTL +#define PWM0_BH0 +#define PWM0_BH1 +#define PWM0_BH0_HP +#define PWM0_BH1_HP +#define PWM0_BL0 +#define PWM0_BL1 +#define PWM0_CCTL +#define PWM0_CH0 +#define PWM0_CH1 +#define PWM0_CH0_HP +#define PWM0_CH1_HP +#define PWM0_CL0 +#define PWM0_CL1 +#define PWM0_DCTL +#define PWM0_DH0 +#define PWM0_DH1 +#define PWM0_DH0_HP +#define PWM0_DH1_HP +#define PWM0_DL0 +#define PWM0_DL1 +#define PWM0_REVID +#define PWM1_CTL +#define PWM1_CHANCFG +#define PWM1_TRIPCFG +#define PWM1_STAT +#define PWM1_IMSK +#define PWM1_ILAT +#define PWM1_CHOPCFG +#define PWM1_DT +#define PWM1_SYNC_WID +#define PWM1_TM0 +#define PWM1_TM1 +#define PWM1_TM2 +#define PWM1_TM3 +#define PWM1_TM4 +#define PWM1_DLYA +#define PWM1_DLYB +#define PWM1_DLYC +#define PWM1_DLYD +#define PWM1_ACTL +#define PWM1_AH0 +#define PWM1_AH1 +#define PWM1_AH0_HP +#define PWM1_AH1_HP +#define PWM1_AL0 +#define PWM1_AL1 +#define PWM1_BCTL +#define PWM1_BH0 +#define PWM1_BH1 +#define PWM1_BH0_HP +#define PWM1_BH1_HP +#define PWM1_BL0 +#define PWM1_BL1 +#define PWM1_CCTL +#define PWM1_CH0 +#define PWM1_CH1 +#define PWM1_CH0_HP +#define PWM1_CH1_HP +#define PWM1_CL0 +#define PWM1_CL1 +#define PWM1_DCTL +#define PWM1_DH0 +#define PWM1_DH1 +#define PWM1_DH0_HP +#define PWM1_DH1_HP +#define PWM1_DL0 +#define PWM1_DL1 +#define PWM1_REVID +#define VID0_CONN +#define SWU0_GCTL +#define SWU0_GSTAT +#define SWU0_CTL0 +#define SWU0_CTL1 +#define SWU0_CTL2 +#define SWU0_CTL3 +#define SWU0_LA0 +#define SWU0_LA1 +#define SWU0_LA2 +#define SWU0_LA3 +#define SWU0_UA0 +#define SWU0_UA1 +#define SWU0_UA2 +#define SWU0_UA3 +#define SWU0_ID0 +#define SWU0_ID1 +#define SWU0_ID2 +#define SWU0_ID3 +#define SWU0_CNT0 +#define SWU0_CNT1 +#define SWU0_CNT2 +#define SWU0_CNT3 +#define SWU0_TARG0 +#define SWU0_TARG1 +#define SWU0_TARG2 +#define SWU0_TARG3 +#define SWU0_HIST0 +#define SWU0_HIST1 +#define SWU0_HIST2 +#define SWU0_HIST3 +#define SWU0_CUR0 +#define SWU0_CUR1 +#define SWU0_CUR2 +#define SWU0_CUR3 +#define SWU1_GCTL +#define SWU1_GSTAT +#define SWU1_CTL0 +#define SWU1_CTL1 +#define SWU1_CTL2 +#define SWU1_CTL3 +#define SWU1_LA0 +#define SWU1_LA1 +#define SWU1_LA2 +#define SWU1_LA3 +#define SWU1_UA0 +#define SWU1_UA1 +#define SWU1_UA2 +#define SWU1_UA3 +#define SWU1_ID0 +#define SWU1_ID1 +#define SWU1_ID2 +#define SWU1_ID3 +#define SWU1_CNT0 +#define SWU1_CNT1 +#define SWU1_CNT2 +#define SWU1_CNT3 +#define SWU1_TARG0 +#define SWU1_TARG1 +#define SWU1_TARG2 +#define SWU1_TARG3 +#define SWU1_HIST0 +#define SWU1_HIST1 +#define SWU1_HIST2 +#define SWU1_HIST3 +#define SWU1_CUR0 +#define SWU1_CUR1 +#define SWU1_CUR2 +#define SWU1_CUR3 +#define SWU2_GCTL +#define SWU2_GSTAT +#define SWU2_CTL0 +#define SWU2_CTL1 +#define SWU2_CTL2 +#define SWU2_CTL3 +#define SWU2_LA0 +#define SWU2_LA1 +#define SWU2_LA2 +#define SWU2_LA3 +#define SWU2_UA0 +#define SWU2_UA1 +#define SWU2_UA2 +#define SWU2_UA3 +#define SWU2_ID0 +#define SWU2_ID1 +#define SWU2_ID2 +#define SWU2_ID3 +#define SWU2_CNT0 +#define SWU2_CNT1 +#define SWU2_CNT2 +#define SWU2_CNT3 +#define SWU2_TARG0 +#define SWU2_TARG1 +#define SWU2_TARG2 +#define SWU2_TARG3 +#define SWU2_HIST0 +#define SWU2_HIST1 +#define SWU2_HIST2 +#define SWU2_HIST3 +#define SWU2_CUR0 +#define SWU2_CUR1 +#define SWU2_CUR2 +#define SWU2_CUR3 +#define SWU3_GCTL +#define SWU3_GSTAT +#define SWU3_CTL0 +#define SWU3_CTL1 +#define SWU3_CTL2 +#define SWU3_CTL3 +#define SWU3_LA0 +#define SWU3_LA1 +#define SWU3_LA2 +#define SWU3_LA3 +#define SWU3_UA0 +#define SWU3_UA1 +#define SWU3_UA2 +#define SWU3_UA3 +#define SWU3_ID0 +#define SWU3_ID1 +#define SWU3_ID2 +#define SWU3_ID3 +#define SWU3_CNT0 +#define SWU3_CNT1 +#define SWU3_CNT2 +#define SWU3_CNT3 +#define SWU3_TARG0 +#define SWU3_TARG1 +#define SWU3_TARG2 +#define SWU3_TARG3 +#define SWU3_HIST0 +#define SWU3_HIST1 +#define SWU3_HIST2 +#define SWU3_HIST3 +#define SWU3_CUR0 +#define SWU3_CUR1 +#define SWU3_CUR2 +#define SWU3_CUR3 +#define SWU4_GCTL +#define SWU4_GSTAT +#define SWU4_CTL0 +#define SWU4_CTL1 +#define SWU4_CTL2 +#define SWU4_CTL3 +#define SWU4_LA0 +#define SWU4_LA1 +#define SWU4_LA2 +#define SWU4_LA3 +#define SWU4_UA0 +#define SWU4_UA1 +#define SWU4_UA2 +#define SWU4_UA3 +#define SWU4_ID0 +#define SWU4_ID1 +#define SWU4_ID2 +#define SWU4_ID3 +#define SWU4_CNT0 +#define SWU4_CNT1 +#define SWU4_CNT2 +#define SWU4_CNT3 +#define SWU4_TARG0 +#define SWU4_TARG1 +#define SWU4_TARG2 +#define SWU4_TARG3 +#define SWU4_HIST0 +#define SWU4_HIST1 +#define SWU4_HIST2 +#define SWU4_HIST3 +#define SWU4_CUR0 +#define SWU4_CUR1 +#define SWU4_CUR2 +#define SWU4_CUR3 +#define SWU5_GCTL +#define SWU5_GSTAT +#define SWU5_CTL0 +#define SWU5_CTL1 +#define SWU5_CTL2 +#define SWU5_CTL3 +#define SWU5_LA0 +#define SWU5_LA1 +#define SWU5_LA2 +#define SWU5_LA3 +#define SWU5_UA0 +#define SWU5_UA1 +#define SWU5_UA2 +#define SWU5_UA3 +#define SWU5_ID0 +#define SWU5_ID1 +#define SWU5_ID2 +#define SWU5_ID3 +#define SWU5_CNT0 +#define SWU5_CNT1 +#define SWU5_CNT2 +#define SWU5_CNT3 +#define SWU5_TARG0 +#define SWU5_TARG1 +#define SWU5_TARG2 +#define SWU5_TARG3 +#define SWU5_HIST0 +#define SWU5_HIST1 +#define SWU5_HIST2 +#define SWU5_HIST3 +#define SWU5_CUR0 +#define SWU5_CUR1 +#define SWU5_CUR2 +#define SWU5_CUR3 +#define SWU6_GCTL +#define SWU6_GSTAT +#define SWU6_CTL0 +#define SWU6_CTL1 +#define SWU6_CTL2 +#define SWU6_CTL3 +#define SWU6_LA0 +#define SWU6_LA1 +#define SWU6_LA2 +#define SWU6_LA3 +#define SWU6_UA0 +#define SWU6_UA1 +#define SWU6_UA2 +#define SWU6_UA3 +#define SWU6_ID0 +#define SWU6_ID1 +#define SWU6_ID2 +#define SWU6_ID3 +#define SWU6_CNT0 +#define SWU6_CNT1 +#define SWU6_CNT2 +#define SWU6_CNT3 +#define SWU6_TARG0 +#define SWU6_TARG1 +#define SWU6_TARG2 +#define SWU6_TARG3 +#define SWU6_HIST0 +#define SWU6_HIST1 +#define SWU6_HIST2 +#define SWU6_HIST3 +#define SWU6_CUR0 +#define SWU6_CUR1 +#define SWU6_CUR2 +#define SWU6_CUR3 +#define SDU0_IDCODE +#define SDU0_CTL +#define SDU0_STAT +#define SDU0_MACCTL +#define SDU0_MACADDR +#define SDU0_MACDATA +#define SDU0_DMARD +#define SDU0_DMAWD +#define SDU0_MSG +#define SDU0_MSG_SET +#define SDU0_MSG_CLR +#define SDU0_GHLT +#define EMAC0_MACCFG +#define EMAC0_MACFRMFILT +#define EMAC0_HASHTBL_HI +#define EMAC0_HASHTBL_LO +#define EMAC0_GMII_ADDR +#define EMAC0_GMII_DATA +#define EMAC0_FLOWCTL +#define EMAC0_VLANTAG +#define EMAC0_VER +#define EMAC0_DBG +#define EMAC0_RMTWKUP +#define EMAC0_PMT_CTLSTAT +#define EMAC0_ISTAT +#define EMAC0_IMSK +#define EMAC0_ADDR0_HI +#define EMAC0_ADDR0_LO +#define EMAC0_MMC_CTL +#define EMAC0_MMC_RXINT +#define EMAC0_MMC_TXINT +#define EMAC0_MMC_RXIMSK +#define EMAC0_MMC_TXIMSK +#define EMAC0_TXOCTCNT_GB +#define EMAC0_TXFRMCNT_GB +#define EMAC0_TXBCASTFRM_G +#define EMAC0_TXMCASTFRM_G +#define EMAC0_TX64_GB +#define EMAC0_TX65TO127_GB +#define EMAC0_TX128TO255_GB +#define EMAC0_TX256TO511_GB +#define EMAC0_TX512TO1023_GB +#define EMAC0_TX1024TOMAX_GB +#define EMAC0_TXUCASTFRM_GB +#define EMAC0_TXMCASTFRM_GB +#define EMAC0_TXBCASTFRM_GB +#define EMAC0_TXUNDR_ERR +#define EMAC0_TXSNGCOL_G +#define EMAC0_TXMULTCOL_G +#define EMAC0_TXDEFERRED +#define EMAC0_TXLATECOL +#define EMAC0_TXEXCESSCOL +#define EMAC0_TXCARR_ERR +#define EMAC0_TXOCTCNT_G +#define EMAC0_TXFRMCNT_G +#define EMAC0_TXEXCESSDEF +#define EMAC0_TXPAUSEFRM +#define EMAC0_TXVLANFRM_G +#define EMAC0_RXFRMCNT_GB +#define EMAC0_RXOCTCNT_GB +#define EMAC0_RXOCTCNT_G +#define EMAC0_RXBCASTFRM_G +#define EMAC0_RXMCASTFRM_G +#define EMAC0_RXCRC_ERR +#define EMAC0_RXALIGN_ERR +#define EMAC0_RXRUNT_ERR +#define EMAC0_RXJAB_ERR +#define EMAC0_RXUSIZE_G +#define EMAC0_RXOSIZE_G +#define EMAC0_RX64_GB +#define EMAC0_RX65TO127_GB +#define EMAC0_RX128TO255_GB +#define EMAC0_RX256TO511_GB +#define EMAC0_RX512TO1023_GB +#define EMAC0_RX1024TOMAX_GB +#define EMAC0_RXUCASTFRM_G +#define EMAC0_RXLEN_ERR +#define EMAC0_RXOORTYPE +#define EMAC0_RXPAUSEFRM +#define EMAC0_RXFIFO_OVF +#define EMAC0_RXVLANFRM_GB +#define EMAC0_RXWDOG_ERR +#define EMAC0_IPC_RXIMSK +#define EMAC0_IPC_RXINT +#define EMAC0_RXIPV4_GD_FRM +#define EMAC0_RXIPV4_HDR_ERR_FRM +#define EMAC0_RXIPV4_NOPAY_FRM +#define EMAC0_RXIPV4_FRAG_FRM +#define EMAC0_RXIPV4_UDSBL_FRM +#define EMAC0_RXIPV6_GD_FRM +#define EMAC0_RXIPV6_HDR_ERR_FRM +#define EMAC0_RXIPV6_NOPAY_FRM +#define EMAC0_RXUDP_GD_FRM +#define EMAC0_RXUDP_ERR_FRM +#define EMAC0_RXTCP_GD_FRM +#define EMAC0_RXTCP_ERR_FRM +#define EMAC0_RXICMP_GD_FRM +#define EMAC0_RXICMP_ERR_FRM +#define EMAC0_RXIPV4_GD_OCT +#define EMAC0_RXIPV4_HDR_ERR_OCT +#define EMAC0_RXIPV4_NOPAY_OCT +#define EMAC0_RXIPV4_FRAG_OCT +#define EMAC0_RXIPV4_UDSBL_OCT +#define EMAC0_RXIPV6_GD_OCT +#define EMAC0_RXIPV6_HDR_ERR_OCT +#define EMAC0_RXIPV6_NOPAY_OCT +#define EMAC0_RXUDP_GD_OCT +#define EMAC0_RXUDP_ERR_OCT +#define EMAC0_RXTCP_GD_OCT +#define EMAC0_RXTCP_ERR_OCT +#define EMAC0_RXICMP_GD_OCT +#define EMAC0_RXICMP_ERR_OCT +#define EMAC0_TM_CTL +#define EMAC0_TM_SUBSEC +#define EMAC0_TM_SEC +#define EMAC0_TM_NSEC +#define EMAC0_TM_SECUPDT +#define EMAC0_TM_NSECUPDT +#define EMAC0_TM_ADDEND +#define EMAC0_TM_TGTM +#define EMAC0_TM_NTGTM +#define EMAC0_TM_HISEC +#define EMAC0_TM_STMPSTAT +#define EMAC0_TM_PPSCTL +#define EMAC0_TM_AUXSTMP_NSEC +#define EMAC0_TM_AUXSTMP_SEC +#define EMAC0_DMA_BUSMODE +#define EMAC0_DMA_TXPOLL +#define EMAC0_DMA_RXPOLL +#define EMAC0_DMA_RXDSC_ADDR +#define EMAC0_DMA_TXDSC_ADDR +#define EMAC0_DMA_STAT +#define EMAC0_DMA_OPMODE +#define EMAC0_DMA_IEN +#define EMAC0_DMA_MISS_FRM +#define EMAC0_DMA_RXIWDOG +#define EMAC0_DMA_BMMODE +#define EMAC0_DMA_BMSTAT +#define EMAC0_DMA_TXDSC_CUR +#define EMAC0_DMA_RXDSC_CUR +#define EMAC0_DMA_TXBUF_CUR +#define EMAC0_DMA_RXBUF_CUR +#define EMAC0_HWFEAT +#define EMAC1_MACCFG +#define EMAC1_MACFRMFILT +#define EMAC1_HASHTBL_HI +#define EMAC1_HASHTBL_LO +#define EMAC1_GMII_ADDR +#define EMAC1_GMII_DATA +#define EMAC1_FLOWCTL +#define EMAC1_VLANTAG +#define EMAC1_VER +#define EMAC1_DBG +#define EMAC1_RMTWKUP +#define EMAC1_PMT_CTLSTAT +#define EMAC1_ISTAT +#define EMAC1_IMSK +#define EMAC1_ADDR0_HI +#define EMAC1_ADDR0_LO +#define EMAC1_MMC_CTL +#define EMAC1_MMC_RXINT +#define EMAC1_MMC_TXINT +#define EMAC1_MMC_RXIMSK +#define EMAC1_MMC_TXIMSK +#define EMAC1_TXOCTCNT_GB +#define EMAC1_TXFRMCNT_GB +#define EMAC1_TXBCASTFRM_G +#define EMAC1_TXMCASTFRM_G +#define EMAC1_TX64_GB +#define EMAC1_TX65TO127_GB +#define EMAC1_TX128TO255_GB +#define EMAC1_TX256TO511_GB +#define EMAC1_TX512TO1023_GB +#define EMAC1_TX1024TOMAX_GB +#define EMAC1_TXUCASTFRM_GB +#define EMAC1_TXMCASTFRM_GB +#define EMAC1_TXBCASTFRM_GB +#define EMAC1_TXUNDR_ERR +#define EMAC1_TXSNGCOL_G +#define EMAC1_TXMULTCOL_G +#define EMAC1_TXDEFERRED +#define EMAC1_TXLATECOL +#define EMAC1_TXEXCESSCOL +#define EMAC1_TXCARR_ERR +#define EMAC1_TXOCTCNT_G +#define EMAC1_TXFRMCNT_G +#define EMAC1_TXEXCESSDEF +#define EMAC1_TXPAUSEFRM +#define EMAC1_TXVLANFRM_G +#define EMAC1_RXFRMCNT_GB +#define EMAC1_RXOCTCNT_GB +#define EMAC1_RXOCTCNT_G +#define EMAC1_RXBCASTFRM_G +#define EMAC1_RXMCASTFRM_G +#define EMAC1_RXCRC_ERR +#define EMAC1_RXALIGN_ERR +#define EMAC1_RXRUNT_ERR +#define EMAC1_RXJAB_ERR +#define EMAC1_RXUSIZE_G +#define EMAC1_RXOSIZE_G +#define EMAC1_RX64_GB +#define EMAC1_RX65TO127_GB +#define EMAC1_RX128TO255_GB +#define EMAC1_RX256TO511_GB +#define EMAC1_RX512TO1023_GB +#define EMAC1_RX1024TOMAX_GB +#define EMAC1_RXUCASTFRM_G +#define EMAC1_RXLEN_ERR +#define EMAC1_RXOORTYPE +#define EMAC1_RXPAUSEFRM +#define EMAC1_RXFIFO_OVF +#define EMAC1_RXVLANFRM_GB +#define EMAC1_RXWDOG_ERR +#define EMAC1_IPC_RXIMSK +#define EMAC1_IPC_RXINT +#define EMAC1_RXIPV4_GD_FRM +#define EMAC1_RXIPV4_HDR_ERR_FRM +#define EMAC1_RXIPV4_NOPAY_FRM +#define EMAC1_RXIPV4_FRAG_FRM +#define EMAC1_RXIPV4_UDSBL_FRM +#define EMAC1_RXIPV6_GD_FRM +#define EMAC1_RXIPV6_HDR_ERR_FRM +#define EMAC1_RXIPV6_NOPAY_FRM +#define EMAC1_RXUDP_GD_FRM +#define EMAC1_RXUDP_ERR_FRM +#define EMAC1_RXTCP_GD_FRM +#define EMAC1_RXTCP_ERR_FRM +#define EMAC1_RXICMP_GD_FRM +#define EMAC1_RXICMP_ERR_FRM +#define EMAC1_RXIPV4_GD_OCT +#define EMAC1_RXIPV4_HDR_ERR_OCT +#define EMAC1_RXIPV4_NOPAY_OCT +#define EMAC1_RXIPV4_FRAG_OCT +#define EMAC1_RXIPV4_UDSBL_OCT +#define EMAC1_RXIPV6_GD_OCT +#define EMAC1_RXIPV6_HDR_ERR_OCT +#define EMAC1_RXIPV6_NOPAY_OCT +#define EMAC1_RXUDP_GD_OCT +#define EMAC1_RXUDP_ERR_OCT +#define EMAC1_RXTCP_GD_OCT +#define EMAC1_RXTCP_ERR_OCT +#define EMAC1_RXICMP_GD_OCT +#define EMAC1_RXICMP_ERR_OCT +#define EMAC1_TM_CTL +#define EMAC1_TM_SUBSEC +#define EMAC1_TM_SEC +#define EMAC1_TM_NSEC +#define EMAC1_TM_SECUPDT +#define EMAC1_TM_NSECUPDT +#define EMAC1_TM_ADDEND +#define EMAC1_TM_TGTM +#define EMAC1_TM_NTGTM +#define EMAC1_TM_HISEC +#define EMAC1_TM_STMPSTAT +#define EMAC1_TM_PPSCTL +#define EMAC1_TM_AUXSTMP_NSEC +#define EMAC1_TM_AUXSTMP_SEC +#define EMAC1_DMA_BUSMODE +#define EMAC1_DMA_TXPOLL +#define EMAC1_DMA_RXPOLL +#define EMAC1_DMA_RXDSC_ADDR +#define EMAC1_DMA_TXDSC_ADDR +#define EMAC1_DMA_STAT +#define EMAC1_DMA_OPMODE +#define EMAC1_DMA_IEN +#define EMAC1_DMA_MISS_FRM +#define EMAC1_DMA_RXIWDOG +#define EMAC1_DMA_BMMODE +#define EMAC1_DMA_BMSTAT +#define EMAC1_DMA_TXDSC_CUR +#define EMAC1_DMA_RXDSC_CUR +#define EMAC1_DMA_TXBUF_CUR +#define EMAC1_DMA_RXBUF_CUR +#define EMAC1_HWFEAT +#define SPORT0_CTL_A +#define SPORT0_DIV_A +#define SPORT0_MCTL_A +#define SPORT0_CS0_A +#define SPORT0_CS1_A +#define SPORT0_CS2_A +#define SPORT0_CS3_A +#define SPORT0_CNT_A +#define SPORT0_ERR_A +#define SPORT0_MSTAT_A +#define SPORT0_CTL2_A +#define SPORT0_TXPRI_A +#define SPORT0_RXPRI_A +#define SPORT0_TXSEC_A +#define SPORT0_RXSEC_A +#define SPORT0_CTL_B +#define SPORT0_DIV_B +#define SPORT0_MCTL_B +#define SPORT0_CS0_B +#define SPORT0_CS1_B +#define SPORT0_CS2_B +#define SPORT0_CS3_B +#define SPORT0_CNT_B +#define SPORT0_ERR_B +#define SPORT0_MSTAT_B +#define SPORT0_CTL2_B +#define SPORT0_TXPRI_B +#define SPORT0_RXPRI_B +#define SPORT0_TXSEC_B +#define SPORT0_RXSEC_B +#define SPORT1_CTL_A +#define SPORT1_DIV_A +#define SPORT1_MCTL_A +#define SPORT1_CS0_A +#define SPORT1_CS1_A +#define SPORT1_CS2_A +#define SPORT1_CS3_A +#define SPORT1_CNT_A +#define SPORT1_ERR_A +#define SPORT1_MSTAT_A +#define SPORT1_CTL2_A +#define SPORT1_TXPRI_A +#define SPORT1_RXPRI_A +#define SPORT1_TXSEC_A +#define SPORT1_RXSEC_A +#define SPORT1_CTL_B +#define SPORT1_DIV_B +#define SPORT1_MCTL_B +#define SPORT1_CS0_B +#define SPORT1_CS1_B +#define SPORT1_CS2_B +#define SPORT1_CS3_B +#define SPORT1_CNT_B +#define SPORT1_ERR_B +#define SPORT1_MSTAT_B +#define SPORT1_CTL2_B +#define SPORT1_TXPRI_B +#define SPORT1_RXPRI_B +#define SPORT1_TXSEC_B +#define SPORT1_RXSEC_B +#define SPORT2_CTL_A +#define SPORT2_DIV_A +#define SPORT2_MCTL_A +#define SPORT2_CS0_A +#define SPORT2_CS1_A +#define SPORT2_CS2_A +#define SPORT2_CS3_A +#define SPORT2_CNT_A +#define SPORT2_ERR_A +#define SPORT2_MSTAT_A +#define SPORT2_CTL2_A +#define SPORT2_TXPRI_A +#define SPORT2_RXPRI_A +#define SPORT2_TXSEC_A +#define SPORT2_RXSEC_A +#define SPORT2_CTL_B +#define SPORT2_DIV_B +#define SPORT2_MCTL_B +#define SPORT2_CS0_B +#define SPORT2_CS1_B +#define SPORT2_CS2_B +#define SPORT2_CS3_B +#define SPORT2_CNT_B +#define SPORT2_ERR_B +#define SPORT2_MSTAT_B +#define SPORT2_CTL2_B +#define SPORT2_TXPRI_B +#define SPORT2_RXPRI_B +#define SPORT2_TXSEC_B +#define SPORT2_RXSEC_B +#define SPI0_REGBASE +#define SPI0_CTL +#define SPI0_RXCTL +#define SPI0_TXCTL +#define SPI0_CLK +#define SPI0_DLY +#define SPI0_SLVSEL +#define SPI0_RWC +#define SPI0_RWCR +#define SPI0_TWC +#define SPI0_TWCR +#define SPI0_IMSK +#define SPI0_IMSK_CLR +#define SPI0_IMSK_SET +#define SPI0_STAT +#define SPI0_ILAT +#define SPI0_ILAT_CLR +#define SPI0_RFIFO +#define SPI0_TFIFO +#define SPI1_REGBASE +#define SPI1_CTL +#define SPI1_RXCTL +#define SPI1_TXCTL +#define SPI1_CLK +#define SPI1_DLY +#define SPI1_SLVSEL +#define SPI1_RWC +#define SPI1_RWCR +#define SPI1_TWC +#define SPI1_TWCR +#define SPI1_IMSK +#define SPI1_IMSK_CLR +#define SPI1_IMSK_SET +#define SPI1_STAT +#define SPI1_ILAT +#define SPI1_ILAT_CLR +#define SPI1_RFIFO +#define SPI1_TFIFO +#define DMA0_DSCPTR_NXT +#define DMA0_ADDRSTART +#define DMA0_CFG +#define DMA0_XCNT +#define DMA0_XMOD +#define DMA0_YCNT +#define DMA0_YMOD +#define DMA0_DSCPTR_CUR +#define DMA0_DSCPTR_PRV +#define DMA0_ADDR_CUR +#define DMA0_STAT +#define DMA0_XCNT_CUR +#define DMA0_YCNT_CUR +#define DMA0_BWLCNT +#define DMA0_BWLCNT_CUR +#define DMA0_BWMCNT +#define DMA0_BWMCNT_CUR +#define DMA1_DSCPTR_NXT +#define DMA1_ADDRSTART +#define DMA1_CFG +#define DMA1_XCNT +#define DMA1_XMOD +#define DMA1_YCNT +#define DMA1_YMOD +#define DMA1_DSCPTR_CUR +#define DMA1_DSCPTR_PRV +#define DMA1_ADDR_CUR +#define DMA1_STAT +#define DMA1_XCNT_CUR +#define DMA1_YCNT_CUR +#define DMA1_BWLCNT +#define DMA1_BWLCNT_CUR +#define DMA1_BWMCNT +#define DMA1_BWMCNT_CUR +#define DMA2_DSCPTR_NXT +#define DMA2_ADDRSTART +#define DMA2_CFG +#define DMA2_XCNT +#define DMA2_XMOD +#define DMA2_YCNT +#define DMA2_YMOD +#define DMA2_DSCPTR_CUR +#define DMA2_DSCPTR_PRV +#define DMA2_ADDR_CUR +#define DMA2_STAT +#define DMA2_XCNT_CUR +#define DMA2_YCNT_CUR +#define DMA2_BWLCNT +#define DMA2_BWLCNT_CUR +#define DMA2_BWMCNT +#define DMA2_BWMCNT_CUR +#define DMA3_DSCPTR_NXT +#define DMA3_ADDRSTART +#define DMA3_CFG +#define DMA3_XCNT +#define DMA3_XMOD +#define DMA3_YCNT +#define DMA3_YMOD +#define DMA3_DSCPTR_CUR +#define DMA3_DSCPTR_PRV +#define DMA3_ADDR_CUR +#define DMA3_STAT +#define DMA3_XCNT_CUR +#define DMA3_YCNT_CUR +#define DMA3_BWLCNT +#define DMA3_BWLCNT_CUR +#define DMA3_BWMCNT +#define DMA3_BWMCNT_CUR +#define DMA4_DSCPTR_NXT +#define DMA4_ADDRSTART +#define DMA4_CFG +#define DMA4_XCNT +#define DMA4_XMOD +#define DMA4_YCNT +#define DMA4_YMOD +#define DMA4_DSCPTR_CUR +#define DMA4_DSCPTR_PRV +#define DMA4_ADDR_CUR +#define DMA4_STAT +#define DMA4_XCNT_CUR +#define DMA4_YCNT_CUR +#define DMA4_BWLCNT +#define DMA4_BWLCNT_CUR +#define DMA4_BWMCNT +#define DMA4_BWMCNT_CUR +#define DMA5_DSCPTR_NXT +#define DMA5_ADDRSTART +#define DMA5_CFG +#define DMA5_XCNT +#define DMA5_XMOD +#define DMA5_YCNT +#define DMA5_YMOD +#define DMA5_DSCPTR_CUR +#define DMA5_DSCPTR_PRV +#define DMA5_ADDR_CUR +#define DMA5_STAT +#define DMA5_XCNT_CUR +#define DMA5_YCNT_CUR +#define DMA5_BWLCNT +#define DMA5_BWLCNT_CUR +#define DMA5_BWMCNT +#define DMA5_BWMCNT_CUR +#define DMA6_DSCPTR_NXT +#define DMA6_ADDRSTART +#define DMA6_CFG +#define DMA6_XCNT +#define DMA6_XMOD +#define DMA6_YCNT +#define DMA6_YMOD +#define DMA6_DSCPTR_CUR +#define DMA6_DSCPTR_PRV +#define DMA6_ADDR_CUR +#define DMA6_STAT +#define DMA6_XCNT_CUR +#define DMA6_YCNT_CUR +#define DMA6_BWLCNT +#define DMA6_BWLCNT_CUR +#define DMA6_BWMCNT +#define DMA6_BWMCNT_CUR +#define DMA7_DSCPTR_NXT +#define DMA7_ADDRSTART +#define DMA7_CFG +#define DMA7_XCNT +#define DMA7_XMOD +#define DMA7_YCNT +#define DMA7_YMOD +#define DMA7_DSCPTR_CUR +#define DMA7_DSCPTR_PRV +#define DMA7_ADDR_CUR +#define DMA7_STAT +#define DMA7_XCNT_CUR +#define DMA7_YCNT_CUR +#define DMA7_BWLCNT +#define DMA7_BWLCNT_CUR +#define DMA7_BWMCNT +#define DMA7_BWMCNT_CUR +#define DMA8_DSCPTR_NXT +#define DMA8_ADDRSTART +#define DMA8_CFG +#define DMA8_XCNT +#define DMA8_XMOD +#define DMA8_YCNT +#define DMA8_YMOD +#define DMA8_DSCPTR_CUR +#define DMA8_DSCPTR_PRV +#define DMA8_ADDR_CUR +#define DMA8_STAT +#define DMA8_XCNT_CUR +#define DMA8_YCNT_CUR +#define DMA8_BWLCNT +#define DMA8_BWLCNT_CUR +#define DMA8_BWMCNT +#define DMA8_BWMCNT_CUR +#define DMA9_DSCPTR_NXT +#define DMA9_ADDRSTART +#define DMA9_CFG +#define DMA9_XCNT +#define DMA9_XMOD +#define DMA9_YCNT +#define DMA9_YMOD +#define DMA9_DSCPTR_CUR +#define DMA9_DSCPTR_PRV +#define DMA9_ADDR_CUR +#define DMA9_STAT +#define DMA9_XCNT_CUR +#define DMA9_YCNT_CUR +#define DMA9_BWLCNT +#define DMA9_BWLCNT_CUR +#define DMA9_BWMCNT +#define DMA9_BWMCNT_CUR +#define DMA10_DSCPTR_NXT +#define DMA10_ADDRSTART +#define DMA10_CFG +#define DMA10_XCNT +#define DMA10_XMOD +#define DMA10_YCNT +#define DMA10_YMOD +#define DMA10_DSCPTR_CUR +#define DMA10_DSCPTR_PRV +#define DMA10_ADDR_CUR +#define DMA10_STAT +#define DMA10_XCNT_CUR +#define DMA10_YCNT_CUR +#define DMA10_BWLCNT +#define DMA10_BWLCNT_CUR +#define DMA10_BWMCNT +#define DMA10_BWMCNT_CUR +#define DMA11_DSCPTR_NXT +#define DMA11_ADDRSTART +#define DMA11_CFG +#define DMA11_XCNT +#define DMA11_XMOD +#define DMA11_YCNT +#define DMA11_YMOD +#define DMA11_DSCPTR_CUR +#define DMA11_DSCPTR_PRV +#define DMA11_ADDR_CUR +#define DMA11_STAT +#define DMA11_XCNT_CUR +#define DMA11_YCNT_CUR +#define DMA11_BWLCNT +#define DMA11_BWLCNT_CUR +#define DMA11_BWMCNT +#define DMA11_BWMCNT_CUR +#define DMA12_DSCPTR_NXT +#define DMA12_ADDRSTART +#define DMA12_CFG +#define DMA12_XCNT +#define DMA12_XMOD +#define DMA12_YCNT +#define DMA12_YMOD +#define DMA12_DSCPTR_CUR +#define DMA12_DSCPTR_PRV +#define DMA12_ADDR_CUR +#define DMA12_STAT +#define DMA12_XCNT_CUR +#define DMA12_YCNT_CUR +#define DMA12_BWLCNT +#define DMA12_BWLCNT_CUR +#define DMA12_BWMCNT +#define DMA12_BWMCNT_CUR +#define DMA13_DSCPTR_NXT +#define DMA13_ADDRSTART +#define DMA13_CFG +#define DMA13_XCNT +#define DMA13_XMOD +#define DMA13_YCNT +#define DMA13_YMOD +#define DMA13_DSCPTR_CUR +#define DMA13_DSCPTR_PRV +#define DMA13_ADDR_CUR +#define DMA13_STAT +#define DMA13_XCNT_CUR +#define DMA13_YCNT_CUR +#define DMA13_BWLCNT +#define DMA13_BWLCNT_CUR +#define DMA13_BWMCNT +#define DMA13_BWMCNT_CUR +#define DMA14_DSCPTR_NXT +#define DMA14_ADDRSTART +#define DMA14_CFG +#define DMA14_XCNT +#define DMA14_XMOD +#define DMA14_YCNT +#define DMA14_YMOD +#define DMA14_DSCPTR_CUR +#define DMA14_DSCPTR_PRV +#define DMA14_ADDR_CUR +#define DMA14_STAT +#define DMA14_XCNT_CUR +#define DMA14_YCNT_CUR +#define DMA14_BWLCNT +#define DMA14_BWLCNT_CUR +#define DMA14_BWMCNT +#define DMA14_BWMCNT_CUR +#define DMA15_DSCPTR_NXT +#define DMA15_ADDRSTART +#define DMA15_CFG +#define DMA15_XCNT +#define DMA15_XMOD +#define DMA15_YCNT +#define DMA15_YMOD +#define DMA15_DSCPTR_CUR +#define DMA15_DSCPTR_PRV +#define DMA15_ADDR_CUR +#define DMA15_STAT +#define DMA15_XCNT_CUR +#define DMA15_YCNT_CUR +#define DMA15_BWLCNT +#define DMA15_BWLCNT_CUR +#define DMA15_BWMCNT +#define DMA15_BWMCNT_CUR +#define DMA16_DSCPTR_NXT +#define DMA16_ADDRSTART +#define DMA16_CFG +#define DMA16_XCNT +#define DMA16_XMOD +#define DMA16_YCNT +#define DMA16_YMOD +#define DMA16_DSCPTR_CUR +#define DMA16_DSCPTR_PRV +#define DMA16_ADDR_CUR +#define DMA16_STAT +#define DMA16_XCNT_CUR +#define DMA16_YCNT_CUR +#define DMA16_BWLCNT +#define DMA16_BWLCNT_CUR +#define DMA16_BWMCNT +#define DMA16_BWMCNT_CUR +#define DMA17_DSCPTR_NXT +#define DMA17_ADDRSTART +#define DMA17_CFG +#define DMA17_XCNT +#define DMA17_XMOD +#define DMA17_YCNT +#define DMA17_YMOD +#define DMA17_DSCPTR_CUR +#define DMA17_DSCPTR_PRV +#define DMA17_ADDR_CUR +#define DMA17_STAT +#define DMA17_XCNT_CUR +#define DMA17_YCNT_CUR +#define DMA17_BWLCNT +#define DMA17_BWLCNT_CUR +#define DMA17_BWMCNT +#define DMA17_BWMCNT_CUR +#define DMA18_DSCPTR_NXT +#define DMA18_ADDRSTART +#define DMA18_CFG +#define DMA18_XCNT +#define DMA18_XMOD +#define DMA18_YCNT +#define DMA18_YMOD +#define DMA18_DSCPTR_CUR +#define DMA18_DSCPTR_PRV +#define DMA18_ADDR_CUR +#define DMA18_STAT +#define DMA18_XCNT_CUR +#define DMA18_YCNT_CUR +#define DMA18_BWLCNT +#define DMA18_BWLCNT_CUR +#define DMA18_BWMCNT +#define DMA18_BWMCNT_CUR +#define DMA19_DSCPTR_NXT +#define DMA19_ADDRSTART +#define DMA19_CFG +#define DMA19_XCNT +#define DMA19_XMOD +#define DMA19_YCNT +#define DMA19_YMOD +#define DMA19_DSCPTR_CUR +#define DMA19_DSCPTR_PRV +#define DMA19_ADDR_CUR +#define DMA19_STAT +#define DMA19_XCNT_CUR +#define DMA19_YCNT_CUR +#define DMA19_BWLCNT +#define DMA19_BWLCNT_CUR +#define DMA19_BWMCNT +#define DMA19_BWMCNT_CUR +#define DMA20_DSCPTR_NXT +#define DMA20_ADDRSTART +#define DMA20_CFG +#define DMA20_XCNT +#define DMA20_XMOD +#define DMA20_YCNT +#define DMA20_YMOD +#define DMA20_DSCPTR_CUR +#define DMA20_DSCPTR_PRV +#define DMA20_ADDR_CUR +#define DMA20_STAT +#define DMA20_XCNT_CUR +#define DMA20_YCNT_CUR +#define DMA20_BWLCNT +#define DMA20_BWLCNT_CUR +#define DMA20_BWMCNT +#define DMA20_BWMCNT_CUR +#define MDMA_S0_NEXT_DESC_PTR +#define DMA21_DSCPTR_NXT +#define DMA21_ADDRSTART +#define DMA21_CFG +#define DMA21_XCNT +#define DMA21_XMOD +#define DMA21_YCNT +#define DMA21_YMOD +#define DMA21_DSCPTR_CUR +#define DMA21_DSCPTR_PRV +#define DMA21_ADDR_CUR +#define DMA21_STAT +#define DMA21_XCNT_CUR +#define DMA21_YCNT_CUR +#define DMA21_BWLCNT +#define DMA21_BWLCNT_CUR +#define DMA21_BWMCNT +#define DMA21_BWMCNT_CUR +#define MDMA_D0_NEXT_DESC_PTR +#define DMA22_DSCPTR_NXT +#define DMA22_ADDRSTART +#define DMA22_CFG +#define DMA22_XCNT +#define DMA22_XMOD +#define DMA22_YCNT +#define DMA22_YMOD +#define DMA22_DSCPTR_CUR +#define DMA22_DSCPTR_PRV +#define DMA22_ADDR_CUR +#define DMA22_STAT +#define DMA22_XCNT_CUR +#define DMA22_YCNT_CUR +#define DMA22_BWLCNT +#define DMA22_BWLCNT_CUR +#define DMA22_BWMCNT +#define DMA22_BWMCNT_CUR +#define DMA23_DSCPTR_NXT +#define DMA23_ADDRSTART +#define DMA23_CFG +#define DMA23_XCNT +#define DMA23_XMOD +#define DMA23_YCNT +#define DMA23_YMOD +#define DMA23_DSCPTR_CUR +#define DMA23_DSCPTR_PRV +#define DMA23_ADDR_CUR +#define DMA23_STAT +#define DMA23_XCNT_CUR +#define DMA23_YCNT_CUR +#define DMA23_BWLCNT +#define DMA23_BWLCNT_CUR +#define DMA23_BWMCNT +#define DMA23_BWMCNT_CUR +#define DMA24_DSCPTR_NXT +#define DMA24_ADDRSTART +#define DMA24_CFG +#define DMA24_XCNT +#define DMA24_XMOD +#define DMA24_YCNT +#define DMA24_YMOD +#define DMA24_DSCPTR_CUR +#define DMA24_DSCPTR_PRV +#define DMA24_ADDR_CUR +#define DMA24_STAT +#define DMA24_XCNT_CUR +#define DMA24_YCNT_CUR +#define DMA24_BWLCNT +#define DMA24_BWLCNT_CUR +#define DMA24_BWMCNT +#define DMA24_BWMCNT_CUR +#define DMA25_DSCPTR_NXT +#define DMA25_ADDRSTART +#define DMA25_CFG +#define DMA25_XCNT +#define DMA25_XMOD +#define DMA25_YCNT +#define DMA25_YMOD +#define DMA25_DSCPTR_CUR +#define DMA25_DSCPTR_PRV +#define DMA25_ADDR_CUR +#define DMA25_STAT +#define DMA25_XCNT_CUR +#define DMA25_YCNT_CUR +#define DMA25_BWLCNT +#define DMA25_BWLCNT_CUR +#define DMA25_BWMCNT +#define DMA25_BWMCNT_CUR +#define DMA26_DSCPTR_NXT +#define DMA26_ADDRSTART +#define DMA26_CFG +#define DMA26_XCNT +#define DMA26_XMOD +#define DMA26_YCNT +#define DMA26_YMOD +#define DMA26_DSCPTR_CUR +#define DMA26_DSCPTR_PRV +#define DMA26_ADDR_CUR +#define DMA26_STAT +#define DMA26_XCNT_CUR +#define DMA26_YCNT_CUR +#define DMA26_BWLCNT +#define DMA26_BWLCNT_CUR +#define DMA26_BWMCNT +#define DMA26_BWMCNT_CUR +#define DMA27_DSCPTR_NXT +#define DMA27_ADDRSTART +#define DMA27_CFG +#define DMA27_XCNT +#define DMA27_XMOD +#define DMA27_YCNT +#define DMA27_YMOD +#define DMA27_DSCPTR_CUR +#define DMA27_DSCPTR_PRV +#define DMA27_ADDR_CUR +#define DMA27_STAT +#define DMA27_XCNT_CUR +#define DMA27_YCNT_CUR +#define DMA27_BWLCNT +#define DMA27_BWLCNT_CUR +#define DMA27_BWMCNT +#define DMA27_BWMCNT_CUR +#define DMA28_DSCPTR_NXT +#define DMA28_ADDRSTART +#define DMA28_CFG +#define DMA28_XCNT +#define DMA28_XMOD +#define DMA28_YCNT +#define DMA28_YMOD +#define DMA28_DSCPTR_CUR +#define DMA28_DSCPTR_PRV +#define DMA28_ADDR_CUR +#define DMA28_STAT +#define DMA28_XCNT_CUR +#define DMA28_YCNT_CUR +#define DMA28_BWLCNT +#define DMA28_BWLCNT_CUR +#define DMA28_BWMCNT +#define DMA28_BWMCNT_CUR +#define DMA29_DSCPTR_NXT +#define DMA29_ADDRSTART +#define DMA29_CFG +#define DMA29_XCNT +#define DMA29_XMOD +#define DMA29_YCNT +#define DMA29_YMOD +#define DMA29_DSCPTR_CUR +#define DMA29_DSCPTR_PRV +#define DMA29_ADDR_CUR +#define DMA29_STAT +#define DMA29_XCNT_CUR +#define DMA29_YCNT_CUR +#define DMA29_BWLCNT +#define DMA29_BWLCNT_CUR +#define DMA29_BWMCNT +#define DMA29_BWMCNT_CUR +#define DMA30_DSCPTR_NXT +#define DMA30_ADDRSTART +#define DMA30_CFG +#define DMA30_XCNT +#define DMA30_XMOD +#define DMA30_YCNT +#define DMA30_YMOD +#define DMA30_DSCPTR_CUR +#define DMA30_DSCPTR_PRV +#define DMA30_ADDR_CUR +#define DMA30_STAT +#define DMA30_XCNT_CUR +#define DMA30_YCNT_CUR +#define DMA30_BWLCNT +#define DMA30_BWLCNT_CUR +#define DMA30_BWMCNT +#define DMA30_BWMCNT_CUR +#define DMA31_DSCPTR_NXT +#define DMA31_ADDRSTART +#define DMA31_CFG +#define DMA31_XCNT +#define DMA31_XMOD +#define DMA31_YCNT +#define DMA31_YMOD +#define DMA31_DSCPTR_CUR +#define DMA31_DSCPTR_PRV +#define DMA31_ADDR_CUR +#define DMA31_STAT +#define DMA31_XCNT_CUR +#define DMA31_YCNT_CUR +#define DMA31_BWLCNT +#define DMA31_BWLCNT_CUR +#define DMA31_BWMCNT +#define DMA31_BWMCNT_CUR +#define DMA32_DSCPTR_NXT +#define DMA32_ADDRSTART +#define DMA32_CFG +#define DMA32_XCNT +#define DMA32_XMOD +#define DMA32_YCNT +#define DMA32_YMOD +#define DMA32_DSCPTR_CUR +#define DMA32_DSCPTR_PRV +#define DMA32_ADDR_CUR +#define DMA32_STAT +#define DMA32_XCNT_CUR +#define DMA32_YCNT_CUR +#define DMA32_BWLCNT +#define DMA32_BWLCNT_CUR +#define DMA32_BWMCNT +#define DMA32_BWMCNT_CUR +#define DMA33_DSCPTR_NXT +#define DMA33_ADDRSTART +#define DMA33_CFG +#define DMA33_XCNT +#define DMA33_XMOD +#define DMA33_YCNT +#define DMA33_YMOD +#define DMA33_DSCPTR_CUR +#define DMA33_DSCPTR_PRV +#define DMA33_ADDR_CUR +#define DMA33_STAT +#define DMA33_XCNT_CUR +#define DMA33_YCNT_CUR +#define DMA33_BWLCNT +#define DMA33_BWLCNT_CUR +#define DMA33_BWMCNT +#define DMA33_BWMCNT_CUR +#define DMA34_DSCPTR_NXT +#define DMA34_ADDRSTART +#define DMA34_CFG +#define DMA34_XCNT +#define DMA34_XMOD +#define DMA34_YCNT +#define DMA34_YMOD +#define DMA34_DSCPTR_CUR +#define DMA34_DSCPTR_PRV +#define DMA34_ADDR_CUR +#define DMA34_STAT +#define DMA34_XCNT_CUR +#define DMA34_YCNT_CUR +#define DMA34_BWLCNT +#define DMA34_BWLCNT_CUR +#define DMA34_BWMCNT +#define DMA34_BWMCNT_CUR +#define DMA35_DSCPTR_NXT +#define DMA35_ADDRSTART +#define DMA35_CFG +#define DMA35_XCNT +#define DMA35_XMOD +#define DMA35_YCNT +#define DMA35_YMOD +#define DMA35_DSCPTR_CUR +#define DMA35_DSCPTR_PRV +#define DMA35_ADDR_CUR +#define DMA35_STAT +#define DMA35_XCNT_CUR +#define DMA35_YCNT_CUR +#define DMA35_BWLCNT +#define DMA35_BWLCNT_CUR +#define DMA35_BWMCNT +#define DMA35_BWMCNT_CUR +#define DMA36_DSCPTR_NXT +#define DMA36_ADDRSTART +#define DMA36_CFG +#define DMA36_XCNT +#define DMA36_XMOD +#define DMA36_YCNT +#define DMA36_YMOD +#define DMA36_DSCPTR_CUR +#define DMA36_DSCPTR_PRV +#define DMA36_ADDR_CUR +#define DMA36_STAT +#define DMA36_XCNT_CUR +#define DMA36_YCNT_CUR +#define DMA36_BWLCNT +#define DMA36_BWLCNT_CUR +#define DMA36_BWMCNT +#define DMA36_BWMCNT_CUR +#define DMA37_DSCPTR_NXT +#define DMA37_ADDRSTART +#define DMA37_CFG +#define DMA37_XCNT +#define DMA37_XMOD +#define DMA37_YCNT +#define DMA37_YMOD +#define DMA37_DSCPTR_CUR +#define DMA37_DSCPTR_PRV +#define DMA37_ADDR_CUR +#define DMA37_STAT +#define DMA37_XCNT_CUR +#define DMA37_YCNT_CUR +#define DMA37_BWLCNT +#define DMA37_BWLCNT_CUR +#define DMA37_BWMCNT +#define DMA37_BWMCNT_CUR +#define DMA38_DSCPTR_NXT +#define DMA38_ADDRSTART +#define DMA38_CFG +#define DMA38_XCNT +#define DMA38_XMOD +#define DMA38_YCNT +#define DMA38_YMOD +#define DMA38_DSCPTR_CUR +#define DMA38_DSCPTR_PRV +#define DMA38_ADDR_CUR +#define DMA38_STAT +#define DMA38_XCNT_CUR +#define DMA38_YCNT_CUR +#define DMA38_BWLCNT +#define DMA38_BWLCNT_CUR +#define DMA38_BWMCNT +#define DMA38_BWMCNT_CUR +#define DMA39_DSCPTR_NXT +#define DMA39_ADDRSTART +#define DMA39_CFG +#define DMA39_XCNT +#define DMA39_XMOD +#define DMA39_YCNT +#define DMA39_YMOD +#define DMA39_DSCPTR_CUR +#define DMA39_DSCPTR_PRV +#define DMA39_ADDR_CUR +#define DMA39_STAT +#define DMA39_XCNT_CUR +#define DMA39_YCNT_CUR +#define DMA39_BWLCNT +#define DMA39_BWLCNT_CUR +#define DMA39_BWMCNT +#define DMA39_BWMCNT_CUR +#define DMA40_DSCPTR_NXT +#define DMA40_ADDRSTART +#define DMA40_CFG +#define DMA40_XCNT +#define DMA40_XMOD +#define DMA40_YCNT +#define DMA40_YMOD +#define DMA40_DSCPTR_CUR +#define DMA40_DSCPTR_PRV +#define DMA40_ADDR_CUR +#define DMA40_STAT +#define DMA40_XCNT_CUR +#define DMA40_YCNT_CUR +#define DMA40_BWLCNT +#define DMA40_BWLCNT_CUR +#define DMA40_BWMCNT +#define DMA40_BWMCNT_CUR +#define DMA41_DSCPTR_NXT +#define DMA41_ADDRSTART +#define DMA41_CFG +#define DMA41_XCNT +#define DMA41_XMOD +#define DMA41_YCNT +#define DMA41_YMOD +#define DMA41_DSCPTR_CUR +#define DMA41_DSCPTR_PRV +#define DMA41_ADDR_CUR +#define DMA41_STAT +#define DMA41_XCNT_CUR +#define DMA41_YCNT_CUR +#define DMA41_BWLCNT +#define DMA41_BWLCNT_CUR +#define DMA41_BWMCNT +#define DMA41_BWMCNT_CUR +#define DMA42_DSCPTR_NXT +#define DMA42_ADDRSTART +#define DMA42_CFG +#define DMA42_XCNT +#define DMA42_XMOD +#define DMA42_YCNT +#define DMA42_YMOD +#define DMA42_DSCPTR_CUR +#define DMA42_DSCPTR_PRV +#define DMA42_ADDR_CUR +#define DMA42_STAT +#define DMA42_XCNT_CUR +#define DMA42_YCNT_CUR +#define DMA42_BWLCNT +#define DMA42_BWLCNT_CUR +#define DMA42_BWMCNT +#define DMA42_BWMCNT_CUR +#define DMA43_DSCPTR_NXT +#define DMA43_ADDRSTART +#define DMA43_CFG +#define DMA43_XCNT +#define DMA43_XMOD +#define DMA43_YCNT +#define DMA43_YMOD +#define DMA43_DSCPTR_CUR +#define DMA43_DSCPTR_PRV +#define DMA43_ADDR_CUR +#define DMA43_STAT +#define DMA43_XCNT_CUR +#define DMA43_YCNT_CUR +#define DMA43_BWLCNT +#define DMA43_BWLCNT_CUR +#define DMA43_BWMCNT +#define DMA43_BWMCNT_CUR +#define DMA44_DSCPTR_NXT +#define DMA44_ADDRSTART +#define DMA44_CFG +#define DMA44_XCNT +#define DMA44_XMOD +#define DMA44_YCNT +#define DMA44_YMOD +#define DMA44_DSCPTR_CUR +#define DMA44_DSCPTR_PRV +#define DMA44_ADDR_CUR +#define DMA44_STAT +#define DMA44_XCNT_CUR +#define DMA44_YCNT_CUR +#define DMA44_BWLCNT +#define DMA44_BWLCNT_CUR +#define DMA44_BWMCNT +#define DMA44_BWMCNT_CUR +#define DMA45_DSCPTR_NXT +#define DMA45_ADDRSTART +#define DMA45_CFG +#define DMA45_XCNT +#define DMA45_XMOD +#define DMA45_YCNT +#define DMA45_YMOD +#define DMA45_DSCPTR_CUR +#define DMA45_DSCPTR_PRV +#define DMA45_ADDR_CUR +#define DMA45_STAT +#define DMA45_XCNT_CUR +#define DMA45_YCNT_CUR +#define DMA45_BWLCNT +#define DMA45_BWLCNT_CUR +#define DMA45_BWMCNT +#define DMA45_BWMCNT_CUR +#define DMA46_DSCPTR_NXT +#define DMA46_ADDRSTART +#define DMA46_CFG +#define DMA46_XCNT +#define DMA46_XMOD +#define DMA46_YCNT +#define DMA46_YMOD +#define DMA46_DSCPTR_CUR +#define DMA46_DSCPTR_PRV +#define DMA46_ADDR_CUR +#define DMA46_STAT +#define DMA46_XCNT_CUR +#define DMA46_YCNT_CUR +#define DMA46_BWLCNT +#define DMA46_BWLCNT_CUR +#define DMA46_BWMCNT +#define DMA46_BWMCNT_CUR +#define ACM0_CTL +#define ACM0_TC0 +#define ACM0_TC1 +#define ACM0_STAT +#define ACM0_EVSTAT +#define ACM0_EVMSK +#define ACM0_MEVSTAT +#define ACM0_MEVMSK +#define ACM0_EVCTL0 +#define ACM0_EVCTL1 +#define ACM0_EVCTL2 +#define ACM0_EVCTL3 +#define ACM0_EVCTL4 +#define ACM0_EVCTL5 +#define ACM0_EVCTL6 +#define ACM0_EVCTL7 +#define ACM0_EVCTL8 +#define ACM0_EVCTL9 +#define ACM0_EVCTL10 +#define ACM0_EVCTL11 +#define ACM0_EVCTL12 +#define ACM0_EVCTL13 +#define ACM0_EVCTL14 +#define ACM0_EVCTL15 +#define ACM0_EVTIME0 +#define ACM0_EVTIME1 +#define ACM0_EVTIME2 +#define ACM0_EVTIME3 +#define ACM0_EVTIME4 +#define ACM0_EVTIME5 +#define ACM0_EVTIME6 +#define ACM0_EVTIME7 +#define ACM0_EVTIME8 +#define ACM0_EVTIME9 +#define ACM0_EVTIME10 +#define ACM0_EVTIME11 +#define ACM0_EVTIME12 +#define ACM0_EVTIME13 +#define ACM0_EVTIME14 +#define ACM0_EVTIME15 +#define ACM0_EVORD0 +#define ACM0_EVORD1 +#define ACM0_EVORD2 +#define ACM0_EVORD3 +#define ACM0_EVORD4 +#define ACM0_EVORD5 +#define ACM0_EVORD6 +#define ACM0_EVORD7 +#define ACM0_EVORD8 +#define ACM0_EVORD9 +#define ACM0_EVORD10 +#define ACM0_EVORD11 +#define ACM0_EVORD12 +#define ACM0_EVORD13 +#define ACM0_EVORD14 +#define ACM0_EVORD15 +#define ACM0_TMR0 +#define ACM0_TMR1 +#define DMC0_ID +#define DMC0_CTL +#define DMC0_STAT +#define DMC0_EFFCTL +#define DMC0_PRIO +#define DMC0_PRIOMSK +#define DMC0_CFG +#define DMC0_TR0 +#define DMC0_TR1 +#define DMC0_TR2 +#define DMC0_MSK +#define DMC0_MR +#define DMC0_EMR1 +#define DMC0_EMR2 +#define DMC0_EMR3 +#define DMC0_DLLCTL +#define DMC0_PADCTL +#define SCB0_ARBR0 +#define SCB0_ARBR1 +#define SCB0_ARBR2 +#define SCB0_ARBR3 +#define SCB0_ARBR4 +#define SCB0_ARBR5 +#define SCB0_ARBW0 +#define SCB0_ARBW1 +#define SCB0_ARBW2 +#define SCB0_ARBW3 +#define SCB0_ARBW4 +#define SCB0_ARBW5 +#define SCB0_SLAVES +#define SCB0_MASTERS +#define SCB1_ARBR0 +#define SCB1_ARBW0 +#define SCB1_SLAVES +#define SCB1_MASTERS +#define SCB2_ARBR0 +#define SCB2_ARBW0 +#define SCB2_SLAVES +#define SCB2_MASTERS +#define SCB3_ARBR0 +#define SCB3_ARBW0 +#define SCB3_SLAVES +#define SCB3_MASTERS +#define SCB4_ARBR0 +#define SCB4_ARBW0 +#define SCB4_SLAVES +#define SCB4_MASTERS +#define SCB5_ARBR0 +#define SCB5_ARBW0 +#define SCB5_SLAVES +#define SCB5_MASTERS +#define SCB6_ARBR0 +#define SCB6_ARBW0 +#define SCB6_SLAVES +#define SCB6_MASTERS +#define SCB7_ARBR0 +#define SCB7_ARBW0 +#define SCB7_SLAVES +#define SCB7_MASTERS +#define SCB8_ARBR0 +#define SCB8_ARBW0 +#define SCB8_SLAVES +#define SCB8_MASTERS +#define SCB9_ARBR0 +#define SCB9_ARBW0 +#define SCB9_SLAVES +#define SCB9_MASTERS +#define SCB10_ARBR0 +#define SCB10_ARBR1 +#define SCB10_ARBR2 +#define SCB10_ARBW0 +#define SCB10_ARBW1 +#define SCB10_ARBW2 +#define SCB10_SLAVES +#define SCB10_MASTERS +#define SCB11_ARBR0 +#define SCB11_ARBR1 +#define SCB11_ARBR2 +#define SCB11_ARBR3 +#define SCB11_ARBR4 +#define SCB11_ARBR5 +#define SCB11_ARBR6 +#define SCB11_ARBW0 +#define SCB11_ARBW1 +#define SCB11_ARBW2 +#define SCB11_ARBW3 +#define SCB11_ARBW4 +#define SCB11_ARBW5 +#define SCB11_ARBW6 +#define SCB11_SLAVES +#define SCB11_MASTERS +#define L2_CTL +#define L2_ACTL_C0 +#define L2_ACTL_C1 +#define L2_ACTL_SYS +#define L2_STAT +#define L2_RPCR +#define L2_WPCR +#define L2_RFA +#define L2_ERRADDR0 +#define L2_ERRADDR1 +#define L2_ERRADDR2 +#define L2_ERRADDR3 +#define L2_ERRADDR4 +#define L2_ERRADDR5 +#define L2_ERRADDR6 +#define L2_ERRADDR7 +#define L2_ET0 +#define L2_EADDR0 +#define L2_ET1 +#define L2_EADDR1 +#define SEC0_CCTL0 +#define SEC0_CCTL1 +#define SEC0_CSTAT0 +#define SEC0_CSTAT1 +#define SEC0_CPND0 +#define SEC0_CPND1 +#define SEC0_CACT0 +#define SEC0_CACT1 +#define SEC0_CPMSK0 +#define SEC0_CPMSK1 +#define SEC0_CGMSK0 +#define SEC0_CGMSK1 +#define SEC0_CPLVL0 +#define SEC0_CPLVL1 +#define SEC0_CSID0 +#define SEC0_CSID1 +#define SEC0_FCTL +#define SEC0_FSTAT +#define SEC0_FSID +#define SEC0_FEND +#define SEC0_FDLY +#define SEC0_FDLY_CUR +#define SEC0_FSRDLY +#define SEC0_FSRDLY_CUR +#define SEC0_FCOPP +#define SEC0_FCOPP_CUR +#define SEC0_GCTL +#define SEC0_GSTAT +#define SEC0_RAISE +#define SEC0_END +#define SEC0_SCTL0 +#define SEC0_SCTL1 +#define SEC0_SCTL2 +#define SEC0_SCTL3 +#define SEC0_SCTL4 +#define SEC0_SCTL5 +#define SEC0_SCTL6 +#define SEC0_SCTL7 +#define SEC0_SCTL8 +#define SEC0_SCTL9 +#define SEC0_SCTL10 +#define SEC0_SCTL11 +#define SEC0_SCTL12 +#define SEC0_SCTL13 +#define SEC0_SCTL14 +#define SEC0_SCTL15 +#define SEC0_SCTL16 +#define SEC0_SCTL17 +#define SEC0_SCTL18 +#define SEC0_SCTL19 +#define SEC0_SCTL20 +#define SEC0_SCTL21 +#define SEC0_SCTL22 +#define SEC0_SCTL23 +#define SEC0_SCTL24 +#define SEC0_SCTL25 +#define SEC0_SCTL26 +#define SEC0_SCTL27 +#define SEC0_SCTL28 +#define SEC0_SCTL29 +#define SEC0_SCTL30 +#define SEC0_SCTL31 +#define SEC0_SCTL32 +#define SEC0_SCTL33 +#define SEC0_SCTL34 +#define SEC0_SCTL35 +#define SEC0_SCTL36 +#define SEC0_SCTL37 +#define SEC0_SCTL38 +#define SEC0_SCTL39 +#define SEC0_SCTL40 +#define SEC0_SCTL41 +#define SEC0_SCTL42 +#define SEC0_SCTL43 +#define SEC0_SCTL44 +#define SEC0_SCTL45 +#define SEC0_SCTL46 +#define SEC0_SCTL47 +#define SEC0_SCTL48 +#define SEC0_SCTL49 +#define SEC0_SCTL50 +#define SEC0_SCTL51 +#define SEC0_SCTL52 +#define SEC0_SCTL53 +#define SEC0_SCTL54 +#define SEC0_SCTL55 +#define SEC0_SCTL56 +#define SEC0_SCTL57 +#define SEC0_SCTL58 +#define SEC0_SCTL59 +#define SEC0_SCTL60 +#define SEC0_SCTL61 +#define SEC0_SCTL62 +#define SEC0_SCTL63 +#define SEC0_SCTL64 +#define SEC0_SCTL65 +#define SEC0_SCTL66 +#define SEC0_SCTL67 +#define SEC0_SCTL68 +#define SEC0_SCTL69 +#define SEC0_SCTL70 +#define SEC0_SCTL71 +#define SEC0_SCTL72 +#define SEC0_SCTL73 +#define SEC0_SCTL74 +#define SEC0_SCTL75 +#define SEC0_SCTL76 +#define SEC0_SCTL77 +#define SEC0_SCTL78 +#define SEC0_SCTL79 +#define SEC0_SCTL80 +#define SEC0_SCTL81 +#define SEC0_SCTL82 +#define SEC0_SCTL83 +#define SEC0_SCTL84 +#define SEC0_SCTL85 +#define SEC0_SCTL86 +#define SEC0_SCTL87 +#define SEC0_SCTL88 +#define SEC0_SCTL89 +#define SEC0_SCTL90 +#define SEC0_SCTL91 +#define SEC0_SCTL92 +#define SEC0_SCTL93 +#define SEC0_SCTL94 +#define SEC0_SCTL95 +#define SEC0_SCTL96 +#define SEC0_SCTL97 +#define SEC0_SCTL98 +#define SEC0_SCTL99 +#define SEC0_SCTL100 +#define SEC0_SCTL101 +#define SEC0_SCTL102 +#define SEC0_SCTL103 +#define SEC0_SCTL104 +#define SEC0_SCTL105 +#define SEC0_SCTL106 +#define SEC0_SCTL107 +#define SEC0_SCTL108 +#define SEC0_SCTL109 +#define SEC0_SCTL110 +#define SEC0_SCTL111 +#define SEC0_SCTL112 +#define SEC0_SCTL113 +#define SEC0_SCTL114 +#define SEC0_SCTL115 +#define SEC0_SCTL116 +#define SEC0_SCTL117 +#define SEC0_SCTL118 +#define SEC0_SCTL119 +#define SEC0_SCTL120 +#define SEC0_SCTL121 +#define SEC0_SCTL122 +#define SEC0_SCTL123 +#define SEC0_SCTL124 +#define SEC0_SCTL125 +#define SEC0_SCTL126 +#define SEC0_SCTL127 +#define SEC0_SCTL128 +#define SEC0_SCTL129 +#define SEC0_SCTL130 +#define SEC0_SCTL131 +#define SEC0_SCTL132 +#define SEC0_SCTL133 +#define SEC0_SCTL134 +#define SEC0_SCTL135 +#define SEC0_SCTL136 +#define SEC0_SCTL137 +#define SEC0_SCTL138 +#define SEC0_SCTL139 +#define SEC0_SSTAT0 +#define SEC0_SSTAT1 +#define SEC0_SSTAT2 +#define SEC0_SSTAT3 +#define SEC0_SSTAT4 +#define SEC0_SSTAT5 +#define SEC0_SSTAT6 +#define SEC0_SSTAT7 +#define SEC0_SSTAT8 +#define SEC0_SSTAT9 +#define SEC0_SSTAT10 +#define SEC0_SSTAT11 +#define SEC0_SSTAT12 +#define SEC0_SSTAT13 +#define SEC0_SSTAT14 +#define SEC0_SSTAT15 +#define SEC0_SSTAT16 +#define SEC0_SSTAT17 +#define SEC0_SSTAT18 +#define SEC0_SSTAT19 +#define SEC0_SSTAT20 +#define SEC0_SSTAT21 +#define SEC0_SSTAT22 +#define SEC0_SSTAT23 +#define SEC0_SSTAT24 +#define SEC0_SSTAT25 +#define SEC0_SSTAT26 +#define SEC0_SSTAT27 +#define SEC0_SSTAT28 +#define SEC0_SSTAT29 +#define SEC0_SSTAT30 +#define SEC0_SSTAT31 +#define SEC0_SSTAT32 +#define SEC0_SSTAT33 +#define SEC0_SSTAT34 +#define SEC0_SSTAT35 +#define SEC0_SSTAT36 +#define SEC0_SSTAT37 +#define SEC0_SSTAT38 +#define SEC0_SSTAT39 +#define SEC0_SSTAT40 +#define SEC0_SSTAT41 +#define SEC0_SSTAT42 +#define SEC0_SSTAT43 +#define SEC0_SSTAT44 +#define SEC0_SSTAT45 +#define SEC0_SSTAT46 +#define SEC0_SSTAT47 +#define SEC0_SSTAT48 +#define SEC0_SSTAT49 +#define SEC0_SSTAT50 +#define SEC0_SSTAT51 +#define SEC0_SSTAT52 +#define SEC0_SSTAT53 +#define SEC0_SSTAT54 +#define SEC0_SSTAT55 +#define SEC0_SSTAT56 +#define SEC0_SSTAT57 +#define SEC0_SSTAT58 +#define SEC0_SSTAT59 +#define SEC0_SSTAT60 +#define SEC0_SSTAT61 +#define SEC0_SSTAT62 +#define SEC0_SSTAT63 +#define SEC0_SSTAT64 +#define SEC0_SSTAT65 +#define SEC0_SSTAT66 +#define SEC0_SSTAT67 +#define SEC0_SSTAT68 +#define SEC0_SSTAT69 +#define SEC0_SSTAT70 +#define SEC0_SSTAT71 +#define SEC0_SSTAT72 +#define SEC0_SSTAT73 +#define SEC0_SSTAT74 +#define SEC0_SSTAT75 +#define SEC0_SSTAT76 +#define SEC0_SSTAT77 +#define SEC0_SSTAT78 +#define SEC0_SSTAT79 +#define SEC0_SSTAT80 +#define SEC0_SSTAT81 +#define SEC0_SSTAT82 +#define SEC0_SSTAT83 +#define SEC0_SSTAT84 +#define SEC0_SSTAT85 +#define SEC0_SSTAT86 +#define SEC0_SSTAT87 +#define SEC0_SSTAT88 +#define SEC0_SSTAT89 +#define SEC0_SSTAT90 +#define SEC0_SSTAT91 +#define SEC0_SSTAT92 +#define SEC0_SSTAT93 +#define SEC0_SSTAT94 +#define SEC0_SSTAT95 +#define SEC0_SSTAT96 +#define SEC0_SSTAT97 +#define SEC0_SSTAT98 +#define SEC0_SSTAT99 +#define SEC0_SSTAT100 +#define SEC0_SSTAT101 +#define SEC0_SSTAT102 +#define SEC0_SSTAT103 +#define SEC0_SSTAT104 +#define SEC0_SSTAT105 +#define SEC0_SSTAT106 +#define SEC0_SSTAT107 +#define SEC0_SSTAT108 +#define SEC0_SSTAT109 +#define SEC0_SSTAT110 +#define SEC0_SSTAT111 +#define SEC0_SSTAT112 +#define SEC0_SSTAT113 +#define SEC0_SSTAT114 +#define SEC0_SSTAT115 +#define SEC0_SSTAT116 +#define SEC0_SSTAT117 +#define SEC0_SSTAT118 +#define SEC0_SSTAT119 +#define SEC0_SSTAT120 +#define SEC0_SSTAT121 +#define SEC0_SSTAT122 +#define SEC0_SSTAT123 +#define SEC0_SSTAT124 +#define SEC0_SSTAT125 +#define SEC0_SSTAT126 +#define SEC0_SSTAT127 +#define SEC0_SSTAT128 +#define SEC0_SSTAT129 +#define SEC0_SSTAT130 +#define SEC0_SSTAT131 +#define SEC0_SSTAT132 +#define SEC0_SSTAT133 +#define SEC0_SSTAT134 +#define SEC0_SSTAT135 +#define SEC0_SSTAT136 +#define SEC0_SSTAT137 +#define SEC0_SSTAT138 +#define SEC0_SSTAT139 +#define TRU0_SSR0 +#define TRU0_SSR1 +#define TRU0_SSR2 +#define TRU0_SSR3 +#define TRU0_SSR4 +#define TRU0_SSR5 +#define TRU0_SSR6 +#define TRU0_SSR7 +#define TRU0_SSR8 +#define TRU0_SSR9 +#define TRU0_SSR10 +#define TRU0_SSR11 +#define TRU0_SSR12 +#define TRU0_SSR13 +#define TRU0_SSR14 +#define TRU0_SSR15 +#define TRU0_SSR16 +#define TRU0_SSR17 +#define TRU0_SSR18 +#define TRU0_SSR19 +#define TRU0_SSR20 +#define TRU0_SSR21 +#define TRU0_SSR22 +#define TRU0_SSR23 +#define TRU0_SSR24 +#define TRU0_SSR25 +#define TRU0_SSR26 +#define TRU0_SSR27 +#define TRU0_SSR28 +#define TRU0_SSR29 +#define TRU0_SSR30 +#define TRU0_SSR31 +#define TRU0_SSR32 +#define TRU0_SSR33 +#define TRU0_SSR34 +#define TRU0_SSR35 +#define TRU0_SSR36 +#define TRU0_SSR37 +#define TRU0_SSR38 +#define TRU0_SSR39 +#define TRU0_SSR40 +#define TRU0_SSR41 +#define TRU0_SSR42 +#define TRU0_SSR43 +#define TRU0_SSR44 +#define TRU0_SSR45 +#define TRU0_SSR46 +#define TRU0_SSR47 +#define TRU0_SSR48 +#define TRU0_SSR49 +#define TRU0_SSR50 +#define TRU0_SSR51 +#define TRU0_SSR52 +#define TRU0_SSR53 +#define TRU0_SSR54 +#define TRU0_SSR55 +#define TRU0_SSR56 +#define TRU0_SSR57 +#define TRU0_SSR58 +#define TRU0_SSR59 +#define TRU0_SSR60 +#define TRU0_SSR61 +#define TRU0_SSR62 +#define TRU0_SSR63 +#define TRU0_SSR64 +#define TRU0_SSR65 +#define TRU0_SSR66 +#define TRU0_SSR67 +#define TRU0_SSR68 +#define TRU0_SSR69 +#define TRU0_SSR70 +#define TRU0_SSR71 +#define TRU0_SSR72 +#define TRU0_SSR73 +#define TRU0_SSR74 +#define TRU0_SSR75 +#define TRU0_SSR76 +#define TRU0_SSR77 +#define TRU0_SSR78 +#define TRU0_SSR79 +#define TRU0_SSR80 +#define TRU0_SSR81 +#define TRU0_SSR82 +#define TRU0_SSR83 +#define TRU0_SSR84 +#define TRU0_SSR85 +#define TRU0_SSR86 +#define TRU0_MTR +#define TRU0_ERRADDR +#define TRU0_STAT +#define TRU0_REVID +#define TRU0_GCTL +#define RCU0_CTL +#define RCU0_STAT +#define RCU0_CRCTL +#define RCU0_CRSTAT +#define RCU0_SIDIS +#define RCU0_SISTAT +#define RCU0_SVECT_LCK +#define RCU0_BCODE +#define RCU0_SVECT0 +#define RCU0_SVECT1 +#define SPU0_CTL +#define SPU0_STAT +#define SPU0_WP0 +#define SPU0_WP1 +#define SPU0_WP2 +#define SPU0_WP3 +#define SPU0_WP4 +#define SPU0_WP5 +#define SPU0_WP6 +#define SPU0_WP7 +#define SPU0_WP8 +#define SPU0_WP9 +#define SPU0_WP10 +#define SPU0_WP11 +#define SPU0_WP12 +#define SPU0_WP13 +#define SPU0_WP14 +#define SPU0_WP15 +#define SPU0_WP16 +#define SPU0_WP17 +#define SPU0_WP18 +#define SPU0_WP19 +#define SPU0_WP20 +#define SPU0_WP21 +#define SPU0_WP22 +#define SPU0_WP23 +#define SPU0_WP24 +#define SPU0_WP25 +#define SPU0_WP26 +#define SPU0_WP27 +#define SPU0_WP28 +#define SPU0_WP29 +#define SPU0_WP30 +#define SPU0_WP31 +#define SPU0_WP32 +#define SPU0_WP33 +#define SPU0_WP34 +#define SPU0_WP35 +#define SPU0_WP36 +#define SPU0_WP37 +#define SPU0_WP38 +#define SPU0_WP39 +#define SPU0_WP40 +#define SPU0_WP41 +#define SPU0_WP42 +#define SPU0_WP43 +#define SPU0_WP44 +#define SPU0_WP45 +#define SPU0_WP46 +#define SPU0_WP47 +#define SPU0_WP48 +#define SPU0_WP49 +#define SPU0_WP50 +#define SPU0_WP51 +#define SPU0_WP52 +#define SPU0_WP53 +#define SPU0_WP54 +#define SPU0_WP55 +#define SPU0_WP56 +#define SPU0_WP57 +#define SPU0_WP58 +#define SPU0_WP59 +#define SPU0_WP60 +#define SPU0_WP61 +#define SPU0_WP62 +#define SPU0_WP63 +#define SPU0_WP64 +#define SPU0_WP65 +#define SPU0_WP66 +#define SPU0_WP67 +#define SPU0_WP68 +#define SPU0_WP69 +#define SPU0_WP70 +#define SPU0_WP71 +#define SPU0_WP72 +#define SPU0_WP73 +#define SPU0_WP74 +#define SPU0_WP75 +#define SPU0_WP76 +#define SPU0_WP77 +#define SPU0_WP78 +#define SPU0_WP79 +#define SPU0_WP80 +#define SPU0_WP81 +#define SPU0_WP82 +#define SPU0_WP83 +#define SPU0_WP84 +#define SPU0_WP85 +#define CGU_CTL +#define CGU_STAT +#define CGU_DIV +#define CGU_CLKOUTSEL +#define DPM0_CTL +#define DPM0_STAT +#define DPM0_CCBF_DIS +#define DPM0_CCBF_EN +#define DPM0_CCBF_STAT +#define DPM0_CCBF_STAT_STKY +#define DPM0_SCBF_DIS +#define DPM0_WAKE_EN +#define DPM0_WAKE_POL +#define DPM0_WAKE_STAT +#define DPM0_HIB_DIS +#define DPM0_PGCNTR +#define DPM0_RESTORE0 +#define DPM0_RESTORE1 +#define DPM0_RESTORE2 +#define DPM0_RESTORE3 +#define DPM0_RESTORE4 +#define DPM0_RESTORE5 +#define DPM0_RESTORE6 +#define DPM0_RESTORE7 +#define DPM0_RESTORE8 +#define DPM0_RESTORE9 +#define DPM0_RESTORE10 +#define DPM0_RESTORE11 +#define DPM0_RESTORE12 +#define DPM0_RESTORE13 +#define DPM0_RESTORE14 +#define DPM0_RESTORE15 +#define EFS0_CTL +#define EFS0_DAT0 +#define EFS0_DAT1 +#define EFS0_DAT2 +#define EFS0_DAT3 +#define EFS0_DAT4 +#define EFS0_DAT5 +#define EFS0_DAT6 +#define EFS0_DAT7 +#define EFS0_PGM0 +#define EFS0_PGM1 +#define EFS0_PGM2 +#define EFS0_PGM3 +#define EFS0_PGM4 +#define EFS0_PGM5 +#define EFS0_PGM6 +#define EFS0_PGM7 +#define EFS0_PGM_TIMING +#define USB0_FADDR +#define USB0_POWER +#define USB0_INTRTX +#define USB0_INTRRX +#define USB0_INTRTXE +#define USB0_INTRRXE +#define USB0_IRQ +#define USB0_IEN +#define USB0_FRAME +#define USB0_INDEX +#define USB0_TESTMODE +#define USB0_EPI_TXMAXP0 +#define USB0_EP0I_CSR0_H +#define USB0_EPI_TXCSR0_H +#define USB0_EP0I_CSR0_P +#define USB0_EPI_TXCSR0_P +#define USB0_EPI_RXMAXP0 +#define USB0_EPI_RXCSR0_H +#define USB0_EPI_RXCSR0_P +#define USB0_EP0I_CNT0 +#define USB0_EPI_RXCNT0 +#define USB0_EP0I_TYPE0 +#define USB0_EPI_TXTYPE0 +#define USB0_EP0I_NAKLIMIT0 +#define USB0_EPI_TXINTERVAL0 +#define USB0_EPI_RXTYPE0 +#define USB0_EPI_RXINTERVAL0 +#define USB0_EP0I_CFGDATA0 +#define USB0_FIFOB0 +#define USB0_FIFOB1 +#define USB0_FIFOB2 +#define USB0_FIFOB3 +#define USB0_FIFOB4 +#define USB0_FIFOB5 +#define USB0_FIFOB6 +#define USB0_FIFOB7 +#define USB0_FIFOB8 +#define USB0_FIFOB9 +#define USB0_FIFOB10 +#define USB0_FIFOB11 +#define USB0_FIFOH0 +#define USB0_FIFOH1 +#define USB0_FIFOH2 +#define USB0_FIFOH3 +#define USB0_FIFOH4 +#define USB0_FIFOH5 +#define USB0_FIFOH6 +#define USB0_FIFOH7 +#define USB0_FIFOH8 +#define USB0_FIFOH9 +#define USB0_FIFOH10 +#define USB0_FIFOH11 +#define USB0_FIFO0 +#define USB0_FIFO1 +#define USB0_FIFO2 +#define USB0_FIFO3 +#define USB0_FIFO4 +#define USB0_FIFO5 +#define USB0_FIFO6 +#define USB0_FIFO7 +#define USB0_FIFO8 +#define USB0_FIFO9 +#define USB0_FIFO10 +#define USB0_FIFO11 +#define USB0_DEV_CTL +#define USB0_TXFIFOSZ +#define USB0_RXFIFOSZ +#define USB0_TXFIFOADDR +#define USB0_RXFIFOADDR +#define USB0_VENDSTAT +#define USB0_HWVERS +#define USB0_EPINFO +#define USB0_RAMINFO +#define USB0_LINKINFO +#define USB0_VPLEN +#define USB0_HS_EOF1 +#define USB0_FS_EOF1 +#define USB0_LS_EOF1 +#define USB0_SOFT_RST +#define USB0_TXFUNCADDR0 +#define USB0_TXFUNCADDR1 +#define USB0_TXFUNCADDR2 +#define USB0_TXFUNCADDR3 +#define USB0_TXFUNCADDR4 +#define USB0_TXFUNCADDR5 +#define USB0_TXFUNCADDR6 +#define USB0_TXFUNCADDR7 +#define USB0_TXFUNCADDR8 +#define USB0_TXFUNCADDR9 +#define USB0_TXFUNCADDR10 +#define USB0_TXFUNCADDR11 +#define USB0_TXHUBADDR0 +#define USB0_TXHUBADDR1 +#define USB0_TXHUBADDR2 +#define USB0_TXHUBADDR3 +#define USB0_TXHUBADDR4 +#define USB0_TXHUBADDR5 +#define USB0_TXHUBADDR6 +#define USB0_TXHUBADDR7 +#define USB0_TXHUBADDR8 +#define USB0_TXHUBADDR9 +#define USB0_TXHUBADDR10 +#define USB0_TXHUBADDR11 +#define USB0_TXHUBPORT0 +#define USB0_TXHUBPORT1 +#define USB0_TXHUBPORT2 +#define USB0_TXHUBPORT3 +#define USB0_TXHUBPORT4 +#define USB0_TXHUBPORT5 +#define USB0_TXHUBPORT6 +#define USB0_TXHUBPORT7 +#define USB0_TXHUBPORT8 +#define USB0_TXHUBPORT9 +#define USB0_TXHUBPORT10 +#define USB0_TXHUBPORT11 +#define USB0_RXFUNCADDR0 +#define USB0_RXFUNCADDR1 +#define USB0_RXFUNCADDR2 +#define USB0_RXFUNCADDR3 +#define USB0_RXFUNCADDR4 +#define USB0_RXFUNCADDR5 +#define USB0_RXFUNCADDR6 +#define USB0_RXFUNCADDR7 +#define USB0_RXFUNCADDR8 +#define USB0_RXFUNCADDR9 +#define USB0_RXFUNCADDR10 +#define USB0_RXFUNCADDR11 +#define USB0_RXHUBADDR0 +#define USB0_RXHUBADDR1 +#define USB0_RXHUBADDR2 +#define USB0_RXHUBADDR3 +#define USB0_RXHUBADDR4 +#define USB0_RXHUBADDR5 +#define USB0_RXHUBADDR6 +#define USB0_RXHUBADDR7 +#define USB0_RXHUBADDR8 +#define USB0_RXHUBADDR9 +#define USB0_RXHUBADDR10 +#define USB0_RXHUBADDR11 +#define USB0_RXHUBPORT0 +#define USB0_RXHUBPORT1 +#define USB0_RXHUBPORT2 +#define USB0_RXHUBPORT3 +#define USB0_RXHUBPORT4 +#define USB0_RXHUBPORT5 +#define USB0_RXHUBPORT6 +#define USB0_RXHUBPORT7 +#define USB0_RXHUBPORT8 +#define USB0_RXHUBPORT9 +#define USB0_RXHUBPORT10 +#define USB0_RXHUBPORT11 +#define USB0_EP0_CSR0_H +#define USB0_EP0_CSR0_P +#define USB0_EP0_CNT0 +#define USB0_EP0_TYPE0 +#define USB0_EP0_NAKLIMIT0 +#define USB0_EP0_CFGDATA0 +#define USB0_EP_TXMAXP0 +#define USB0_EP_TXMAXP1 +#define USB0_EP_TXMAXP2 +#define USB0_EP_TXMAXP3 +#define USB0_EP_TXMAXP4 +#define USB0_EP_TXMAXP5 +#define USB0_EP_TXMAXP6 +#define USB0_EP_TXMAXP7 +#define USB0_EP_TXMAXP8 +#define USB0_EP_TXMAXP9 +#define USB0_EP_TXMAXP10 +#define USB0_EP_TXCSR0_H +#define USB0_EP_TXCSR1_H +#define USB0_EP_TXCSR2_H +#define USB0_EP_TXCSR3_H +#define USB0_EP_TXCSR4_H +#define USB0_EP_TXCSR5_H +#define USB0_EP_TXCSR6_H +#define USB0_EP_TXCSR7_H +#define USB0_EP_TXCSR8_H +#define USB0_EP_TXCSR9_H +#define USB0_EP_TXCSR10_H +#define USB0_EP_TXCSR0_P +#define USB0_EP_TXCSR1_P +#define USB0_EP_TXCSR2_P +#define USB0_EP_TXCSR3_P +#define USB0_EP_TXCSR4_P +#define USB0_EP_TXCSR5_P +#define USB0_EP_TXCSR6_P +#define USB0_EP_TXCSR7_P +#define USB0_EP_TXCSR8_P +#define USB0_EP_TXCSR9_P +#define USB0_EP_TXCSR10_P +#define USB0_EP_RXMAXP0 +#define USB0_EP_RXMAXP1 +#define USB0_EP_RXMAXP2 +#define USB0_EP_RXMAXP3 +#define USB0_EP_RXMAXP4 +#define USB0_EP_RXMAXP5 +#define USB0_EP_RXMAXP6 +#define USB0_EP_RXMAXP7 +#define USB0_EP_RXMAXP8 +#define USB0_EP_RXMAXP9 +#define USB0_EP_RXMAXP10 +#define USB0_EP_RXCSR0_H +#define USB0_EP_RXCSR1_H +#define USB0_EP_RXCSR2_H +#define USB0_EP_RXCSR3_H +#define USB0_EP_RXCSR4_H +#define USB0_EP_RXCSR5_H +#define USB0_EP_RXCSR6_H +#define USB0_EP_RXCSR7_H +#define USB0_EP_RXCSR8_H +#define USB0_EP_RXCSR9_H +#define USB0_EP_RXCSR10_H +#define USB0_EP_RXCSR0_P +#define USB0_EP_RXCSR1_P +#define USB0_EP_RXCSR2_P +#define USB0_EP_RXCSR3_P +#define USB0_EP_RXCSR4_P +#define USB0_EP_RXCSR5_P +#define USB0_EP_RXCSR6_P +#define USB0_EP_RXCSR7_P +#define USB0_EP_RXCSR8_P +#define USB0_EP_RXCSR9_P +#define USB0_EP_RXCSR10_P +#define USB0_EP_RXCNT0 +#define USB0_EP_RXCNT1 +#define USB0_EP_RXCNT2 +#define USB0_EP_RXCNT3 +#define USB0_EP_RXCNT4 +#define USB0_EP_RXCNT5 +#define USB0_EP_RXCNT6 +#define USB0_EP_RXCNT7 +#define USB0_EP_RXCNT8 +#define USB0_EP_RXCNT9 +#define USB0_EP_RXCNT10 +#define USB0_EP_TXTYPE0 +#define USB0_EP_TXTYPE1 +#define USB0_EP_TXTYPE2 +#define USB0_EP_TXTYPE3 +#define USB0_EP_TXTYPE4 +#define USB0_EP_TXTYPE5 +#define USB0_EP_TXTYPE6 +#define USB0_EP_TXTYPE7 +#define USB0_EP_TXTYPE8 +#define USB0_EP_TXTYPE9 +#define USB0_EP_TXTYPE10 +#define USB0_EP_TXINTERVAL0 +#define USB0_EP_TXINTERVAL1 +#define USB0_EP_TXINTERVAL2 +#define USB0_EP_TXINTERVAL3 +#define USB0_EP_TXINTERVAL4 +#define USB0_EP_TXINTERVAL5 +#define USB0_EP_TXINTERVAL6 +#define USB0_EP_TXINTERVAL7 +#define USB0_EP_TXINTERVAL8 +#define USB0_EP_TXINTERVAL9 +#define USB0_EP_TXINTERVAL10 +#define USB0_EP_RXTYPE0 +#define USB0_EP_RXTYPE1 +#define USB0_EP_RXTYPE2 +#define USB0_EP_RXTYPE3 +#define USB0_EP_RXTYPE4 +#define USB0_EP_RXTYPE5 +#define USB0_EP_RXTYPE6 +#define USB0_EP_RXTYPE7 +#define USB0_EP_RXTYPE8 +#define USB0_EP_RXTYPE9 +#define USB0_EP_RXTYPE10 +#define USB0_EP_RXINTERVAL0 +#define USB0_EP_RXINTERVAL1 +#define USB0_EP_RXINTERVAL2 +#define USB0_EP_RXINTERVAL3 +#define USB0_EP_RXINTERVAL4 +#define USB0_EP_RXINTERVAL5 +#define USB0_EP_RXINTERVAL6 +#define USB0_EP_RXINTERVAL7 +#define USB0_EP_RXINTERVAL8 +#define USB0_EP_RXINTERVAL9 +#define USB0_EP_RXINTERVAL10 +#define USB0_DMA_IRQ +#define USB0_DMA_CTL0 +#define USB0_DMA_CTL1 +#define USB0_DMA_CTL2 +#define USB0_DMA_CTL3 +#define USB0_DMA_CTL4 +#define USB0_DMA_CTL5 +#define USB0_DMA_CTL6 +#define USB0_DMA_CTL7 +#define USB0_DMA_ADDR0 +#define USB0_DMA_ADDR1 +#define USB0_DMA_ADDR2 +#define USB0_DMA_ADDR3 +#define USB0_DMA_ADDR4 +#define USB0_DMA_ADDR5 +#define USB0_DMA_ADDR6 +#define USB0_DMA_ADDR7 +#define USB0_DMA_CNT0 +#define USB0_DMA_CNT1 +#define USB0_DMA_CNT2 +#define USB0_DMA_CNT3 +#define USB0_DMA_CNT4 +#define USB0_DMA_CNT5 +#define USB0_DMA_CNT6 +#define USB0_DMA_CNT7 +#define USB0_RQPKTCNT0 +#define USB0_RQPKTCNT1 +#define USB0_RQPKTCNT2 +#define USB0_RQPKTCNT3 +#define USB0_RQPKTCNT4 +#define USB0_RQPKTCNT5 +#define USB0_RQPKTCNT6 +#define USB0_RQPKTCNT7 +#define USB0_RQPKTCNT8 +#define USB0_RQPKTCNT9 +#define USB0_RQPKTCNT10 +#define USB0_CT_UCH +#define USB0_CT_HHSRTN +#define USB0_CT_HSBT +#define USB0_LPM_ATTR +#define USB0_LPM_CTL +#define USB0_LPM_IEN +#define USB0_LPM_IRQ +#define USB0_LPM_FADDR +#define USB0_VBUS_CTL +#define USB0_BAT_CHG +#define USB0_PHY_CTL +#define USB0_TESTCTL +#define USB0_PLL_OSC + +#define +/* CHIPID Masks */ +#define +#define +#define + +#define L1_DATA_A_SRAM +#define L1_DATA_A_SRAM_SIZE 0x8000 +#define L1_DATA_A_SRAM_END +#define L1_DATA_B_SRAM +#define L1_DATA_B_SRAM_SIZE 0x4000 +#define L1_DATA_B_SRAM_END + +#define L1_INST_SRAM +#define L1_INST_SRAM_SIZE 0x8000 +#define L1_INST_SRAM_END + +#endif /* __BFIN_DEF diff --git a/arch/bla new file mode 100644 index 0000000..cfe1a1d --- /dev/null +++ b/arch/blackfin/i @@ -0,0 +1,128 @@ +/* + * DO NOT EDIT THIS FILE + * This file + *   svn://sources.b + * and can + * DO NOT EDIT THIS FILE + * + * Copyright + * Licensed under the ADI BSD license. + *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd should be up to date with: not work on BF506 silicon version Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ Be Used to Access 16-bit System MMR Registers */ Error from an Access in the Shadow of a Conditional Branch */ Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ Errors Caused by Fetches at the Boundary of Reserved Memory */ Error Goes Undetected in ITU-R 656 Mode */ Fetches Can Cause Undesired External FIFO Operations */ Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ at End of Hardware Loop Causes Infinite Stall */ Receiver Fails on Extended Bit Pulses */ Error when RETI Points to Invalid Memory */ Incorrect Settings During Reset */ Default MSEL Value in PLL_CTL */ SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ Instruction Cannot Be Interrupted */ ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ that don't exist on this proc */ ckfin/include/asm/mach-bf609/def_local.h b/arch/blackfin/include/asm/mach-bf609/def_local.h nclude/asm/mach-bf609/def_local.h 1	/* Linux glue */ ckfin/include/asm/mach-bf609/portmux.h b/arch/blackfin/include/asm/mach-bf609/portmux.h nclude/asm/mach-bf609/portmux.h 2008-2011 Analog Devices Inc. S	MAX_BLACKFIN_GPIOS | P_IDENT(GPIO_PC6) | P_FUNCT(0)) | P_IDENT(GPIO_PC7) | P_FUNCT(0)) | P_IDENT(GPIO_PC2) | P_FUNCT(0)) | P_IDENT(GPIO_PC0) | P_FUNCT(0)) | P_IDENT(GPIO_PC3) | P_FUNCT(0)) | P_IDENT(GPIO_PC1) | P_FUNCT(0)) | P_IDENT(GPIO_PB13) | P_FUNCT(0)) | P_IDENT(GPIO_PD6) | P_FUNCT(0)) | P_IDENT(GPIO_PC5) | P_FUNCT(0)) | P_IDENT(GPIO_PC4) | P_FUNCT(0)) | P_IDENT(GPIO_PB14) | P_FUNCT(0)) | P_IDENT(GPIO_PE10) | P_FUNCT(0)) | P_IDENT(GPIO_PE11) | P_FUNCT(0)) | P_IDENT(GPIO_PG3) | P_FUNCT(0)) | P_IDENT(GPIO_PG0) | P_FUNCT(0)) | P_IDENT(GPIO_PG2) | P_FUNCT(0)) | P_IDENT(GPIO_PE15) | P_FUNCT(0)) | P_IDENT(GPIO_PG5) | P_FUNCT(0)) | P_IDENT(GPIO_PE12) | P_FUNCT(0)) | P_IDENT(GPIO_PE13) | P_FUNCT(0)) | P_IDENT(GPIO_PE14) | P_FUNCT(0)) | P_IDENT(GPIO_PG6) | P_FUNCT(0)) | P_IDENT(GPIO_PF0) | P_FUNCT(1)) | P_IDENT(GPIO_PF1) | P_FUNCT(1)) | P_IDENT(GPIO_PF2) | P_FUNCT(1)) | P_IDENT(GPIO_PF3) | P_FUNCT(1)) | P_IDENT(GPIO_PF4) | P_FUNCT(1)) | P_IDENT(GPIO_PF5) | P_FUNCT(1)) | P_IDENT(GPIO_PF6) | P_FUNCT(1)) | P_IDENT(GPIO_PF7) | P_FUNCT(1)) | P_IDENT(GPIO_PF8) | P_FUNCT(1)) | P_IDENT(GPIO_PF9) | P_FUNCT(1)) | P_IDENT(GPIO_PF10) | P_FUNCT(1)) | P_IDENT(GPIO_PF11) | P_FUNCT(1)) | P_IDENT(GPIO_PF12) | P_FUNCT(1)) | P_IDENT(GPIO_PF13) | P_FUNCT(1)) | P_IDENT(GPIO_PF14) | P_FUNCT(1)) | P_IDENT(GPIO_PF15) | P_FUNCT(1)) | P_IDENT(GPIO_PE3) | P_FUNCT(1)) | P_IDENT(GPIO_PE4) | P_FUNCT(1)) | P_IDENT(GPIO_PE0) | P_FUNCT(1)) | P_IDENT(GPIO_PE1) | P_FUNCT(1)) | P_IDENT(GPIO_PD12) | P_FUNCT(1)) | P_IDENT(GPIO_PD15) | P_FUNCT(1)) | P_IDENT(GPIO_PE2) | P_FUNCT(1)) | P_IDENT(GPIO_PE5) | P_FUNCT(1)) | P_IDENT(GPIO_PE9) | P_FUNCT(1)) | P_IDENT(GPIO_PE8) | P_FUNCT(1)) | P_IDENT(GPIO_PE7) | P_FUNCT(1)) | P_IDENT(GPIO_PE6) | P_FUNCT(1)) | P_IDENT(GPIO_PC0) | P_FUNCT(1)) | P_IDENT(GPIO_PC1) | P_FUNCT(1)) | P_IDENT(GPIO_PC2) | P_FUNCT(1)) | P_IDENT(GPIO_PC3) | P_FUNCT(1)) | P_IDENT(GPIO_PC4) | P_FUNCT(1)) | P_IDENT(GPIO_PC5) | P_FUNCT(1)) | P_IDENT(GPIO_PC6) | P_FUNCT(1)) | P_IDENT(GPIO_PC7) | P_FUNCT(1)) | P_IDENT(GPIO_PC8) | P_FUNCT(1)) | P_IDENT(GPIO_PC9) | P_FUNCT(1)) | P_IDENT(GPIO_PC10) | P_FUNCT(1)) | P_IDENT(GPIO_PC11) | P_FUNCT(1)) | P_IDENT(GPIO_PC12) | P_FUNCT(1)) | P_IDENT(GPIO_PC13) | P_FUNCT(1)) | P_IDENT(GPIO_PC14) | P_FUNCT(1)) | P_IDENT(GPIO_PC15) | P_FUNCT(1)) | P_IDENT(GPIO_PD0) | P_FUNCT(1)) | P_IDENT(GPIO_PD1) | P_FUNCT(1)) | P_IDENT(GPIO_PB14) | P_FUNCT(1)) | P_IDENT(GPIO_PB13) | P_FUNCT(1)) | P_IDENT(GPIO_PD6) | P_FUNCT(1)) | P_IDENT(GPIO_PB15) | P_FUNCT(1)) | P_IDENT(GPIO_PA0) | P_FUNCT(1)) | P_IDENT(GPIO_PA1) | P_FUNCT(1)) | P_IDENT(GPIO_PA2) | P_FUNCT(1)) | P_IDENT(GPIO_PA3) | P_FUNCT(1)) | P_IDENT(GPIO_PA4) | P_FUNCT(1)) | P_IDENT(GPIO_PA5) | P_FUNCT(1)) | P_IDENT(GPIO_PA6) | P_FUNCT(1)) | P_IDENT(GPIO_PA7) | P_FUNCT(1)) | P_IDENT(GPIO_PA8) | P_FUNCT(1)) | P_IDENT(GPIO_PA9) | P_FUNCT(1)) | P_IDENT(GPIO_PA10) | P_FUNCT(1)) | P_IDENT(GPIO_PA11) | P_FUNCT(1)) | P_IDENT(GPIO_PA12) | P_FUNCT(1)) | P_IDENT(GPIO_PA13) | P_FUNCT(1)) | P_IDENT(GPIO_PA14) | P_FUNCT(1)) | P_IDENT(GPIO_PA15) | P_FUNCT(1)) | P_IDENT(GPIO_PB7) | P_FUNCT(1)) | P_IDENT(GPIO_PB8) | P_FUNCT(1)) | P_IDENT(GPIO_PB0) | P_FUNCT(1)) | P_IDENT(GPIO_PB1) | P_FUNCT(1)) | P_IDENT(GPIO_PB2) | P_FUNCT(1)) | P_IDENT(GPIO_PB3) | P_FUNCT(1)) | P_IDENT(GPIO_PD11) | P_FUNCT(3)) | P_IDENT(GPIO_PD4) | P_FUNCT(0)) | P_IDENT(GPIO_PD2) | P_FUNCT(0)) | P_IDENT(GPIO_PD3) | P_FUNCT(0)) | P_IDENT(GPIO_PD10) | P_FUNCT(0)) | P_IDENT(GPIO_PD0) | P_FUNCT(0)) | P_IDENT(GPIO_PD1) | P_FUNCT(0)) | P_IDENT(GPIO_PD11) | P_FUNCT(0)) | P_IDENT(GPIO_PD1) | P_FUNCT(2)) | P_IDENT(GPIO_PD0) | P_FUNCT(2)) | P_IDENT(GPIO_PC15) | P_FUNCT(0)) | P_IDENT(GPIO_PD9) | P_FUNCT(0)) | P_IDENT(GPIO_PC13) | P_FUNCT(0)) | P_IDENT(GPIO_PC12) | P_FUNCT(0)) | P_IDENT(GPIO_PD12) | P_FUNCT(3)) | P_IDENT(GPIO_PD5) | P_FUNCT(0)) | P_IDENT(GPIO_PD14) | P_FUNCT(0)) | P_IDENT(GPIO_PD13) | P_FUNCT(0)) | P_IDENT(GPIO_PE2) | P_FUNCT(0)) | P_IDENT(GPIO_PE1) | P_FUNCT(0)) | P_IDENT(GPIO_PE0) | P_FUNCT(0)) | P_IDENT(GPIO_PD12) | P_FUNCT(0)) | P_IDENT(GPIO_PD15) | P_FUNCT(2)) | P_IDENT(GPIO_PD10) | P_FUNCT(2)) | P_IDENT(GPIO_PD9) | P_FUNCT(2)) | P_IDENT(GPIO_PF8) | P_FUNCT(0)) | P_IDENT(GPIO_PF9) | P_FUNCT(0)) | P_IDENT(GPIO_PC14) | P_FUNCT(0)) | P_IDENT(GPIO_PD7) | P_FUNCT(1)) | P_IDENT(GPIO_PD8) | P_FUNCT(1)) | P_IDENT(GPIO_PD9) | P_FUNCT(1)) | P_IDENT(GPIO_PD10) | P_FUNCT(1)) | P_IDENT(GPIO_PG15) | P_FUNCT(0)) | P_IDENT(GPIO_PG14) | P_FUNCT(0)) | P_IDENT(GPIO_PG10) | P_FUNCT(0)) | P_IDENT(GPIO_PG13) | P_FUNCT(0)) | P_IDENT(GPIO_PG13) | P_FUNCT(3)) | P_IDENT(GPIO_PE14) | P_FUNCT(2)) | P_IDENT(GPIO_PG4) | P_FUNCT(1)) | P_IDENT(GPIO_PG1) | P_FUNCT(1)) | P_IDENT(GPIO_PG8) | P_FUNCT(1)) | P_IDENT(GPIO_PG9) | P_FUNCT(1)) | P_IDENT(GPIO_PG7) | P_FUNCT(1)) | P_IDENT(GPIO_PG11) | P_FUNCT(1)) | P_IDENT(GPIO_PG12) | P_FUNCT(1)) | P_IDENT(GPIO_PG3) | P_FUNCT(2)) | P_IDENT(GPIO_PG2) | P_FUNCT(2)) | P_IDENT(GPIO_PG0) | P_FUNCT(2)) | P_IDENT(GPIO_PE15) | P_FUNCT(2)) | P_IDENT(GPIO_PE13) | P_FUNCT(2)) | P_IDENT(GPIO_PE12) | P_FUNCT(2)) | P_IDENT(GPIO_PE10) | P_FUNCT(2)) | P_IDENT(GPIO_PE11) | P_FUNCT(2)) | P_IDENT(GPIO_PG5) | P_FUNCT(1)) | P_IDENT(GPIO_PG6) | P_FUNCT(1)) | P_IDENT(GPIO_PB15) | P_FUNCT(0)) | P_IDENT(GPIO_PC13) | P_FUNCT(2)) | P_IDENT(GPIO_PC11) | P_FUNCT(2)) | P_IDENT(GPIO_PC9) | P_FUNCT(0)) | P_IDENT(GPIO_PC13) | P_FUNCT(2)) | P_IDENT(GPIO_PC11) | P_FUNCT(2)) | P_IDENT(GPIO_PA0) | P_FUNCT(0)) | P_IDENT(GPIO_PA1) | P_FUNCT(0)) | P_IDENT(GPIO_PA2) | P_FUNCT(0)) | P_IDENT(GPIO_PA3) | P_FUNCT(0)) | P_IDENT(GPIO_PA4) | P_FUNCT(0)) | P_IDENT(GPIO_PA5) | P_FUNCT(0)) | P_IDENT(GPIO_PA6) | P_FUNCT(0)) | P_IDENT(GPIO_PA7) | P_FUNCT(0)) | P_IDENT(GPIO_PA8) | P_FUNCT(0)) | P_IDENT(GPIO_PA9) | P_FUNCT(0)) | P_IDENT(GPIO_PB2) | P_FUNCT(0)) | P_IDENT(GPIO_PA10) | P_FUNCT(0)) | P_IDENT(GPIO_PA11) | P_FUNCT(0)) | P_IDENT(GPIO_PB3) | P_FUNCT(0)) | P_IDENT(GPIO_PA12) | P_FUNCT(0)) | P_IDENT(GPIO_PA13) | P_FUNCT(0)) | P_IDENT(GPIO_PA14) | P_FUNCT(0)) | P_IDENT(GPIO_PA15) | P_FUNCT(0)) | P_IDENT(GPIO_PB6) | P_FUNCT(0)) | P_IDENT(GPIO_PB7) | P_FUNCT(0)) | P_IDENT(GPIO_PB8) | P_FUNCT(0)) | P_IDENT(GPIO_PB10) | P_FUNCT(0)) | P_IDENT(GPIO_PB11) | P_FUNCT(0)) (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0)) | P_IDENT(GPIO_PB1) | P_FUNCT(0)) | P_IDENT(GPIO_PB4) | P_FUNCT(0)) | P_IDENT(GPIO_PB5) | P_FUNCT(0)) | P_IDENT(GPIO_PB4) | P_FUNCT(1)) | P_IDENT(GPIO_PB5) | P_FUNCT(1)) | P_IDENT(GPIO_PG1) | P_FUNCT(2)) | P_IDENT(GPIO_PG4) | P_FUNCT(2)) ckfin/include/asm/mach-bf609/ports.h b/arch/blackfin/include/asm/mach-bf609/ports.h nclude/asm/mach-bf609/ports.h _FUNC_1	(PORT_x_MUX_FUNC_1 << 0) _FUNC_2	(PORT_x_MUX_FUNC_2 << 0) _FUNC_3	(PORT_x_MUX_FUNC_3 << 0) _FUNC_4	(PORT_x_MUX_FUNC_4 << 0) _FUNC_1	(PORT_x_MUX_FUNC_1 << 2) _FUNC_2	(PORT_x_MUX_FUNC_2 << 2) _FUNC_3	(PORT_x_MUX_FUNC_3 << 2) _FUNC_4	(PORT_x_MUX_FUNC_4 << 2) _FUNC_1	(PORT_x_MUX_FUNC_1 << 4) _FUNC_2	(PORT_x_MUX_FUNC_2 << 4) _FUNC_3	(PORT_x_MUX_FUNC_3 << 4) _FUNC_4	(PORT_x_MUX_FUNC_4 << 4) _FUNC_1	(PORT_x_MUX_FUNC_1 << 6) _FUNC_2	(PORT_x_MUX_FUNC_2 << 6) _FUNC_3	(PORT_x_MUX_FUNC_3 << 6) _FUNC_4	(PORT_x_MUX_FUNC_4 << 6) _FUNC_1	(PORT_x_MUX_FUNC_1 << 8) _FUNC_2	(PORT_x_MUX_FUNC_2 << 8) _FUNC_3	(PORT_x_MUX_FUNC_3 << 8) _FUNC_4	(PORT_x_MUX_FUNC_4 << 8) _FUNC_1	(PORT_x_MUX_FUNC_1 << 10) _FUNC_2	(PORT_x_MUX_FUNC_2 << 10) _FUNC_3	(PORT_x_MUX_FUNC_3 << 10) _FUNC_4	(PORT_x_MUX_FUNC_4 << 10) _FUNC_1	(PORT_x_MUX_FUNC_1 << 12) _FUNC_2	(PORT_x_MUX_FUNC_2 << 12) _FUNC_3	(PORT_x_MUX_FUNC_3 << 12) _FUNC_4	(PORT_x_MUX_FUNC_4 << 12) _FUNC_1	(PORT_x_MUX_FUNC_1 << 14) _FUNC_2	(PORT_x_MUX_FUNC_2 << 14) _FUNC_3	(PORT_x_MUX_FUNC_3 << 14) _FUNC_4	(PORT_x_MUX_FUNC_4 << 14) _FUNC_1	(PORT_x_MUX_FUNC_1 << 16) _FUNC_2	(PORT_x_MUX_FUNC_2 << 16) _FUNC_3	(PORT_x_MUX_FUNC_3 << 16) _FUNC_4	(PORT_x_MUX_FUNC_4 << 16) _FUNC_1	(PORT_x_MUX_FUNC_1 << 18) _FUNC_2	(PORT_x_MUX_FUNC_2 << 18) _FUNC_3	(PORT_x_MUX_FUNC_3 << 18) _FUNC_4	(PORT_x_MUX_FUNC_4 << 18) 0_FUNC_1	(PORT_x_MUX_FUNC_1 << 20) 0_FUNC_2	(PORT_x_MUX_FUNC_2 << 20) 0_FUNC_3	(PORT_x_MUX_FUNC_3 << 20) 0_FUNC_4	(PORT_x_MUX_FUNC_4 << 20) 1_FUNC_1	(PORT_x_MUX_FUNC_1 << 22) 1_FUNC_2	(PORT_x_MUX_FUNC_2 << 22) 1_FUNC_3	(PORT_x_MUX_FUNC_3 << 22) 1_FUNC_4	(PORT_x_MUX_FUNC_4 << 22) 2_FUNC_1	(PORT_x_MUX_FUNC_1 << 24) 2_FUNC_2	(PORT_x_MUX_FUNC_2 << 24) 2_FUNC_3	(PORT_x_MUX_FUNC_3 << 24) 2_FUNC_4	(PORT_x_MUX_FUNC_4 << 24) 3_FUNC_1	(PORT_x_MUX_FUNC_1 << 26) 3_FUNC_2	(PORT_x_MUX_FUNC_2 << 26) 3_FUNC_3	(PORT_x_MUX_FUNC_3 << 26) 3_FUNC_4	(PORT_x_MUX_FUNC_4 << 26) 4_FUNC_1	(PORT_x_MUX_FUNC_1 << 28) 4_FUNC_2	(PORT_x_MUX_FUNC_2 << 28) 4_FUNC_3	(PORT_x_MUX_FUNC_3 << 28) 4_FUNC_4	(PORT_x_MUX_FUNC_4 << 28) 5_FUNC_1	(PORT_x_MUX_FUNC_1 << 30) 5_FUNC_2	(PORT_x_MUX_FUNC_2 << 30) 5_FUNC_3	(PORT_x_MUX_FUNC_3 << 30) 5_FUNC_4	(PORT_x_MUX_FUNC_4 << 30) ch-common/bits/ports-a.h" ch-common/bits/ports-b.h" ch-common/bits/ports-c.h" ch-common/bits/ports-d.h" ch-common/bits/ports-e.h" ch-common/bits/ports-f.h" ch-common/bits/ports-g.h" ckfin/include/asm/mach-common/bits/cgu.h b/arch/blackfin/include/asm/mach-common/bits/cgu.h nclude/asm/mach-common/bits/cgu.h << SYSSEL_P) ckfin/include/asm/mach-common/bits/dde.h b/arch/blackfin/include/asm/mach-common/bits/dde.h nclude/asm/mach-common/bits/dde.h << DMAEN_P)	/* DMA Channel Enable */ << WNR_P)	/* Channel Direction (W/R*) */ << SYNC_P)	/* Synchronize Work Unit Transitions */ << CADDR_P)	/* Use Current Address */ << PSIZE_P)	/* Peripheral Word Size */ << MSIZE_P)	/* Memory Transfer Size */ << FLOW_P)	/* Next Operation */ << FLOW_P)	/* Stop Mode */ << FLOW_P)	/* Autobuffer Mode */ << FLOW_P)	/* Descriptor List */ << FLOW_P)	/* Descriptor Array */ << FLOW_P)	/* Descriptor On Demand List */ << FLOW_P)	/* Descriptor On Demand Array */ << NDSIZE_P)	/* Next Descriptor Set Size */ << NDSIZE_P) << NDSIZE_P) << NDSIZE_P) << NDSIZE_P) << NDSIZE_P) << NDSIZE_P) << NDSIZE_P) (1 << INT_P) (2 << INT_P) (1 << INT_P)    /* xcount expires interrupt */ << TRIG_P)	/* Generate Trigger */ << DESCIDCPY_P) << DMA_DONE_P)	/* Work Unit/Row Done Interrupt */ << DMA_ERR_P)	/* Error Interrupt */ << DMA_PIRQ_P)	/* Peripheral Interrupt Request */ << DMA_ERRC_P)	/* Error Cause */ << DMA_RUN_P)	/* Run Status */ << DMA_PBWIDTH_P)	/* Peripheral Bus Width */ << DMA_MBWIDTH_P)	/* Memory Bus Width */ << DMA_FIFOFILL_P)	/* FIFO Fill Status */ << DMA_TWAIT_P)	/* Trigger Wait Status */ ckfin/include/asm/mach-common/bits/mpu.h b/arch/blackfin/include/asm/mach-common/bits/mpu.h nclude/asm/mach-common/bits/mpu.h nclude/asm/mach-common/bits/mpu.h B		0x00010000	/* 4 KB page size */ B		0x00020000	/* 1 MB page size */ B		0x00030000	/* 4 MB page size */ SK		0x00030000	/* the bits for the page_size field */ KB		0x00040000	/* 16 KB page size */ KB		0x00050000	/* 64 KB page size */ MB		0x00060000	/* 16 MB page size */ MB		0x00070000	/* 64 MB page size */ SK		0x00070000	/* the bits for the page_size field */ 0x00000020	/* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */ O		0x00000200	/* 0=low priority port, 1= high priority port */ ckfin/include/asm/mach-common/bits/pll.h b/arch/blackfin/include/asm/mach-common/bits/pll.h nclude/asm/mach-common/bits/pll.h nclude/asm/mach-common/bits/pll.h Multiplier Select For CCLK/VCO Factors */ Enable Additional Hysteresis on SPORT Input Pins */
+#define MSEL_P			9
+
 /* PLL_DIV Masks */
 #define SSEL			0x000F		/* System Select */
 #define CSEL			0x0030		/* Core Select */
@@ -29,6 +31,9 @@
 #define CCLK_DIV4		CSEL_DIV4
 #define CCLK_DIV8		CSEL_DIV8
+#define SSEL_P			0
+#define CSEL_P			4
+
 /* PLL_STAT Masks */
 #define ACTIVE_PLLENABLED	0x0001		/* Processor In Active Mode With PLL Enabled */
 #define FULL_ON			0x0002		/* Processor In Full On Mode */
-- 
1.7.9.5



    