
On Fri, Jun 19, 2020 at 2:08 PM Marek Vasut marek.vasut@gmail.com wrote:
On 6/19/20 5:52 PM, Adam Ford wrote:
On Fri, Jun 19, 2020 at 9:18 AM Marek Vasut wrote:
On 6/19/20 3:58 PM, Adam Ford wrote:
This sync's the clock tables with the official release from Renesas' repo based on U-Boot 2018.09 and modified to build into the latest version of U-Boot.
Can you import the clock table from Linux too ?
Sure thing. Doing so actually removed a note for missing clocks. :-)
Nice
[...]
+static const struct mstp_stop_table r8a774a1_mstp_table[] = {
{ 0x00200000, 0x0, 0x00200000, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
{ 0x80000184, 0x180, 0x80000184, 0 },
{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
{ 0x000000B7, 0x0, 0x000000B7, 0 },
+};
Can you check whether all those bits are really defined in the MSTP registers of the SoC ?
Can you give me a point on how to interpret this table? I copied it from the Renesas release, and it looks the same as the table for the R8A7796, but I don't know what it's supposed to do.
Look into renesas_clk_remove() in drivers/clk/renesas/renesas-cpg-mssr.c
I found the RZG2M ref manual 1.00, and lists MSTPSR1-10 and RMSTPCR1-10. Their initial values vary between revisions of the silicon for the RZ/G2M, but there are 12 entries in the table, so I am not even sure I'm looking at the right stuff in the ref manual.
You're looking at the correct part of the manual. The goal is to turn off all the clock expect required ones before booting Linux. The code (see above) should make it clear what each line means and which register is written.
This appears to work with a quick test, but I haven't exercised everything yet.
static const struct mstp_stop_table r8a774a1_mstp_table[] = { { 0x00000000, 0, 0x00000000, 0 }, { 0xc3e81000, 0, 0xc3e81000, 0 }, { 0x000E0FDC, 0, 0x000E0FDC, 0 }, { 0xD00C7C1F, 0, 0xD00C7C1F, 0 }, { 0x80000004, 0, 0x80000004, 0 }, { 0x00DF0006, 0, 0x00DF0006, 0 }, { 0XC5EACCCE, 0, 0XC5EACCCE, 0 }, { 0x29E1401C, 0, 0x29E1401C, 0 }, { 0x00009FF1, 0, 0x00009FF1, 0 }, { 0xFC4FDFE0, 0, 0xFC4FDFE0, 0 }, { 0xFFFEFFE8, 0, 0xFFFEFFE8, 0 }, };
I read through registers 1-10, but there doesn't appear to be a register 0, so I left it as all 0's. The rest of these I only set the bits based on flags that were available for the RZ/G2M regardless of their default clock status.
Does this look right to you? If you think it looks good, I'll submit another revision.
thanks
adam