Signed-off-by: Heiko Schocher hs@denx.de --- arch/arm/include/asm/arch-davinci/aintc_defs.h | 50 +++++++++ arch/arm/include/asm/arch-davinci/ddr2_defs.h | 92 ++++++++++++++++ arch/arm/include/asm/arch-davinci/hardware.h | 11 ++ arch/arm/include/asm/arch-davinci/pll_defs.h | 79 ++++++++++++++ arch/arm/include/asm/arch-davinci/psc_defs.h | 129 +++++++++++++++++++++++ arch/arm/include/asm/arch-davinci/syscfg_defs.h | 66 ++++++++++++ arch/arm/include/asm/arch-davinci/timer_defs.h | 48 +++++++++ 7 files changed, 475 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-davinci/aintc_defs.h create mode 100644 arch/arm/include/asm/arch-davinci/ddr2_defs.h create mode 100644 arch/arm/include/asm/arch-davinci/pll_defs.h create mode 100644 arch/arm/include/asm/arch-davinci/psc_defs.h create mode 100644 arch/arm/include/asm/arch-davinci/syscfg_defs.h create mode 100644 arch/arm/include/asm/arch-davinci/timer_defs.h
diff --git a/arch/arm/include/asm/arch-davinci/aintc_defs.h b/arch/arm/include/asm/arch-davinci/aintc_defs.h new file mode 100644 index 0000000..8f37053 --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/aintc_defs.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _DV_AINTC_DEFS_H_ +#define _DV_AINTC_DEFS_H_ + +struct dv_aintc_regs { + unsigned int fiq0; /* 0x00 */ + unsigned int fiq1; /* 0x04 */ + unsigned int irq0; /* 0x08 */ + unsigned int irq1; /* 0x0c */ + unsigned int fiqentry; /* 0x10 */ + unsigned int irqentry; /* 0x14 */ + unsigned int eint0; /* 0x18 */ + unsigned int eint1; /* 0x1c */ + unsigned int intctl; /* 0x20 */ + unsigned int eabase; /* 0x24 */ + unsigned char rsvd0[8]; /* 0x28 */ + unsigned int intpri0; /* 0x30 */ + unsigned int intpri1; /* 0x34 */ + unsigned int intpri2; /* 0x38 */ + unsigned int intpri3; /* 0x3c */ + unsigned int intpri4; /* 0x40 */ + unsigned int intpri5; /* 0x44 */ + unsigned int intpri6; /* 0x48 */ + unsigned int intpri7; /* 0x4c */ +}; + +#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE) + +#endif /* _DV_AINTC_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-davinci/ddr2_defs.h b/arch/arm/include/asm/arch-davinci/ddr2_defs.h new file mode 100644 index 0000000..628aef7 --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/ddr2_defs.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _DV_DDR2_DEFS_H_ +#define _DV_DDR2_DEFS_H_ + +/* + * DDR2 Memory Ctrl Register structure + * See sprueh7d.pdf for more details. + */ +struct dv_ddr2_regs_ctrl { + unsigned char rsvd0[4]; /* 0x00 */ + unsigned int sdrstat; /* 0x04 */ + unsigned int sdbcr; /* 0x08 */ + unsigned int sdrcr; /* 0x0C */ + unsigned int sdtimr; /* 0x10 */ + unsigned int sdtimr2; /* 0x14 */ + unsigned char rsvd1[4]; /* 0x18 */ + unsigned int sdbcr2; /* 0x1C */ + unsigned int pbbpr; /* 0x20 */ + unsigned char rsvd2[156]; /* 0x24 */ + unsigned int irr; /* 0xC0 */ + unsigned int imr; /* 0xC4 */ + unsigned int imsr; /* 0xC8 */ + unsigned int imcr; /* 0xCC */ + unsigned char rsvd3[20]; /* 0xD0 */ + unsigned int ddrphycr; /* 0xE4 */ + unsigned int ddrphycr2; /* 0xE8 */ + unsigned char rsvd4[4]; /* 0xEC */ +}; + +#define DM36x_DDR_PHY_PWRDNEN 0x40 +#define DM36x_DDR_PHY_EXT_STRBEN 0x80 +#define DM36x_DDR_PHY_RD_LATENCY_SHIFT 0 + +#define DM36x_DDR_SDTMR1_RFC_SHIFT 25 +#define DM36x_DDR_SDTMR1_RP_SHIFT 22 +#define DM36x_DDR_SDTMR1_RCD_SHIFT 19 +#define DM36x_DDR_SDTMR1_WR_SHIFT 16 +#define DM36x_DDR_SDTMR1_RAS_SHIFT 11 +#define DM36x_DDR_SDTMR1_RC_SHIFT 6 +#define DM36x_DDR_SDTMR1_RRD_SHIFT 3 +#define DM36x_DDR_SDTMR1_WTR_SHIFT 0 + +#define DM36x_DDR_SDTMR2_RASMAX_SHIFT 27 +#define DM36x_DDR_SDTMR2_XP_SHIFT 25 +#define DM36x_DDR_SDTMR2_XSNR_SHIFT 16 +#define DM36x_DDR_SDTMR2_XSRD_SHIFT 8 +#define DM36x_DDR_SDTMR2_RTP_SHIFT 5 +#define DM36x_DDR_SDTMR2_CKE_SHIFT 0 + +#define DM36x_DDR_SDCR_IBANK_POS_SHIFT 26 +#define DM36x_DDR_SDCR_MSDRAMEN_SHIFT 25 +#define DM36x_DDR_SDCR_DDRDRIVE1_SHIFT 24 +#define DM36x_DDR_SDCR_BOOTUNLOCK_SHIFT 23 +#define DM36x_DDR_SDCR_DDR_DDQS_SHIFT 22 +#define DM36x_DDR_SDCR_DDR2EN_SHIFT 20 +#define DM36x_DDR_SDCR_DDRDRIVE0_SHIFT 18 +#define DM36x_DDR_SDCR_DDREN_SHIFT 17 +#define DM36x_DDR_SDCR_SDRAMEN_SHIFT 16 +#define DM36x_DDR_SDCR_TIMUNLOCK_SHIFT 15 +#define DM36x_DDR_SDCR_BUS_WIDTH_SHIFT 14 +#define DM36x_DDR_SDCR_CL_SHIFT 9 +#define DM36x_DDR_SDCR_IBANK_SHIFT 4 +#define DM36x_DDR_SDCR_PAGESIZE_SHIFT 0 + +#define DM36x_DDR_BOOTUNLOCK (1 << DM36x_DDR_SDCR_BOOTUNLOCK_SHIFT) +#define DM36x_DDR_TIMUNLOCK (1 << DM36x_DDR_SDCR_TIMUNLOCK_SHIFT) + +#define dv_ddr2_regs_ctrl \ + ((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE) + +#endif /* _DV_DDR2_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index df3f549..f2c1060 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -108,6 +108,7 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_MMC_SD1_BASE 0x01d00000 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000 #define DAVINCI_MMC_SD0_BASE 0x01d11000 +#define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000
#elif defined(CONFIG_SOC_DM646X) #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000 @@ -478,4 +479,14 @@ static inline int get_async3_src(void)
#endif /* CONFIG_SOC_DA8XX */
+#if defined(CONFIG_SOC_DM365) +#include <asm/arch/aintc_defs.h> +#include <asm/arch/ddr2_defs.h> +#include <asm/arch/emif_defs.h> +#include <asm/arch/gpio_defs.h> +#include <asm/arch/pll_defs.h> +#include <asm/arch/psc_defs.h> +#include <asm/arch/syscfg_defs.h> +#include <asm/arch/timer_defs.h> +#endif #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-davinci/pll_defs.h b/arch/arm/include/asm/arch-davinci/pll_defs.h new file mode 100644 index 0000000..5d37616 --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/pll_defs.h @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _DV_PLL_DEFS_H_ +#define _DV_PLL_DEFS_H_ + +struct dv_pll_regs { + unsigned int pid; /* 0x00 */ + unsigned char rsvd0[224]; /* 0x04 */ + unsigned int rstype; /* 0xe4 */ + unsigned char rsvd1[24]; /* 0xe8 */ + unsigned int pllctl; /* 0x100 */ + unsigned char rsvd2[4]; /* 0x104 */ + unsigned int secctl; /* 0x108 */ + unsigned int rv; /* 0x10c */ + unsigned int pllm; /* 0x110 */ + unsigned int prediv; /* 0x114 */ + unsigned int plldiv1; /* 0x118 */ + unsigned int plldiv2; /* 0x11c */ + unsigned int plldiv3; /* 0x120 */ + unsigned int oscdiv1; /* 0x124 */ + unsigned int postdiv; /* 0x128 */ + unsigned int bpdiv; /* 0x12c */ + unsigned char rsvd5[8]; /* 0x130 */ + unsigned int pllcmd; /* 0x138 */ + unsigned int pllstat; /* 0x13c */ + unsigned int alnctl; /* 0x140 */ + unsigned int dchange; /* 0x144 */ + unsigned int cken; /* 0x148 */ + unsigned int ckstat; /* 0x14c */ + unsigned int systat; /* 0x150 */ + unsigned char rsvd6[12]; /* 0x154 */ + unsigned int plldiv4; /* 0x160 */ + unsigned int plldiv5; /* 0x164 */ + unsigned int plldiv6; /* 0x168 */ + unsigned int plldiv7; /* 0x16C */ + unsigned int plldiv8; /* 0x170 */ + unsigned int plldiv9; /* 0x174 */ +}; + +#define PLLCTL_PLLEN (1 << 0) +#define PLLCTL_PLLPWRDN (1 << 1) +#define PLLCTL_PLLRST (1 << 3) +#define PLLCTL_PLLENSRC (1 << 5) +#define PLLCTL_RES_9 (1 << 8) + +#define PLLSECCTL_TINITZ (1 << 16) +#define PLLSECCTL_TENABLE (1 << 17) +#define PLLSECCTL_TENABLEDIV (1 << 18) +#define PLLSECCTL_STOPMODE (1 << 22) + +#define PLLCMD_GOSET (1 << 0) + +#define PLL0_LOCK 0x07000000 +#define PLL1_LOCK 0x07000000 + +#define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) +#define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE) + +#endif /* _DV_PLL_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-davinci/psc_defs.h b/arch/arm/include/asm/arch-davinci/psc_defs.h new file mode 100644 index 0000000..4a16377 --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/psc_defs.h @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _DV_PSC_DEFS_H_ +#define _DV_PSC_DEFS_H_ + +/* + * Power/Sleep Ctrl Register structure + * See sprufb3.pdf, Chapter 7 + */ +struct dv_psc_regs { + unsigned int pid; /* 0x000 */ + unsigned char rsvd0[16]; /* 0x004 */ + unsigned char rsvd1[4]; /* 0x014 */ + unsigned int inteval; /* 0x018 */ + unsigned char rsvd2[36]; /* 0x01C */ + unsigned int merrpr0; /* 0x040 */ + unsigned int merrpr1; /* 0x044 */ + unsigned char rsvd3[8]; /* 0x048 */ + unsigned int merrcr0; /* 0x050 */ + unsigned int merrcr1; /* 0x054 */ + unsigned char rsvd4[8]; /* 0x058 */ + unsigned int perrpr; /* 0x060 */ + unsigned char rsvd5[4]; /* 0x064 */ + unsigned int perrcr; /* 0x068 */ + unsigned char rsvd6[4]; /* 0x06C */ + unsigned int epcpr; /* 0x070 */ + unsigned char rsvd7[4]; /* 0x074 */ + unsigned int epccr; /* 0x078 */ + unsigned char rsvd8[144]; /* 0x07C */ + unsigned char rsvd9[20]; /* 0x10C */ + unsigned int ptcmd; /* 0x120 */ + unsigned char rsvd10[4]; /* 0x124 */ + unsigned int ptstat; /* 0x128 */ + unsigned char rsvd11[212]; /* 0x12C */ + unsigned int pdstat0; /* 0x200 */ + unsigned int pdstat1; /* 0x204 */ + unsigned char rsvd12[248]; /* 0x208 */ + unsigned int pdctl0; /* 0x300 */ + unsigned int pdctl1; /* 0x304 */ + unsigned char rsvd13[536]; /* 0x308 */ + unsigned int mckout0; /* 0x520 */ + unsigned int mckout1; /* 0x524 */ + unsigned char rsvd14[728]; /* 0x528 */ + unsigned int mdstat[52]; /* 0x800 */ + unsigned char rsvd15[304]; /* 0x8D0 */ + unsigned int mdctl[52]; /* 0xA00 */ +}; + +/* PSC constants */ +#define LPSC_TPCC (0) +#define LPSC_TPTC0 (1) +#define LPSC_TPTC1 (2) +#define LPSC_TPTC2 (3) +#define LPSC_TPTC3 (4) +#define LPSC_TIMER3 (5) +#define LPSC_SPI1 (6) +#define LPSC_MMC_SD1 (7) +#define LPSC_ASP1 (8) +#define LPSC_USB (9) +#define LPSC_PWM3 (10) +#define LPSC_SPI2 (11) +#define LPSC_RTO (12) +#define LPSC_DDR2 (13) +#define LPSC_AEMIF (14) +#define LPSC_MMC_SD0 (15) +#define LPSC_MEMSTK (16) +#define TIMER4 (17) +#define LPSC_I2C (18) +#define LPSC_UART0 (19) +#define LPSC_UART1 (20) +#define LPSC_UHPI (21) +#define LPSC_SPIO (22) +#define LPSC_PWM0 (23) +#define LPSC_PWM1 (24) +#define LPSC_PWM2 (25) +#define LPSC_GPIO (26) +#define LPSC_TIMER0 (27) +#define LPSC_TIMER1 (28) +#define LPSC_TIMER2 (29) +#define LPSC_SYSMOD (30) +#define LPSC_ARM (31) +#define LPSC_SPI3 (38) +#define LPSC_SPI4 (39) +#define LPSC_CPGMAC (40) +#define LPSC_RTC (41) +#define LPSC_KEYSCAN (42) +#define LPSC_ADC (43) +#define LPSC_VOICECODEC (44) +#define LPSC_IMCOP (50) +#define LPSC_KALEIDO (51) + + +#define EMURSTIE_MASK (0x00000200) + +#define PD0 (0) + +#define PSC_ENABLE (0x3) +#define PSC_DISABLE (0x2) +#define PSC_SYNCRESET (0x1) +#define PSC_SWRSTDISABLE (0x0) + +#define PSC_GOSTAT (1 << 0) +#define PSC_MD_STATE_MSK (0x1f) + +#define PSC_CMD_GO (1 << 0) + +#define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE) + +#endif /* _DV_PSC_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-davinci/syscfg_defs.h b/arch/arm/include/asm/arch-davinci/syscfg_defs.h new file mode 100644 index 0000000..05af020 --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/syscfg_defs.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _DV_SYSCFG_DEFS_H_ +#define _DV_SYSCFG_DEFS_H_ + +#ifndef CONFIG_SOC_DA8XX +/* System Control Module register structure for DM365 */ +struct dv_sys_module_regs { + unsigned int pinmux[5]; /* 0x00 */ + unsigned int bootcfg; /* 0x14 */ + unsigned int arm_intmux; /* 0x18 */ + unsigned int edma_evtmux; /* 0x1C */ + unsigned int ddr_slew; /* 0x20 */ + unsigned int clkout; /* 0x24 */ + unsigned int device_id; /* 0x28 */ + unsigned int vdac_config; /* 0x2C */ + unsigned int timer64_ctl; /* 0x30 */ + unsigned int usbbphy_ctl; /* 0x34 */ + unsigned int misc; /* 0x38 */ + unsigned int mstpri[2]; /* 0x3C */ + unsigned int vpss_clkctl; /* 0x44 */ + unsigned int peri_clkctl; /* 0x48 */ + unsigned int deepsleep; /* 0x4C */ + unsigned int dft_enable; /* 0x50 */ + unsigned int debounce[8]; /* 0x54 */ + unsigned int vtpiocr; /* 0x74 */ + unsigned int pupdctl0; /* 0x78 */ + unsigned int pupdctl1; /* 0x7C */ + unsigned int hdimcopbt; /* 0x80 */ + unsigned int pll0_config; /* 0x84 */ + unsigned int pll1_config; /* 0x88 */ +}; + +#define VPTIO_RDY (1 << 15) +#define VPTIO_IOPWRDN (1 << 14) +#define VPTIO_CLRZ (1 << 13) +#define VPTIO_LOCK (1 << 7) +#define VPTIO_PWRDN (1 << 6) + +#define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7) + +#define dv_sys_module_regs \ + ((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE) + +#endif /* !CONFIG_SOC_DA8XX */ +#endif /* _DV_SYSCFG_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-davinci/timer_defs.h b/arch/arm/include/asm/arch-davinci/timer_defs.h new file mode 100644 index 0000000..04f32d0 --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/timer_defs.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _DV_TIMER_DEFS_H_ +#define _DV_TIMER_DEFS_H_ + +/* Timer Register structure - See spruee5a.pdf for more details. */ +struct dv_timer_regs { + unsigned int pid12; /* 0x00 */ + unsigned int emumgt_clkspd; /* 0x04 */ + unsigned char rsvd0[8]; /* 0x08 */ + unsigned int tim12; /* 0x10 */ + unsigned int tim34; /* 0x14 */ + unsigned int prd12; /* 0x18 */ + unsigned int prd34; /* 0x1C */ + unsigned int tcr; /* 0x20 */ + unsigned int tgcr; /* 0x24 */ + unsigned int wdtcr; /* 0x28 */ + unsigned char rsvd1[8]; /* 0x2C */ + unsigned int rel12; /* 0x34 */ + unsigned int rel34; /* 0x38 */ + unsigned int cap12; /* 0x3C */ + unsigned int cap34; /* 0x40 */ + unsigned int intctl_stat; /* 0x44 */ +}; + +#define dv_timer_regs ((struct dv_timer_regs *)DAVINCI_TIMER0_BASE) + +#endif /* _DV_TIMER_DEFS_H_ */