-----Original Message----- From: Grant Likely Hmmm.... okay, so what does that output consist of? I can be convinced that pre-RAM output is necessary, but why is it 90%?
Okay, so it's closer to 50-60% than 90... On our other board without PCI, we're talking about 6 lines after and 25 lines before RAM is initailized.
U-Boot 1.1.4 (Apr 17 2007 - 13:30:37)
MPC8260 Reset Status: External Soft, External Hard
MPC8260 Clock Configuration - Bus-to-Core Mult 4.5x, VCO Div 2, 60x Bus Freq 22-65 , Core Freq 100-300 - dfbrg 0, corecnf 0x17, busdf 5, cpmdf 1, plldf 0, pllmf 5 - vco_out 597196800, scc_clk 149299200, brg_clk 149299200 - cpu_clk 447897600, cpm_clk 298598400, bus_clk 99532800 - pci_clk 49766400
CPU: MPC8280 (HiP7 Rev 14, Mask 1.0 1K49M) at 447.897 MHz Board: Innovative Systems AP2, CPU1 Build: $SvnTreeRevision: 89 $ Watchdog enabled UPMs: Configured FPGA: (cfgaddr 0xff810000)............ Status = OK Altera ID: 0x110b I2C: ready DRAM: DIMM socket probe: Slot1 = 1, Slot2 =1 SDRAM configuration read from SPD Size per side = 256MB Organization: 4 sides, 4 banks, 10 Columns, 13 Rows, Width = 64 bits Refresh rate = 13, CAS latency = 2, Using Page Based interleave EAMUX = 0 Total size: 1024 MB !!! Skipping Memtest (SkipMemtest env varable set) !!! Now running in RAM - U-Boot at: 0ff97000 FLASH: 8 MB PCI: Scanning... 00 11 1095 3124 0180 00 01 00 104c b000 0000 00 01 01 104c b000 0000 00 01 02 104c b000 0000 00 01 03 104c b000 0000 00 00 12 104c ac28 0604 00 IDE controller @ 0x00000000 In: serial Out: serial Err: serial Initializing system supervisor... OK Initializing Ethernet switch Device: 0x0d15, revision 1
Ethernet switch initialized Board revision: 2.0 (02) Net: FCC2 ETHERNET, FCC3 ETHERNET [PRIME] Hit any key to stop autoboot: 0