Since we have cache support built in we can remove Tegra's existing cache initialization code amd other related dead code.
Signed-off-by: Simon Glass sjg@chromium.org --- Changes in v2: - Keep Tegra's config.mk file around so we can set the armv4t flags
arch/arm/cpu/armv7/start.S | 12 --- arch/arm/cpu/armv7/tegra2/ap20.h | 7 +-- arch/arm/cpu/armv7/tegra2/board.c | 8 -- arch/arm/cpu/armv7/tegra2/config.mk | 3 - arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 118 ----------------------------- 5 files changed, 1 insertions(+), 147 deletions(-)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 7fdd422..fa79d73 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -81,18 +81,6 @@ _end_vect: _TEXT_BASE: .word CONFIG_SYS_TEXT_BASE
-#ifdef CONFIG_TEGRA2 -/* - * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s). - * U-Boot runs on the AVP first, setting things up for the CPU (PLLs, - * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU - * to pick up its reset vector, which points here. - */ -.globl _armboot_start -_armboot_start: - .word _start -#endif - /* * These are defined in the board-specific linker script. */ diff --git a/arch/arm/cpu/armv7/tegra2/ap20.h b/arch/arm/cpu/armv7/tegra2/ap20.h index 1bb48d6..a4b4d73 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.h +++ b/arch/arm/cpu/armv7/tegra2/ap20.h @@ -95,13 +95,8 @@ #define HALT_COP_EVENT_IRQ_1 (1 << 11) #define HALT_COP_EVENT_FIQ_1 (1 << 9)
-/* Prototypes */ - +/* Start up the tegra2 SOC */ void tegra2_start(void); -void uart_init(void); -void udelay(unsigned long); -void cold_boot(void); -void cache_configure(void);
/* This is the main entry into U-Boot, used by the Cortex-A9 */ extern void _start(void); diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c index e725134..9fc4f1b 100644 --- a/arch/arm/cpu/armv7/tegra2/board.c +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -55,14 +55,6 @@ unsigned int query_sdram_size(void) } }
-void s_init(void) -{ -#ifndef CONFIG_ICACHE_OFF - icache_enable(); -#endif - invalidate_dcache(); -} - int dram_init(void) { unsigned long rs; diff --git a/arch/arm/cpu/armv7/tegra2/config.mk b/arch/arm/cpu/armv7/tegra2/config.mk index f84fdc8..8f9bdc9 100644 --- a/arch/arm/cpu/armv7/tegra2/config.mk +++ b/arch/arm/cpu/armv7/tegra2/config.mk @@ -24,9 +24,6 @@ # MA 02111-1307 USA #
-# Use ARMv4 for Tegra2 - initial code runs on the AVP, which is an ARM7TDI. -PLATFORM_CPPFLAGS += -march=armv4 - # Tegra has an ARMv4T CPU which runs board_init_f(), so we must build this # file with compatible flags ifdef CONFIG_TEGRA2 diff --git a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S index f24a2ff..6b86647 100644 --- a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S +++ b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S @@ -26,14 +26,6 @@ #include <config.h> #include <version.h>
- -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE @ sdram load addr from config file - -.global invalidate_dcache -invalidate_dcache: - mov pc, lr - .align 5 .global reset_cpu reset_cpu: @@ -47,113 +39,3 @@ _loop_forever: b _loop_forever rstctl: .word PRM_RSTCTRL - -.globl lowlevel_init -lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] - mov ip, lr - bl s_init @ go setup pll, mux & memory - ldr ip, [sp] - mov lr, ip - - mov pc, lr @ back to arch calling code - - -.globl startup_cpu -startup_cpu: - @ Initialize the AVP, clocks, and memory controller - @ SDRAM is guaranteed to be on at this point - - ldr r0, =cold_boot @ R0 = reset vector for CPU - bl start_cpu @ start the CPU - - @ Transfer control to the AVP code - bl halt_avp - - @ Should never get here -_loop_forever2: - b _loop_forever2 - -.globl cache_configure -cache_configure: - stmdb r13!,{r14} - @ invalidate instruction cache - mov r1, #0 - mcr p15, 0, r1, c7, c5, 0 - - @ invalidate the i&d tlb entries - mcr p15, 0, r1, c8, c5, 0 - mcr p15, 0, r1, c8, c6, 0 - - @ enable instruction cache - mrc p15, 0, r1, c1, c0, 0 - orr r1, r1, #(1<<12) - mcr p15, 0, r1, c1, c0, 0 - - bl enable_scu - - @ enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg - mrc p15, 0, r0, c1, c0, 1 - orr r0, r0, #0x41 - mcr p15, 0, r0, c1, c0, 1 - - @ Now flush the Dcache - mov r0, #0 - @ 256 cache lines - mov r1, #256 - -invalidate_loop: - add r1, r1, #-1 - mov r0, r1, lsl #5 - @ invalidate d-cache using line (way0) - mcr p15, 0, r0, c7, c6, 2 - - orr r2, r0, #(1<<30) - @ invalidate d-cache using line (way1) - mcr p15, 0, r2, c7, c6, 2 - - orr r2, r0, #(2<<30) - @ invalidate d-cache using line (way2) - mcr p15, 0, r2, c7, c6, 2 - - orr r2, r0, #(3<<30) - @ invalidate d-cache using line (way3) - mcr p15, 0, r2, c7, c6, 2 - cmp r1, #0 - bne invalidate_loop - - @ FIXME: should have ap20's L2 disabled too? -invalidate_done: - ldmia r13!,{pc} - -.globl cold_boot -cold_boot: - msr cpsr_c, #0xD3 - @ Check current processor: CPU or AVP? - @ If CPU, go to CPU boot code, else continue on AVP path - - ldr r0, =NV_PA_PG_UP_BASE - ldr r1, [r0] - ldr r2, =PG_UP_TAG_AVP - - @ are we the CPU? - ldr sp, CPU_STACK - cmp r1, r2 - @ yep, we are the CPU - bne _armboot_start - - @ AVP initialization follows this path - ldr sp, AVP_STACK - @ Init AVP and start CPU - b startup_cpu - - @ the literal pools origin - .ltorg - -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK -AVP_STACK: - .word EARLY_AVP_STACK -CPU_STACK: - .word EARLY_CPU_STACK