Add device tree for N5X.
Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
--- v5: - Sort the node name in alphanumeric order in socfpga_n5x_socdk-u-boot.dtsi - Remove duplicated qspi node from socfpga_n5x_socdk-u-boot.dtsi, It is defined in socfpga_n5x_socdk.dtsi
v4: - Reuse socfpga_n5x_socdk.dts from Linux and add U-boot specifc dts to u-boot.dtsi. Linux socfpga_n5x_socdk.dts: https://github.com/altera-opensource/linux-socfpga/blob/socfpga-5.4.114-lts/...
v3: - Update comment for memory example code - Move all common dts settings for N5X from socfpga_n5x_socdk.dts to socfpga_n5x-u-boot.dtsi - Remove unused parameter "u-boot,boot0"
v2: - Remove socfpga_n5x.dtsi - Reuse socfpga_agilex.dtsi in socfpga_n5x_socdk.dts and update n5x data accordingly. --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_n5x-u-boot.dtsi | 191 +++++++++++++++++++++ arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 63 +++++++ ...fpga_agilex_socdk.dts => socfpga_n5x_socdk.dts} | 110 ++++++------ 4 files changed, 303 insertions(+), 62 deletions(-) create mode 100644 arch/arm/dts/socfpga_n5x-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi copy arch/arm/dts/{socfpga_agilex_socdk.dts => socfpga_n5x_socdk.dts} (51%)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 537c96bf5b..681cad2727 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -400,6 +400,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sr1500.dtb \ socfpga_cyclone5_vining_fpga.dtb \ + socfpga_n5x_socdk.dtb \ socfpga_stratix10_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi b/arch/arm/dts/socfpga_n5x-u-boot.dtsi new file mode 100644 index 0000000000..d377ae5f69 --- /dev/null +++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> + */ + +#include "socfpga_soc64_fit-u-boot.dtsi" +#include <dt-bindings/clock/n5x-clock.h> + +/{ + memory { + #address-cells = <2>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + }; + + soc { + u-boot,dm-pre-reloc; + + ccu: cache-controller@f7000000 { + compatible = "arteris,ncore-ccu"; + reg = <0xf7000000 0x100900>; + u-boot,dm-pre-reloc; + }; + + clocks { + dram_eosc_clk: dram-eosc-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + }; + + memclkmgr: mem-clock-controller@f8040000 { + compatible = "intel,n5x-mem-clkmgr"; + reg = <0xf8040000 0x1000>; + #clock-cells = <0>; + clocks = <&dram_eosc_clk>, <&f2s_free_clk>; + }; + }; +}; + +&clkmgr { + compatible = "intel,n5x-clkmgr"; + u-boot,dm-pre-reloc; +}; + +&gmac0 { + clocks = <&clkmgr N5X_EMAC0_CLK>; +}; + +&gmac1 { + altr,sysmgr-syscon = <&sysmgr 0x48 0>; + clocks = <&clkmgr N5X_EMAC1_CLK>; +}; + +&gmac2 { + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; + clocks = <&clkmgr N5X_EMAC2_CLK>; +}; + +&i2c0 { + clocks = <&clkmgr N5X_L4_SP_CLK>; + reset-names = "i2c"; +}; + +&i2c1 { + clocks = <&clkmgr N5X_L4_SP_CLK>; + reset-names = "i2c"; +}; + +&i2c2 { + clocks = <&clkmgr N5X_L4_SP_CLK>; + reset-names = "i2c"; +}; + +&i2c3 { + clocks = <&clkmgr N5X_L4_SP_CLK>; + reset-names = "i2c"; +}; + +&i2c4 { + clocks = <&clkmgr N5X_L4_SP_CLK>; + reset-names = "i2c"; +}; + +&memclkmgr { + u-boot,dm-pre-reloc; +}; + +&mmc { + clocks = <&clkmgr N5X_L4_MP_CLK>, + <&clkmgr N5X_SDMMC_CLK>; + resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; +}; + +&pdma { + clocks = <&clkmgr N5X_L4_MAIN_CLK>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&qspi { + u-boot,dm-pre-reloc; +}; + +&rst { + compatible = "altr,rst-mgr"; + altr,modrst-offset = <0x20>; + u-boot,dm-pre-reloc; +}; + +&sdr { + compatible = "intel,sdr-ctl-n5x"; + resets = <&rst DDRSCH_RESET>; + clocks = <&memclkmgr>; + clock-names = "mem_clk"; + u-boot,dm-pre-reloc; +}; + +&spi0 { + clocks = <&clkmgr N5X_L4_MAIN_CLK>; +}; + +&spi1 { + clocks = <&clkmgr N5X_L4_MAIN_CLK>; +}; + +&sysmgr { + compatible = "altr,sys-mgr", "syscon"; + u-boot,dm-pre-reloc; +}; + +&timer0 { + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + +&timer1 { + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + +&timer2 { + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + +&timer3 { + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + +&uart0 { + clocks = <&clkmgr N5X_L4_SP_CLK>; + u-boot,dm-pre-reloc; +}; + +&uart1 { + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + +&usb0 { + clocks = <&clkmgr N5X_USB_CLK>; + disable-over-current; + u-boot,dm-pre-reloc; +}; + +&usb1 { + clocks = <&clkmgr N5X_USB_CLK>; + u-boot,dm-pre-reloc; +}; + +&watchdog0 { + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; + u-boot,dm-pre-reloc; +}; + +&watchdog1 { + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; +}; + +&watchdog2 { + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; +}; + +&watchdog3 { + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; +}; diff --git a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi new file mode 100644 index 0000000000..502da36bd8 --- /dev/null +++ b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> + */ + +#include "socfpga_n5x-u-boot.dtsi" + +/{ + aliases { + spi0 = &qspi; + i2c0 = &i2c1; + }; + + memory { + /* + * Memory type: DDR4 (non-interleaving mode) + * 16GB + * <0 0x00000000 0 0x80000000>, + * <4 0x80000000 3 0x80000000>; + * + * 8GB + * <0 0x00000000 0 0x80000000>, + * <2 0x80000000 1 0x80000000>; + * + * 4GB + * <0 0x00000000 0 0x80000000>, + * <1 0x80000000 0 0x80000000>; + * + * Memory type: LPDDR4 (non-interleaving mode) + * Total memory size 3GB, usable = 2.5GB, 0.5GB trade off for secure + * region. + */ + reg = <0 0x00000000 0 0x60000000>, + <0x10 0x00100000 0 0x40000000>; + }; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + u-boot,dm-pre-reloc; +}; + +&i2c1 { + status = "okay"; +}; + +&mmc { + drvsel = <3>; + smplsel = <0>; + u-boot,dm-pre-reloc; +}; + +&qspi { + status = "okay"; +}; + +&watchdog0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_agilex_socdk.dts b/arch/arm/dts/socfpga_n5x_socdk.dts similarity index 51% copy from arch/arm/dts/socfpga_agilex_socdk.dts copy to arch/arm/dts/socfpga_n5x_socdk.dts index bcdeecc0e0..fdf0826aa1 100644 --- a/arch/arm/dts/socfpga_agilex_socdk.dts +++ b/arch/arm/dts/socfpga_n5x_socdk.dts @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019, Intel Corporation + * Copyright (C) 2021, Intel Corporation */ #include "socfpga_agilex.dtsi"
/ { - model = "SoCFPGA Agilex SoCDK"; + model = "eASIC N5X SoCDK";
aliases { serial0 = &uart0; @@ -18,24 +18,6 @@ stdout-path = "serial0:115200n8"; };
- leds { - compatible = "gpio-leds"; - hps0 { - label = "hps_led0"; - gpios = <&portb 20 GPIO_ACTIVE_HIGH>; - }; - - hps1 { - label = "hps_led1"; - gpios = <&portb 19 GPIO_ACTIVE_HIGH>; - }; - - hps2 { - label = "hps_led2"; - gpios = <&portb 21 GPIO_ACTIVE_HIGH>; - }; - }; - memory { device_type = "memory"; /* We expect the bootloader to fill in the reg */ @@ -51,38 +33,38 @@ }; };
-&gpio1 { - status = "okay"; +&clkmgr { + compatible = "intel,easic-n5x-clkmgr"; };
&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - - max-frame-size = <9000>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <4>; - - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <900>; /* 0ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - }; - }; + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <900>; /* 0ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; };
&mmc { @@ -92,31 +74,22 @@ bus-width = <4>; };
-&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - disable-over-current; -}; - -&watchdog0 { +&qspi { status = "okay"; -};
-&qspi { flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "mt25qu02g"; reg = <0>; spi-max-frequency = <100000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>;
m25p,fast-read; cdns,page-size = <256>; cdns,block-size = <16>; - cdns,read-delay = <1>; + cdns,read-delay = <3>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; @@ -139,3 +112,16 @@ }; }; }; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog0 { + status = "okay"; +};