From: Sascha Laue sascha.laue@liebherr.com
Signed-off-by: Sascha Laue sascha.laue@liebherr.com --- post/board/lwmon5/fpga.c | 58 ++++++++++++++++++++++++++++++++++++++++++--- 1 files changed, 54 insertions(+), 4 deletions(-)
diff --git a/post/board/lwmon5/fpga.c b/post/board/lwmon5/fpga.c index b48390b..aa8f8bb 100644 --- a/post/board/lwmon5/fpga.c +++ b/post/board/lwmon5/fpga.c @@ -41,6 +41,14 @@ DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_POST & CFG_POST_BSPEC3
+const static uint pattern[] = { + 0x55555555, + 0xAAAAAAAA, + 0xAA5555AA, + 0x55AAAA55, + 0x0 +}; + static int one_scratch_test(uint value) { uint read_value; @@ -60,13 +68,47 @@ static int one_scratch_test(uint value) return ret; }
+/* FPGA Memory-pattern-test */ +static int fpga_mem_test(void * address) +{ + int ret = 1; + uint read_value; + uint old_value; + uint i = 0; + + old_value = in_be32(address); + + while (pattern[i] != 0) { + out_be32(address, pattern[i]); + /* read other location (protect against data lines capacity) */ + read_value = in_be16((void *)FPGA_VERSION_REG); + /* verify test pattern */ + read_value = in_be32(address); + + if (read_value != pattern[i]) { + post_log("FPGA memory test failed."); + post_log(" write %08X, read %08X at address %08X\n", + pattern[i], read_value, address); + goto out; + } + i++; + } + + ret = 0; +out: + out_be32(address, old_value); + return ret; +} + /* Verify FPGA, get version & memory size */ int fpga_post_test(int flags) { uint old_value; - ushort version; + uint version; uint read_value; int ret = 0; + uint address; + uint old_fpga_stat;
post_log("\n"); old_value = in_be32((void *)FPGA_SCRATCH_REG); @@ -78,16 +120,24 @@ int fpga_post_test(int flags)
out_be32((void *)FPGA_SCRATCH_REG, old_value);
- version = in_be16((void *)FPGA_VERSION_REG); - post_log("FPGA : version %u.%u\n", + version = in_be32((void *)FPGA_VERSION_REG); + post_log("FPGA version %u.%u\n", (version >> 8) & 0xFF, version & 0xFF);
/* Enable write to FPGA RAM */ out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000);
read_value = get_ram_size((void *)CFG_FPGA_BASE_1, 0x4000); - post_log("FPGA RAM size: %d bytes\n", read_value); + post_log("FPGA RAM size %d bytes\n", read_value);
+ for (address = 0; address < 0x1000; address++) { + if (fpga_mem_test((void *)(FPGA_RAM_START + 4*address)) == 1) { + ret = 1; + goto out; + } + } +out: + out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) & 0xEFFF); return ret; }