September 2024 - U-Boot

[PATCH v2 0/4] dm: core: fix several debug messages and migrate debug() to dm_warn
by Quentin Schulz 03 Oct '24

03 Oct '24

Fix a few misleading or incorrect debug messages and prompt text for a Kconfig symbol. Migrate debug() messages to use dm_warn() instead so that we can print them without selecting DM_DEBUG which does too much (e.g. makes assert() reset U-boot if it fails). Tested on top of next branch but it applies without complaints on top of master as well, so up to you to which branch to merge it. Signed-off-by: Quentin Schulz <quentin.schulz(a)cherry.de> --- Changes in v2: - add missing dm/util.h header includes - Link to v1: https://lore.kernel.org/r/20240610-misc-20240610-v1-0-6914f1725dd4@cherry.de --- Quentin Schulz (4): dm: core: fix misleading debug message when matching compatible dm: core: fix signedness in debug messages dm: core: migrate debug() messages to use dm_warn dm: core: fix typo in SPL_DM_WARN prompt text drivers/core/Kconfig | 2 +- drivers/core/device.c | 2 +- drivers/core/fdtaddr.c | 7 +++-- drivers/core/lists.c | 7 ++--- drivers/core/of_access.c | 51 +++++++++++++++--------------- drivers/core/of_addr.c | 41 ++++++++++++------------ drivers/core/of_extra.c | 33 ++++++++++---------- drivers/core/ofnode.c | 81 ++++++++++++++++++++++++------------------------ drivers/core/regmap.c | 57 +++++++++++++++++----------------- drivers/core/root.c | 14 ++++----- drivers/core/uclass.c | 4 +-- 11 files changed, 152 insertions(+), 147 deletions(-) --- base-commit: f9886bc60f42d5bcfcfa4e474af7dc230400b6be change-id: 20240610-misc-20240610-f9dce050186b Best regards, -- Quentin Schulz <quentin.schulz(a)cherry.de>

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[PATCH 0/4] clk/qcom: implement clk dump callback
by Caleb Connolly 02 Oct '24

02 Oct '24

Add support for dumping a few of the clocks used on Qualcomm platforms. Naming the Global PLL's, Root Clock Generators, and gate clocks. This helps a lot with platform bringup and feature enablement by making it easy to sanity check that the clocks are programmed correctly. == Usage == Enable CONFIG_CMD_CLK and "#define LOG_DEBUG" at the top of qcom-<soc>.c. If your SoC doesn't yet define the debug data for clocks, it can be added using the Linux driver as a reference. The "clk dump" command should print the states of all the gates, GPLLs and RCGs for your SoC. == Glossary == RCG: Root Clock Generator * Takes in some fairly arbitrary high freq clock (configurable clock source and options for taking just even pulses and other things) * Output frequency = input_freq * (m/n) * (1/d) where m/n are arbitrary 8 or 16-bit values (depending on the RCG), and d is a number (with support for .5 offsets). GPLL: Global Phase Locked Loop * Crystal as input * integer multiplier + exponent part (2^-40) Gate: Simple on/off clock * Put between RCGs and the peripherals they power * Required to allow for correct power sequencing If you do the maths manually using the equations from "clk dump", the numbers should roughly line up by they're likely to be out by a handful of MHz. They output is formatted so that it can be pasted directly into the python interpreter. == Example output == => clk dump Rate Usecnt Name ------------------------------------------ 38400000 0 |-- xo-board 32764 0 |-- sleep-clk qcom_clk qcom_clk: Gate Clocks: GCC_AGGRE_USB3_SEC_AXI_CLK : GCC_CFG_NOC_USB3_SEC_AXI_CLK : GCC_QUPV3_WRAP0_S0_CLK : GCC_QUPV3_WRAP0_S1_CLK : GCC_QUPV3_WRAP0_S2_CLK : GCC_QUPV3_WRAP0_S3_CLK : GCC_QUPV3_WRAP0_S4_CLK : GCC_QUPV3_WRAP0_S5_CLK : GCC_QUPV3_WRAP0_S6_CLK : GCC_QUPV3_WRAP0_S7_CLK : GCC_QUPV3_WRAP1_S0_CLK : GCC_QUPV3_WRAP1_S1_CLK : ON GCC_QUPV3_WRAP1_S3_CLK : GCC_QUPV3_WRAP1_S4_CLK : GCC_QUPV3_WRAP1_S5_CLK : GCC_QUPV3_WRAP1_S6_CLK : GCC_QUPV3_WRAP1_S7_CLK : GCC_QUPV3_WRAP_0_M_AHB_CLK : GCC_QUPV3_WRAP_0_S_AHB_CLK : GCC_QUPV3_WRAP_1_M_AHB_CLK : ON GCC_QUPV3_WRAP_1_S_AHB_CLK : ON GCC_SDCC2_AHB_CLK : ON GCC_SDCC2_APPS_CLK : ON GCC_SDCC4_AHB_CLK : GCC_SDCC4_APPS_CLK : GCC_UFS_CARD_AHB_CLK : GCC_UFS_CARD_AXI_CLK : GCC_UFS_CARD_CLKREF_CLK : ON GCC_UFS_CARD_ICE_CORE_CLK : GCC_UFS_CARD_PHY_AUX_CLK : GCC_UFS_CARD_RX_SYMBOL_0_CLK : GCC_UFS_CARD_RX_SYMBOL_1_CLK : GCC_UFS_CARD_TX_SYMBOL_0_CLK : GCC_UFS_CARD_UNIPRO_CORE_CLK : GCC_UFS_MEM_CLKREF_CLK : ON GCC_UFS_PHY_AHB_CLK : ON GCC_UFS_PHY_AXI_CLK : ON GCC_UFS_PHY_ICE_CORE_CLK : ON GCC_UFS_PHY_PHY_AUX_CLK : ON GCC_UFS_PHY_RX_SYMBOL_0_CLK : ON GCC_UFS_PHY_RX_SYMBOL_1_CLK : ON GCC_UFS_PHY_TX_SYMBOL_0_CLK : ON GCC_UFS_PHY_UNIPRO_CORE_CLK : ON GCC_USB30_PRIM_MASTER_CLK : ON GCC_USB30_PRIM_MOCK_UTMI_CLK : ON GCC_USB30_PRIM_SLEEP_CLK : ON GCC_USB30_SEC_MASTER_CLK : GCC_USB30_SEC_MOCK_UTMI_CLK : GCC_USB30_SEC_SLEEP_CLK : GCC_USB3_PRIM_CLKREF_CLK : ON GCC_USB3_PRIM_PHY_AUX_CLK : ON GCC_USB3_PRIM_PHY_COM_AUX_CLK : ON GCC_USB3_PRIM_PHY_PIPE_CLK : ON GCC_USB3_SEC_CLKREF_CLK : ON GCC_USB3_SEC_PHY_AUX_CLK : GCC_USB3_SEC_PHY_PIPE_CLK : GCC_USB3_SEC_PHY_COM_AUX_CLK : GCC_USB_PHY_CFG_AHB2PHY_CLK : ON GPLL clocks: | GPLL | LOCKED | XO_BOARD | PLL_L | ALPHA | +--------+--------+-----------+------------+----------------+ | GPLL0 | X | 19200000 * (0x1f + 0x0 * 2 ** -40 )/ 1000000 | GPLL1 | X | 19200000 * (0x37 + 0x0 * 2 ** -40 ) / 1000000 | GPLL2 | | 19200000 * (0x14 + 0x0 * 2 ** -40 ) / 1000000 | GPLL3 | | 19200000 * (0x30 + 0x0 * 2 ** -40 )/ 1000000 | GPLL4 | X | 19200000 * (0x29 + 0x0 * 2 ** -40 ) / 1000000 | GPLL5 | | 19200000 * (0x30 + 0x0 * 2 ** -40 ) / 1000000 | GPLL6 | | 19200000 * (0x0 + 0x0 * 2 ** -40 )/ 1000000 RCGs: | NAME | ON | SRC | OUT_FREQ = input_freq * (m/n) * (1/d) | [CMD REG ] | +----------------------------------+----+-----+---------------------------------------+--------------+ GCC_USB30_PRIM_MASTER | X | 1 | input_freq * ( 1/ 1) * (1/4.5) | [0x00000000] GCC_USB30_PRIM_MOCK_UTMI | X | 0 | input_freq * ( 1/ 1) * (1/1 ) | [0x00000000] GCC_USB3_PRIM_PHY_AUX | X | 0 | input_freq * ( 1/ 1) * (1/1 ) | [0x00000000] GCC_USB30_SEC_MASTER | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_USB30_SEC_MOCK_UTMI | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_USB3_SEC_PHY_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_SDCC2_APPS | X | 5 | input_freq * ( 1/ 1) * (1/4 ) | [0x00000000] GCC_SDCC4_APPS | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_CORE_2X | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] GCC_QUPV3_WRAP0_S0 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S1 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S2 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S3 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S4 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S5 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S6 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP0_S7 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S0 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S1 | X | 6 | input_freq * ( 384/15625) * (1/1 ) | [0x00000000] GCC_QUPV3_WRAP1_S2 | X | 0 | input_freq * ( 1/ 1) * (1/1 ) | [0x00000000] GCC_QUPV3_WRAP1_S3 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S4 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S5 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S6 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_QUPV3_WRAP1_S7 | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_PCIE_0_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_PCIE_1_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_PCIE_PHY_REFGEN | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] GCC_UFS_CARD_AXI | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] GCC_UFS_CARD_ICE_CORE | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_UFS_CARD_UNIPRO_CORE | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_UFS_CARD_PHY_AUX | | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x80000000] GCC_UFS_PHY_AXI | X | 1 | input_freq * ( 1/ 1) * (1/3 ) | [0x00000000] GCC_UFS_PHY_ICE_CORE | X | 1 | input_freq * ( 1/ 1) * (1/2 ) | [0x00000000] GCC_UFS_PHY_UNIPRO_CORE | X | 1 | input_freq * ( 1/ 1) * (1/4 ) | [0x00000000] GCC_UFS_PHY_PHY_AUX | X | 0 | input_freq * ( 1/ 1) * (1/0.5) | [0x00000000] --- Caleb Connolly (4): clk/qcom: implement clk dump clk/qcom: sdm845: add dump data clk/qcom: sm6115: add debug data clk/qcom: sm8250: add debug data drivers/clk/qcom/clock-qcom.c | 117 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/clock-qcom.h | 6 +++ drivers/clk/qcom/clock-sdm845.c | 93 ++++++++++++++++++++++++++++++++ drivers/clk/qcom/clock-sm6115.c | 63 ++++++++++++++++++++++ drivers/clk/qcom/clock-sm8250.c | 115 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 394 insertions(+) --- change-id: 20240819-b4-qcom-clk-dump-e25a0198f6c0 base-commit: b7d5ce05b1b52136af09cf34541c6a91079a4b86 // Caleb (they/them)

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[PATCH] Revert "gpio: qcom_pmic: add a quirk to skip GPIO configuration"
by Caleb Connolly 02 Oct '24

02 Oct '24

This reverts commit 19f000b72b2fa7e4540f7cdb91287aff594239bd. The bug in writing was caused by a long-standing error in the SPMI driver which has since been fixed - c2de620d64d4 ("spmi: msm: fix version 5 support"). We can safely enable writing GPIO configuration now. Signed-off-by: Caleb Connolly <caleb.connolly(a)linaro.org> --- Tested on SDM845/pm8998 (OnePlus 6) --- drivers/gpio/qcom_pmic_gpio.c | 27 +++++---------------------- 1 file changed, 5 insertions(+), 22 deletions(-) diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index 80fee841ee3f..f2ef4e5ce144 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -68,19 +68,8 @@ #define REG_EN_CTL 0x46 #define REG_EN_CTL_ENABLE (1 << 7) -/** - * pmic_gpio_match_data - platform specific configuration - * - * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them. - * This is a workaround for an unknown bug on some platforms where trying to write the - * GPIO configuration registers causes the board to hang. - */ -enum pmic_gpio_quirks { - QCOM_PMIC_QUIRK_READONLY = (1 << 0), -}; - struct qcom_pmic_gpio_data { uint32_t pid; /* Peripheral ID on SPMI bus */ bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */ u32 pin_count; @@ -127,15 +116,10 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned int offset, bool input, int value) { struct qcom_pmic_gpio_data *plat = dev_get_plat(dev); uint32_t gpio_base = plat->pid + REG_OFFSET(offset); - ulong quirks = dev_get_driver_data(dev); int ret = 0; - /* Some PMICs don't like their GPIOs being configured */ - if (quirks & QCOM_PMIC_QUIRK_READONLY) - return 0; - /* Disable the GPIO */ ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, REG_EN_CTL_ENABLE, 0); if (ret < 0) @@ -277,9 +261,8 @@ static const struct dm_gpio_ops qcom_gpio_ops = { static int qcom_gpio_bind(struct udevice *dev) { struct qcom_pmic_gpio_data *plat = dev_get_plat(dev); - ulong quirks = dev_get_driver_data(dev); struct udevice *child; struct driver *drv; int ret; @@ -291,9 +274,9 @@ static int qcom_gpio_bind(struct udevice *dev) /* Bind the GPIO driver as a child of the PMIC. */ ret = device_bind_with_driver_data(dev, drv, dev->name, - quirks, dev_ofnode(dev), &child); + 0, dev_ofnode(dev), &child); if (ret) return log_msg_ret("bind", ret); dev_set_plat(child, plat); @@ -360,13 +343,13 @@ static int qcom_gpio_probe(struct udevice *dev) static const struct udevice_id qcom_gpio_ids[] = { { .compatible = "qcom,pm8916-gpio" }, { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ - { .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, + { .compatible = "qcom,pm8998-gpio" }, { .compatible = "qcom,pms405-gpio" }, - { .compatible = "qcom,pm6125-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, - { .compatible = "qcom,pm8150-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, - { .compatible = "qcom,pm8550-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, + { .compatible = "qcom,pm6125-gpio" }, + { .compatible = "qcom,pm8150-gpio" }, + { .compatible = "qcom,pm8550-gpio" }, { } }; U_BOOT_DRIVER(qcom_pmic_gpio) = { -- 2.46.0

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[PATCH v2 0/2] qcom: allow msm_gpio to set special pins direction & value
by Neil Armstrong 02 Oct '24

02 Oct '24

After struct msm_special_pin_data was introduced in [1], use the data to setup the pin direction and/or value if supported by the pin data. Add the proper msm_special_pin_data for sm8250 after sm8550 and sm8650. [1] https://lore.kernel.org/all/20240528-topic-sm8x50-pinctrl-pinconf-v1-0-54d1… Signed-off-by: Neil Armstrong <neil.armstrong(a)linaro.org> --- Changes in v2: - dropped last line of sm8250_pin_offsets - Link to v1: https://lore.kernel.org/r/20240910-topic-sm8x50-msm-gpio-special-pins-sm825… --- Neil Armstrong (2): gpio: msm: add support for special pins pinctr: qcom: sm8250: add special pins pins configuration data drivers/gpio/msm_gpio.c | 97 ++++++++++++++++++++++++++++++++--- drivers/pinctrl/qcom/pinctrl-sm8250.c | 42 +++++++++++++-- 2 files changed, 127 insertions(+), 12 deletions(-) --- base-commit: ca55cf8104c0dd78aae45fa66dd8400ef1b3d0ac change-id: 20240910-topic-sm8x50-msm-gpio-special-pins-sm8250-943311b483e2 Best regards, -- Neil Armstrong <neil.armstrong(a)linaro.org>

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[PATCH 0/2] phy: qcom: add QMP UFS PHY support
by neil.armstrong＠linaro.org 02 Oct '24

02 Oct '24

This serie imports the QMP UFS PHY headers then adds the QMP PHY driver in order to support enabling the UFS PHY on the SDM845, SM8250, SM8550 and SM8650 platforms. Signed-off-by: Neil Armstrong <neil.armstrong(a)linaro.org> --- Bhupesh Sharma (2): phy: qcom: Import QMP phy related header files from Linux phy: qcom: Add QMP UFS PHY driver drivers/phy/qcom/Kconfig | 6 + drivers/phy/qcom/Makefile | 1 + drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v2.h | 25 + drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v3.h | 21 + drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v4.h | 31 + drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v5.h | 32 + drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v6.h | 38 + drivers/phy/qcom/phy-qcom-qmp-pcs-v2.h | 43 + drivers/phy/qcom/phy-qcom-qmp-pcs-v3.h | 145 +++ drivers/phy/qcom/phy-qcom-qmp-pcs-v4.h | 135 +++ drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v3.h | 111 ++ drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v4.h | 123 +++ drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v6.h | 89 ++ drivers/phy/qcom/phy-qcom-qmp-qserdes-com.h | 140 +++ drivers/phy/qcom/phy-qcom-qmp-qserdes-pll.h | 69 ++ .../phy/qcom/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 52 + drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v3.h | 68 ++ drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v4.h | 233 ++++ drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx.h | 205 ++++ drivers/phy/qcom/phy-qcom-qmp-ufs.c | 1116 ++++++++++++++++++++ drivers/phy/qcom/phy-qcom-qmp.h | 115 ++ 21 files changed, 2798 insertions(+) --- base-commit: ca55cf8104c0dd78aae45fa66dd8400ef1b3d0ac change-id: 20240910-topic-ufs-qcom-phy-c3d5d0f4138d Best regards, -- Neil Armstrong <neil.armstrong(a)linaro.org>

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[PATCH v3 0/3] Support for Qualcomm sm8150 SoC
by Julius Lehmann 02 Oct '24

02 Oct '24

This series picks up the work from Volodymyr Babchuk (https://lore.kernel.org/u-boot/20240306005230.2638972-1-volodymyr_babchuk@e…). clk and pinctrl drivers are adjusted to work similarly to existing qcom drivers. I could only test this using android boot chainloading. Fixed wrong register values in sm8150_clks, alphabetic ordering and added GCC_SDCC2_APPS_CLK rate setting. Thanks for all the help again! Signed-off-by: Julius Lehmann <lehmanju(a)devpi.de> --- Changes in v3: - fix: config: alphabetic ordering in Kconfig and Makefile - fix: clk: qcom: sm8150 if expression in clk_enable now correct - add: clk: qcom: sm8150 initialize GCC_SDCC2_APPS_CLK (similar to other clock drivers) - fix: clk: qcom: sm8150 GCC_UFS_* clock registers were wrong, copied correct ones over from Linux - Link to v2: https://lore.kernel.org/r/20240911-sm8150-patches-v2-0-0a32c6b6db1a@devpi.de Changes in v2: - fix: clk: qcom: sm8150 command registers for phy_aux_clk (usb) - refactor: pinctrl: qcom: sm8150 use special_pin_start and special_pins_data - Link to v1: https://lore.kernel.org/r/20240909155315.307026-1-lehmanju@devpi.de --- Julius Lehmann (3): clk: qcom: add driver for SM8150 SoC pinctrl: qcom: add driver for SM8150 SoC config: qcom: add sm8150 to qcom_defconfig configs/qcom_defconfig | 2 + drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-sm8150.c | 319 ++++++++++++++++++++++++++++++++++ drivers/pinctrl/qcom/Kconfig | 8 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8150.c | 156 +++++++++++++++++ 7 files changed, 496 insertions(+) --- base-commit: 78d898eec080b02059c8dc09318b8761044fea85 change-id: 20240910-sm8150-patches-559cc2475ded Best regards, -- Julius Lehmann <lehmanju(a)devpi.de>

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[PATCH v2 0/3] dwc3: gadget: properly fix cache operations
by Neil Armstrong 02 Oct '24

02 Oct '24

We experience huge problems with cache handling on Qualcomm systems, and it appears the dcache handling in the DWC3 gadget code is quite wrong and causes operational issues. This serie fixes the dcache operations on unaligned data, and properly invalidate buffers when reading back data from hardware. Signed-off-by: Neil Armstrong <neil.armstrong(a)linaro.org> --- Changes in v2: - Fix typo in drivers/usb/dwc3/core.h and rewrite patch 1 commit message - Link to v1: https://lore.kernel.org/r/20240719-u-boot-dwc3-gadget-dcache-fixup-v1-0-58a… --- Neil Armstrong (3): usb: dwc3: allocate setup_buf with dma_alloc_coherent() usb: dwc3: fix dcache flush range calculation usb: dwc3: invalidate dcache on buffer used in interrupt handling drivers/usb/dwc3/core.h | 2 ++ drivers/usb/dwc3/ep0.c | 6 ++++-- drivers/usb/dwc3/gadget.c | 10 ++++++---- drivers/usb/dwc3/io.h | 13 ++++++++++++- 4 files changed, 24 insertions(+), 7 deletions(-) --- base-commit: 3f772959501c99fbe5aa0b22a36efe3478d1ae1c change-id: 20240719-u-boot-dwc3-gadget-dcache-fixup-ea1e92758663 Best regards, -- Neil Armstrong <neil.armstrong(a)linaro.org>

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[GIT PULL] Please pull u-boot-dfu-20240930
by Mattijs Korpershoek 02 Oct '24

02 Oct '24

Hi Tom, Please find some fixes for master: - Fix Kconfig dependencies for DFU_OVER_USB CI job: - https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/22468/ PS: I know it's a bit late, if you'd prefer to defer this to next release, let me know. Thanks, Mattijs The following changes since commit 5f044932413694475422d4b16607dfcf9aff8781: scripts/Makefile.lib: do not include CONFIG_DEVICE_TREE_INCLUDES in dtsi_include_list (2024-09-10 11:31:54 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-dfu.git tags/u-boot-dfu-20240930 for you to fetch changes up to 2f9c472dd7a91bc2d6e7840a550edcd257ff8b57: dfu: fix Kconfig dependencies (2024-09-13 17:41:18 +0200) ---------------------------------------------------------------- u-boot-dfu-20240930 - Fix Kconfig dependencies for DFU_OVER_USB ---------------------------------------------------------------- Jerome Forissier (1): dfu: fix Kconfig dependencies drivers/dfu/Kconfig | 2 +- drivers/usb/gadget/Kconfig | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)

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[PATCH 00/26] Support display (and even more) on the BSH SMM S2/PRO boards
by Dario Binacchi 01 Oct '24

01 Oct '24

This series was created out of the need to supportsimple-framebuffer for BSH boards SMM_S2 and SMM_S2PRO. To achieve this goal, it was necessary to develop additional code and/or drivers for all the required components (i. e. clock, power domain, video, etc.). This series has a Linux counterpart that will also be submitted upstream as soon as possible. Furthermore, given the overlap in topics with the recent series [1], we are open to collaborate on the common parts to ensure proper development. [1] https://lore.kernel.org/all/20240910101344.110633-1-miquel.raynal@bootlin.c… Dario Binacchi (6): boot: fdt_simplefb: add a debug message video: mxsfb: support simple frame-buffer video: bridge: samsung: support simple frame-buffer imx8mn_bsh_smm_s2/pro: support simple frame-buffer imx8mn_bsh_smm_s2/pro: enable simple frame-buffer imx8mn_bsh_smm_s2/pro: add splash screen with BSH logo Michael Trimarchi (20): clk: Propagate clk_set_rate() if CLK_SET_PARENT_RATE present for gate and mux clk: imx8mn: Prevent clock critical path from disabling during reparent and set_rate clk: imx8mm: Prevent clock critical path from disabling during reparent and set_rate clk: clk-uclass: Implement CLK_OPS_PARENT_ENABLE clk: imx8mm: Mark IMX8MM_SYS_PLL2 and IMX8MM_SYS_PLL3 as enabled clk: imx8mn: Mark IMX8MN_SYS_PLL2 and IMX8MN_SYS_PLL3 as enabled clk: imx8mn: add video clocks support power: Add iMX8M block ctrl driver for dispmix video: Add video link framework video: bridge: Add check_timing interface video: dsi_host: add disable host interface video: Update mxsfb video drivers for iMX8MM/iMX8MN display video: Enable DM_UC_FLAG_SEQ_ALIAS for display and bridge phy: dphy: add support to calculate the timing based on hs_clk_rate phy: dphy: Correct lpx parameter and its derivatives(ta_{get,go,sure}) phy: dphy: Correct clk_pre parameter lib: div64: sync with Linux video: bridge: Add Samsung DSIM bridge video: Add Synaptics R63353 panel driver imx8mn_bsh_smm_s2/pro: Enable display on reference design .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 23 + board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c | 99 ++ boot/fdt_simplefb.c | 2 + common/stdio.c | 4 + configs/imx8mn_bsh_smm_s2_defconfig | 21 + configs/imx8mn_bsh_smm_s2pro_defconfig | 21 + drivers/clk/clk-gate.c | 1 + drivers/clk/clk-mux.c | 2 +- drivers/clk/clk-uclass.c | 67 +- drivers/clk/clk.c | 9 + drivers/clk/imx/clk-imx8mm.c | 73 +- drivers/clk/imx/clk-imx8mn.c | 131 +- drivers/phy/meson-axg-mipi-dphy.c | 2 +- drivers/phy/phy-core-mipi-dphy.c | 36 +- drivers/power/domain/Kconfig | 6 + drivers/power/domain/Makefile | 1 + drivers/power/domain/imx8m-blk-ctrl.c | 438 +++++ drivers/power/domain/imx8m-power-domain.c | 213 ++- drivers/video/Kconfig | 14 + drivers/video/Makefile | 2 + drivers/video/bridge/Kconfig | 13 + drivers/video/bridge/Makefile | 1 + drivers/video/bridge/samsung-dsi-host.c | 1576 +++++++++++++++++ drivers/video/bridge/samsung-dsim.c | 151 ++ drivers/video/bridge/samsung-dsim.h | 20 + drivers/video/bridge/video-bridge-uclass.c | 11 + drivers/video/display-uclass.c | 1 + drivers/video/dsi-host-uclass.c | 10 + drivers/video/mxsfb.c | 144 +- drivers/video/synaptics-r63353.c | 228 +++ drivers/video/video_link.c | 529 ++++++ include/clk.h | 9 + include/configs/imx8mn_bsh_smm_s2.h | 1 + include/configs/imx8mn_bsh_smm_s2_common.h | 4 + include/configs/imx8mn_bsh_smm_s2pro.h | 1 + include/dsi_host.h | 8 + include/linux/clk-provider.h | 1 + include/linux/math64.h | 110 ++ include/phy-mipi-dphy.h | 3 + include/video_bridge.h | 20 + include/video_link.h | 19 + tools/logos/bsh.bmp | Bin 0 -> 10644 bytes 42 files changed, 3942 insertions(+), 83 deletions(-) create mode 100644 drivers/power/domain/imx8m-blk-ctrl.c create mode 100644 drivers/video/bridge/samsung-dsi-host.c create mode 100644 drivers/video/bridge/samsung-dsim.c create mode 100644 drivers/video/bridge/samsung-dsim.h create mode 100644 drivers/video/synaptics-r63353.c create mode 100644 drivers/video/video_link.c create mode 100644 include/video_link.h create mode 100644 tools/logos/bsh.bmp -- 2.43.0

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[PATCH 0/3] env: mmc: fix use of two separate partitions with proper type GUID
by Rasmus Villemoes 01 Oct '24

01 Oct '24

I always define a disk layout with two separate partitions for the two copies of the U-Boot environment and, being the one who introduced the type GUID for such partitions, of course also set those partitions' type GUID appropriately. This has worked just fine, but, it turns out, only because I've never had CONFIG_PARTITION_TYPE_GUID enabled on any of my boards; I've always just set the offsets of the two partitions via the config variables CONFIG_ENV_OFFSET(,_REDUND). I didn't even know that env/mmc.c had learnt to look for the env partition based on the type GUID, or that that would overrule the ENV_OFFSET config variables, until I experienced weird random corruption while doing bringup for an stm32 board, where PARTITION_TYPE_GUID is automatically set because it is select'ed by CMD_STM32PROG. These patches try to fix the code to fit my scheme, while not changing anything for existing setups that use the two-copies-one-partition scheme, other than complaining loudly if the system is misconfigured and avoiding such random corruption of neighbouring partitions. Rasmus Villemoes (3): env: mmc: refactor mmc_offset_try_partition() env: mmc: do not return an offset before the start of the partition env: mmc: rework mmc_env_partition_by_guid() to work with two separate partitions env/mmc.c | 95 ++++++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 77 insertions(+), 18 deletions(-) -- 2.46.0

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