July 2024 - U-Boot

[PATCH 1/2] power: regulator: Do not call set_suspend_value with -ENODATA
by Jonas Karlman 25 Sep '24

25 Sep '24

On some boards a PMIC regulator is flagged with regulator-on-in-suspend and does not define any suspend or max microvolt, e.g. on Radxa ROCK 3A: vcc_ddr: DCDC_REG3 { regulator-name = "vcc_ddr"; regulator-always-on; regulator-boot-on; regulator-initial-mode = <0x2>; regulator-state-mem { regulator-on-in-suspend; }; }; This result in suspend_uV having the value -ENODATA after probe. This negative voltage, -ENODATA, gets missinterpreted and result in an unexpected voltage being set by autoset. E.g. on Radxa ROCK 3A the vcc_ddr regulator by default have a normal and suspend voltage value of 0.5v. However, due to this missinterpretation the suspend voltage end up beind set to 0.5625v instead. Fix this by skip calling regulator_set_suspend_value() in autoset and also protect calling set value ops when input value is -ENODATA. Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- drivers/power/regulator/regulator-uclass.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 88a8525b3c47..03d39587b315 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -60,6 +60,8 @@ int regulator_set_value(struct udevice *dev, int uV) return -EINVAL; if (uc_pdata->max_uV != -ENODATA && uV > uc_pdata->max_uV) return -EINVAL; + if (uV == -ENODATA) + return -EINVAL; if (!ops || !ops->set_value) return -ENOSYS; @@ -90,6 +92,8 @@ int regulator_set_suspend_value(struct udevice *dev, int uV) return -EINVAL; if (uc_pdata->max_uV != -ENODATA && uV > uc_pdata->max_uV) return -EINVAL; + if (uV == -ENODATA) + return -EINVAL; if (!ops->set_suspend_value) return -ENOSYS; @@ -141,6 +145,8 @@ int regulator_set_current(struct udevice *dev, int uA) return -EINVAL; if (uc_pdata->max_uA != -ENODATA && uA > uc_pdata->max_uA) return -EINVAL; + if (uA == -ENODATA) + return -EINVAL; if (!ops || !ops->set_current) return -ENOSYS; @@ -299,7 +305,7 @@ int regulator_autoset(struct udevice *dev) if (ret == -ENOSYS) ret = 0; - if (!ret && uc_pdata->suspend_on) { + if (!ret && uc_pdata->suspend_on && uc_pdata->suspend_uV != -ENODATA) { ret = regulator_set_suspend_value(dev, uc_pdata->suspend_uV); if (ret == -ENOSYS) ret = 0; -- 2.45.2

2 2

[PATCH 1/4] power: regulator: Trigger probe of regulators which are always-on or boot-on
by Marek Vasut 25 Sep '24

25 Sep '24

In case a regulator DT node contains regulator-always-on or regulator-boot-on property, make sure the regulator gets correctly configured by U-Boot on start up. Unconditionally probe such regulator drivers. This is a preparatory patch for introduction of .regulator_post_probe() which would trigger the regulator configuration. Parsing of regulator-always-on and regulator-boot-on DT property has been moved to regulator_post_bind() as the information is required early, the rest of the DT parsing has been kept in regulator_pre_probe() to avoid slowing down the boot process. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Ben Wolsieffer <benwolsieffer(a)gmail.com> Cc: Caleb Connolly <caleb.connolly(a)linaro.org> Cc: Chris Morgan <macromorgan(a)hotmail.com> Cc: Dragan Simic <dsimic(a)manjaro.org> Cc: Eugen Hristev <eugen.hristev(a)collabora.com> Cc: Francesco Dolcini <francesco.dolcini(a)toradex.com> Cc: Heinrich Schuchardt <xypron.glpk(a)gmx.de> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Jagan Teki <jagan(a)amarulasolutions.com> Cc: Jonas Karlman <jonas(a)kwiboo.se> Cc: Kever Yang <kever.yang(a)rock-chips.com> Cc: Kostya Porotchkin <kostap(a)marvell.com> Cc: Matteo Lisi <matteo.lisi(a)engicam.com> Cc: Mattijs Korpershoek <mkorpershoek(a)baylibre.com> Cc: Max Krummenacher <max.krummenacher(a)toradex.com> Cc: Neil Armstrong <neil.armstrong(a)linaro.org> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Philipp Tomsich <philipp.tomsich(a)vrull.eu> Cc: Quentin Schulz <quentin.schulz(a)cherry.de> Cc: Sam Day <me(a)samcday.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Sumit Garg <sumit.garg(a)linaro.org> Cc: Svyatoslav Ryhel <clamor95(a)gmail.com> Cc: Thierry Reding <treding(a)nvidia.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: Volodymyr Babchuk <Volodymyr_Babchuk(a)epam.com> Cc: u-boot-amlogic(a)groups.io Cc: u-boot-qcom(a)groups.io Cc: u-boot(a)dh-electronics.com Cc: u-boot(a)lists.denx.de Cc: uboot-stm32(a)st-md-mailman.stormreply.com --- drivers/power/regulator/regulator-uclass.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 66fd531da04..ccc4ef33d83 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -433,6 +433,8 @@ static int regulator_post_bind(struct udevice *dev) const char *property = "regulator-name"; uc_pdata = dev_get_uclass_plat(dev); + uc_pdata->always_on = dev_read_bool(dev, "regulator-always-on"); + uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on"); /* Regulator's mandatory constraint */ uc_pdata->name = dev_read_string(dev, property); @@ -444,13 +446,21 @@ static int regulator_post_bind(struct udevice *dev) return -EINVAL; } - if (regulator_name_is_unique(dev, uc_pdata->name)) - return 0; + if (!regulator_name_is_unique(dev, uc_pdata->name)) { + debug("'%s' of dev: '%s', has nonunique value: '%s\n", + property, dev->name, uc_pdata->name); + return -EINVAL; + } - debug("'%s' of dev: '%s', has nonunique value: '%s\n", - property, dev->name, uc_pdata->name); + /* + * In case the regulator has regulator-always-on or + * regulator-boot-on DT property, trigger probe() to + * configure its default state during startup. + */ + if (uc_pdata->always_on && uc_pdata->boot_on) + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); - return -EINVAL; + return 0; } static int regulator_pre_probe(struct udevice *dev) @@ -473,8 +483,6 @@ static int regulator_pre_probe(struct udevice *dev) -ENODATA); uc_pdata->max_uA = dev_read_u32_default(dev, "regulator-max-microamp", -ENODATA); - uc_pdata->always_on = dev_read_bool(dev, "regulator-always-on"); - uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on"); uc_pdata->ramp_delay = dev_read_u32_default(dev, "regulator-ramp-delay", 0); uc_pdata->force_off = dev_read_bool(dev, "regulator-force-boot-off"); -- 2.43.0

7 50

[PATCH 00/14] testb: Various tweaks and fixes for Labgrid
by Simon Glass 25 Sep '24

25 Sep '24

This series includes a number of mostly unrelated changes which are in service of running U-Boot on a lab using Labgrid. Changes in v2: - Add new patch to update u-boot.cfg with CFG_... options Simon Glass (14): trace: Update test to tolerate different trace-cmd version dm: core: Enhance comments on bind_drivers_pass() initcall: Correct use of relocation offset am33xx: Provide a function to set up the debug UART sunxi: Mark scp as optional google: Disable TPMv2 on most Chromebooks meson: Correct driver declaration for meson_axg_gpio test: Make bootstd init run only on sandbox log: Allow tests to pass with CONFIG_LOGF_FUNC_PAD set test: dm: Show failing driver name test: Decode exceptions only with sandbox test: Check help output Update u-boot.cfg to include CFG also smbios: Correct error handling when writing tables arch/arm/dts/sunxi-u-boot.dtsi | 1 + arch/arm/mach-omap2/am33xx/board.c | 18 +++++++++++++++--- configs/chromebook_link64_defconfig | 1 + configs/chromebook_link_defconfig | 1 + configs/chromebook_samus_defconfig | 1 + configs/chromebook_samus_tpl_defconfig | 1 + configs/nyan-big_defconfig | 4 +--- configs/snow_defconfig | 1 + drivers/core/lists.c | 16 ++++++++++++++++ drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c | 2 +- drivers/pinctrl/meson/pinctrl-meson-axg.c | 4 ++-- drivers/pinctrl/meson/pinctrl-meson-axg.h | 2 +- drivers/pinctrl/meson/pinctrl-meson-g12a.c | 4 ++-- lib/initcall.c | 6 ++++-- lib/smbios.c | 10 ++++++++-- scripts/Makefile.autoconf | 2 +- test/py/tests/test_dm.py | 5 ++++- test/py/tests/test_help.py | 6 +++++- test/py/tests/test_log.py | 11 +++++++---- test/py/tests/test_trace.py | 6 +++--- test/py/tests/test_ut.py | 1 + test/py/u_boot_console_sandbox.py | 2 +- test/py/u_boot_spawn.py | 10 ++++++---- 23 files changed, 84 insertions(+), 31 deletions(-) -- 2.34.1

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[PATCH 1/4] lib: sha256: add feature sha256_hmac
by Philippe Reynes 20 Sep '24

20 Sep '24

Adds the support of the hmac based on sha256. This implementation is based on rfc2104. Signed-off-by: Philippe Reynes <philippe.reynes(a)softathome.com> --- include/u-boot/sha256.h | 4 ++++ lib/sha256.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/include/u-boot/sha256.h b/include/u-boot/sha256.h index a4fe176c0b4..7aa4c54d0d4 100644 --- a/include/u-boot/sha256.h +++ b/include/u-boot/sha256.h @@ -24,4 +24,8 @@ void sha256_finish(sha256_context * ctx, uint8_t digest[SHA256_SUM_LEN]); void sha256_csum_wd(const unsigned char *input, unsigned int ilen, unsigned char *output, unsigned int chunk_sz); +void sha256_hmac(const unsigned char *key, int keylen, + const unsigned char *input, unsigned int ilen, + unsigned char *output); + #endif /* _SHA256_H */ diff --git a/lib/sha256.c b/lib/sha256.c index 665ba6f152e..64f6b48974b 100644 --- a/lib/sha256.c +++ b/lib/sha256.c @@ -298,3 +298,43 @@ void sha256_csum_wd(const unsigned char *input, unsigned int ilen, sha256_finish(&ctx, output); } + +/* + * Output = HMAC-SHA-256( input buffer, hmac key ) + */ +void sha256_hmac(const unsigned char *key, int keylen, + const unsigned char *input, unsigned int ilen, + unsigned char *output) +{ + int i; + sha256_context ctx; + unsigned char k_ipad[64]; + unsigned char k_opad[64]; + unsigned char tmpbuf[32]; + + memset(k_ipad, 0x36, 64); + memset(k_opad, 0x5C, 64); + + for (i = 0; i < keylen; i++) { + if (i >= 64) + break; + + k_ipad[i] ^= key[i]; + k_opad[i] ^= key[i]; + } + + sha256_starts(&ctx); + sha256_update(&ctx, k_ipad, 64); + sha256_update(&ctx, input, ilen); + sha256_finish(&ctx, tmpbuf); + + sha256_starts(&ctx); + sha256_update(&ctx, k_opad, 64); + sha256_update(&ctx, tmpbuf, 32); + sha256_finish(&ctx, output); + + memset(k_ipad, 0, 64); + memset(k_opad, 0, 64); + memset(tmpbuf, 0, 32); + memset(&ctx, 0, sizeof(sha256_context)); +} -- 2.25.1

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[PATCH v2 0/5] finish using .dtso for overlay source files
by Rasmus Villemoes 20 Sep '24

20 Sep '24

This is a followup to the patches that landed in 2024.01 and nearly made sure that source files for producing .dtbo files use the .dtso extension. In the same release, a few new .dts files snuck in, and there was also some test code involving .dtbo -> .dtbo.S -> .dtbo.o I didn't really know how to handle at the time. This should finish the job, bring us in sync with linux (at least in this respect), and drop the .dts -> .dtbo build rule. Patch 3 depends on 2, and patch 5 depends on the rest. v2: Fix oversight in the imx8mp-dhcom files. Now actually tested on CI, and seems to pass except for the known cyclic false positive: https://dev.azure.com/u-boot/u-boot/_build/results?buildId=8897&view=logs&j… Rasmus Villemoes (5): arm64: dts: imx8mp: rename DHCOM SoM overlays to .dtso kbuild: Allow DTB overlays to built into .dtbo.S files test: overlay: rename overlay source files to .dtso test/py: efi_capsule: rename device tree overlay source to .dtso kbuild: Disallow DTB overlays to built from .dts named source files ...> imx8mp-dhcom-pdk-overlay-eth2xfast.dtso} | 0 ... => imx8mp-dhcom-pdk3-overlay-rev100.dtso} | 0 ...> imx8mp-dhcom-som-overlay-eth1xfast.dtso} | 0 ...> imx8mp-dhcom-som-overlay-eth2xfast.dtso} | 2 +- ...s => imx8mp-dhcom-som-overlay-rev100.dtso} | 0 scripts/Makefile.lib | 23 +++++++++++++++---- test/overlay/Makefile | 4 ++-- test/overlay/cmd_ut_overlay.c | 8 +++---- ...cked.dts => test-fdt-overlay-stacked.dtso} | 0 ...-fdt-overlay.dts => test-fdt-overlay.dtso} | 0 test/py/tests/test_efi_capsule/conftest.py | 6 ++--- .../{version.dts => version.dtso} | 0 12 files changed, 29 insertions(+), 14 deletions(-) rename arch/arm/dts/{imx8mp-dhcom-pdk-overlay-eth2xfast.dts => imx8mp-dhcom-pdk-overlay-eth2xfast.dtso} (100%) rename arch/arm/dts/{imx8mp-dhcom-pdk3-overlay-rev100.dts => imx8mp-dhcom-pdk3-overlay-rev100.dtso} (100%) rename arch/arm/dts/{imx8mp-dhcom-som-overlay-eth1xfast.dts => imx8mp-dhcom-som-overlay-eth1xfast.dtso} (100%) rename arch/arm/dts/{imx8mp-dhcom-som-overlay-eth2xfast.dts => imx8mp-dhcom-som-overlay-eth2xfast.dtso} (91%) rename arch/arm/dts/{imx8mp-dhcom-som-overlay-rev100.dts => imx8mp-dhcom-som-overlay-rev100.dtso} (100%) rename test/overlay/{test-fdt-overlay-stacked.dts => test-fdt-overlay-stacked.dtso} (100%) rename test/overlay/{test-fdt-overlay.dts => test-fdt-overlay.dtso} (100%) rename test/py/tests/test_efi_capsule/{version.dts => version.dtso} (100%) -- 2.45.2

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[PATCH v2 00/14] spl: mmc: Some tweaks for SPL, particularly with MMC
by Simon Glass 20 Sep '24

20 Sep '24

This series includes various minor fixes and tweaks found when trying to reduce the size of MMC code in SPL. Changes in v2: - Avoid changing comment - Various updates to log messages - Drop an unnecessary cast - Update commit message to mention the runtime impact - Leave assert() alone since it is only compiled in with LOG_DEBUG - Update 'return ret' to 'return 0' when ret is known to be 0 - Use uint for arg to spl_mmc_get_device_index() Simon Glass (14): rockchip: Move the default timer init to a common file spl: Correct use of CMD_BOOTI and CMD_BOOTZ spl: Remove some #ifdefs in spl_parse_image_header() spl: Remove remaining #ifdef in spl_parse_image_header() mmc: Use logging instead of printf() mmc: Use logging instead of pr_err() log: Avoid including function names by default spl: mmc: Drop checks for CONFIG_SPL_LIBCOMMON_SUPPORT spl: mmc: Handle error codes consistently spl: mmc: Adjust args of spl_mmc_find_device() spl: mmc: Try to clean up raw-mode options spl: Use unified inline functions for spl_load_info spl: Create a function to init spl_load_info blk: Correct comment for blk_get_devnum_by_uclass_idname() arch/arm/include/asm/arch-rockchip/timer.h | 3 + arch/arm/mach-imx/imx8m/soc.c | 2 + arch/arm/mach-imx/spl_imx_romapi.c | 27 +-- arch/arm/mach-rockchip/Makefile | 4 +- arch/arm/mach-rockchip/spl.c | 21 +-- arch/arm/mach-rockchip/spl_common.c | 36 ++++ arch/arm/mach-rockchip/tpl.c | 30 +--- arch/arm/mach-sunxi/spl_spi_sunxi.c | 3 +- .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 4 +- common/log_console.c | 4 +- common/spl/Kconfig | 52 +++--- common/spl/spl.c | 30 ++-- common/spl/spl_blk_fs.c | 9 +- common/spl/spl_ext.c | 3 +- common/spl/spl_fat.c | 10 +- common/spl/spl_mmc.c | 159 ++++++++---------- common/spl/spl_nand.c | 4 +- common/spl/spl_net.c | 3 +- common/spl/spl_nor.c | 6 +- common/spl/spl_ram.c | 3 +- common/spl/spl_semihosting.c | 4 +- common/spl/spl_spi.c | 4 +- common/spl/spl_ymodem.c | 4 +- configs/am335x_guardian_defconfig | 2 +- configs/am335x_pdu001_defconfig | 2 +- configs/am3517_evm_defconfig | 2 +- configs/am62ax_evm_a53_defconfig | 1 + configs/am62ax_evm_r5_defconfig | 1 + configs/am62px_evm_a53_defconfig | 1 + configs/am62px_evm_r5_defconfig | 1 + configs/am62x_beagleplay_a53_defconfig | 1 + configs/am62x_beagleplay_r5_defconfig | 1 + configs/am62x_evm_a53_defconfig | 1 + configs/am62x_evm_r5_defconfig | 1 + configs/am64x_evm_a53_defconfig | 1 + configs/am64x_evm_r5_defconfig | 1 + configs/am65x_evm_a53_defconfig | 1 + configs/am65x_evm_r5_defconfig | 1 + configs/brppt2_defconfig | 2 +- configs/brsmarc1_defconfig | 2 +- configs/cgtqmx8_defconfig | 1 + configs/chromebit_mickey_defconfig | 2 +- configs/chromebook_jerry_defconfig | 2 +- configs/chromebook_minnie_defconfig | 2 +- configs/chromebook_speedy_defconfig | 2 +- configs/ci20_mmc_defconfig | 1 + configs/da850evm_defconfig | 2 +- configs/da850evm_nand_defconfig | 2 +- configs/deneb_defconfig | 1 + configs/display5_defconfig | 2 +- configs/display5_factory_defconfig | 2 +- configs/draco-rastaban_defconfig | 2 +- configs/draco-thuban_defconfig | 2 +- .../gardena-smart-gateway-at91sam_defconfig | 2 +- configs/giedi_defconfig | 1 + configs/imx28_xea_defconfig | 1 + configs/imx28_xea_sb_defconfig | 1 + configs/imx6q_logic_defconfig | 2 +- configs/imx8mm-cl-iot-gate-optee_defconfig | 1 + configs/imx8mm-cl-iot-gate_defconfig | 1 + configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 + configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 + configs/imx8mm-mx8menlo_defconfig | 1 + configs/imx8mm-phygate-tauri-l_defconfig | 1 + configs/imx8mm_beacon_defconfig | 1 + configs/imx8mm_beacon_fspi_defconfig | 1 + configs/imx8mm_data_modul_edm_sbc_defconfig | 1 + configs/imx8mm_evk_defconfig | 1 + configs/imx8mm_evk_fspi_defconfig | 1 + configs/imx8mm_phg_defconfig | 1 + configs/imx8mm_venice_defconfig | 1 + configs/imx8mn_beacon_2g_defconfig | 1 + configs/imx8mn_beacon_defconfig | 1 + configs/imx8mn_beacon_fspi_defconfig | 1 + configs/imx8mn_bsh_smm_s2_defconfig | 1 + configs/imx8mn_bsh_smm_s2pro_defconfig | 1 + configs/imx8mn_ddr4_evk_defconfig | 1 + configs/imx8mn_evk_defconfig | 1 + configs/imx8mn_var_som_defconfig | 1 + configs/imx8mn_venice_defconfig | 1 + configs/imx8mp-icore-mx8mp-edimm2.2_defconfig | 1 + configs/imx8mp_beacon_defconfig | 1 + configs/imx8mp_data_modul_edm_sbc_defconfig | 1 + configs/imx8mp_debix_model_a_defconfig | 1 + configs/imx8mp_dhcom_pdk2_defconfig | 1 + configs/imx8mp_dhcom_pdk3_defconfig | 1 + configs/imx8mp_evk_defconfig | 1 + configs/imx8mp_rsb3720a1_4G_defconfig | 2 + configs/imx8mp_rsb3720a1_6G_defconfig | 1 + configs/imx8mp_venice_defconfig | 1 + configs/imx8mq_cm_defconfig | 1 + configs/imx8mq_evk_defconfig | 1 + configs/imx8mq_phanbell_defconfig | 1 + configs/imx8mq_reform2_defconfig | 1 + configs/imx8qm_mek_defconfig | 1 + configs/imx8qxp_mek_defconfig | 1 + configs/imx8ulp_evk_defconfig | 1 + configs/imx93-phyboard-segin_defconfig | 1 + configs/imx93_11x11_evk_defconfig | 1 + configs/imx93_11x11_evk_ld_defconfig | 1 + configs/imx93_var_som_defconfig | 1 + configs/imxrt1020-evk_defconfig | 1 + configs/imxrt1050-evk_defconfig | 1 + configs/imxrt1050-evk_fspi_defconfig | 1 + configs/imxrt1170-evk_defconfig | 1 + configs/iot2050_defconfig | 1 + configs/j7200_evm_a72_defconfig | 1 + configs/j7200_evm_r5_defconfig | 1 + configs/j721e_beagleboneai64_a72_defconfig | 1 + configs/j721e_beagleboneai64_r5_defconfig | 1 + configs/j721e_evm_a72_defconfig | 1 + configs/j721e_evm_r5_defconfig | 1 + configs/j721s2_evm_a72_defconfig | 1 + configs/j721s2_evm_r5_defconfig | 1 + configs/j722s_evm_a53_defconfig | 1 + configs/j722s_evm_r5_defconfig | 1 + configs/j784s4_evm_a72_defconfig | 1 + configs/j784s4_evm_r5_defconfig | 1 + configs/kontron-sl-mx8mm_defconfig | 1 + configs/kontron_pitx_imx8m_defconfig | 1 + configs/kontron_sl28_defconfig | 1 + configs/librem5_defconfig | 1 + configs/ls1021aiot_sdcard_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021aqds_sdcard_qspi_defconfig | 1 + configs/ls1021atsn_sdcard_defconfig | 1 + ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig | 1 + configs/msc_sm2s_imx8mp_defconfig | 1 + configs/omap35_logic_defconfig | 2 +- configs/omap35_logic_somlv_defconfig | 2 +- configs/omap3_logic_defconfig | 2 +- configs/omap3_logic_somlv_defconfig | 2 +- configs/phycore-imx8mm_defconfig | 1 + configs/phycore-imx8mp_defconfig | 1 + configs/phycore_am62x_a53_defconfig | 1 + configs/phycore_am62x_r5_defconfig | 1 + configs/phycore_am64x_a53_defconfig | 1 + configs/phycore_am64x_r5_defconfig | 1 + configs/pico-imx8mq_defconfig | 1 + configs/sama5d27_wlsom1_ek_mmc_defconfig | 2 +- .../sama5d27_wlsom1_ek_qspiflash_defconfig | 2 +- configs/sama5d2_icp_mmc_defconfig | 2 +- configs/sandbox_defconfig | 1 + configs/sandbox_noinst_defconfig | 1 + configs/sniper_defconfig | 2 +- configs/socfpga_secu1_defconfig | 2 +- configs/verdin-am62_a53_defconfig | 1 + configs/verdin-am62_r5_defconfig | 1 + configs/verdin-imx8mm_defconfig | 1 + configs/verdin-imx8mp_defconfig | 1 + drivers/mmc/mmc.c | 49 +++--- drivers/mmc/sdhci.c | 46 +++-- drivers/usb/gadget/f_sdp.c | 8 +- include/blk.h | 4 +- include/log.h | 16 +- include/spl.h | 60 ++++--- test/cmd/pinmux.c | 8 +- test/image/spl_load.c | 4 +- test/image/spl_load_os.c | 6 +- test/log/log_test.c | 4 +- 163 files changed, 429 insertions(+), 358 deletions(-) create mode 100644 arch/arm/mach-rockchip/spl_common.c -- 2.34.1

2 41

[PATCH] mtd: spi-nor: scale up timeout for full-chip erase
by Venkatesh Yadav Abbarapu 20 Sep '24

20 Sep '24

This patch fixes timeout issues seen on large NOR flash. For full-chip erase, where we use the SPINOR_OP_CHIP_ERASE (0xc7) opcode. Use a different timeout for full-chip erase than for other commands. [Ported from Linux kernel commit 09b6a377687b ("mtd: spi-nor: scale up timeout for full-chip erase") ] Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- drivers/mtd/spi/spi-nor-core.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 9a1801ba93..171c68787c 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -45,6 +45,12 @@ #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) +/* + * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up + * for larger flash + */ +#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) + #define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y)) struct sfdp_parameter_header { @@ -832,6 +838,20 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor) DEFAULT_READY_WAIT_JIFFIES); } +static int spi_nor_erase_chip_wait_till_ready(struct spi_nor *nor, unsigned long size) +{ + /* + * Scale the timeout linearly with the size of the flash, with + * a minimum calibrated to an old 2MB flash. We could try to + * pull these from CFI/SFDP, but these values should be good + * enough for now. + */ + unsigned long timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, + CHIP_ERASE_2MB_READY_WAIT_JIFFIES * + (unsigned long)(size / SZ_2M)); + return spi_nor_wait_till_ready_with_timeout(nor, timeout); +} + #ifdef CONFIG_SPI_FLASH_BAR /* * This "clean_bar" is necessary in a situation when one was accessing @@ -966,7 +986,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) { struct spi_nor *nor = mtd_to_spi_nor(mtd); bool addr_known = false; - u32 addr, len, rem; + u32 addr, len, rem, max_size; int ret, err; dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, @@ -980,6 +1000,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) addr = instr->addr; len = instr->len; + max_size = instr->len; instr->state = MTD_ERASING; addr_known = true; @@ -1012,7 +1033,13 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) addr += ret; len -= ret; - ret = spi_nor_wait_till_ready(nor); + if (max_size == mtd->size && + !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { + ret = spi_nor_erase_chip_wait_till_ready(nor, mtd->size); + } else { + ret = spi_nor_wait_till_ready(nor); + } + if (ret) goto erase_err; } -- 2.25.1

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[PATCH v4 0/6] rpi5: initial support
by Ivan T. Ivanov 19 Sep '24

19 Sep '24

Hi, These patches are slight update for patches posted earlier here[1]. They are adding basic support for RPi5 and are based on v2 series from Dmitry Malkin[2]. What changed: * Initial memory map now includes whole first 1GB of DRAM. At runtime, the firmware will adjust this size depending on whether an HDMI cable is plugged in or not. If there is HDMI monitor connected it will reserve framebufer memory region and will add simple-framebuffer device into devicetree. * Dynamically calculate bits per pixel in video driver. This works on all prevous RPi's models that I have. * I am dropping PCIe patch for now. I made some progress on porting changes from vendor Linux tree to U-Boot. Unfortunatly testing it is little bit tricky. They are many devices behind PCIe, but more or less all of them requires missing either "reset-controller" or "clock-controller" or "pin-controller" drivers. I was able to probe "cdns,macb" device, but access to ethernet PHY over MDIO bus is stucking. Then I ported "raspberrypi,rp1-adc" driver from vendor Linux tree, but it requires missing clock. And on top of that machine that I used for developing this crashed and I lost my PCIe changes :-|. Anyway. These patches allows me to boot current openSUSE Tumbleweed without modification. I can see serial console log and boot process on HDMI connected monitor. I think these patches should be enough for start. Please consider for inclusion. Thanks, Ivan [1] https://lore.kernel.org/all/20231218210341.30073-1-iivanov@suse.de/ [2] https://lore.kernel.org/all/CAKRNjQ0dsWozGo4n8g58m4cCEk3n=qx1R+L24WBgpo-iP1… Dmitry Malkin (2): rpi5: add initial memory map for bcm2712 rpi5: Use devicetree as alternative way to read IO base addresses Ivan T. Ivanov (4): rpi5: Use devicetree to retrieve board revision bcm2835: Dynamically calculate bytes per pixel parameter mmc: bcmstb: Add support for bcm2712 SD controller configs: rpi_arm64: enable SDHCI BCMSTB driver arch/arm/mach-bcm283x/include/mach/base.h | 5 +- arch/arm/mach-bcm283x/include/mach/mbox.h | 3 +- arch/arm/mach-bcm283x/include/mach/sdhci.h | 3 +- arch/arm/mach-bcm283x/include/mach/timer.h | 3 +- arch/arm/mach-bcm283x/include/mach/wdog.h | 3 +- arch/arm/mach-bcm283x/init.c | 74 ++++++++- board/raspberrypi/rpi/rpi.c | 22 ++- configs/rpi_arm64_defconfig | 1 + drivers/mmc/bcmstb_sdhci.c | 173 ++++++++++++++++++++- drivers/video/bcm2835.c | 18 ++- 10 files changed, 282 insertions(+), 23 deletions(-) -- 2.35.3

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[PATCH v2 0/2] riscv: spacemit: bananapi_f3: add support for Banana Pi F3 board
by Kongyang Liu 12 Sep '24

12 Sep '24

Banana Pi F3 board is a industrial grade RISC-V development board, it design with SpacemiT K1 8 core RISC-V chip, CPU integrates 2.0 TOPs AI computing power. 4G DDR and 16G eMMC onboard.2x GbE Ethernet prot, 4x USB 3.0 and PCIe for M.2 interface, support HDMI and Dual MIPI-CSI Camera. This patch introduces fundamental support for the Banana Pi F3 board, encompassing UART, CPU, and PLIC support. This ensures that U-Boot can operate in serial console mode. Changes in v2: - Change license to GPL-2.0-or-later - Add memory node for dts - Add ft_board_setup function for kernel memory init - Use default prompt Kongyang Liu (2): riscv: spacemit: bananapi_f3: initial support added doc: spacemit: bananapi_f3: document Banana Pi F3 board arch/riscv/Kconfig | 5 + arch/riscv/cpu/k1/Kconfig | 18 ++ arch/riscv/cpu/k1/Makefile | 6 + arch/riscv/cpu/k1/cpu.c | 9 + arch/riscv/cpu/k1/dram.c | 54 ++++ arch/riscv/dts/Makefile | 1 + arch/riscv/dts/k1-bananapi-f3.dts | 25 ++ arch/riscv/dts/k1.dtsi | 375 +++++++++++++++++++++++++ board/spacemit/bananapi_f3/Kconfig | 25 ++ board/spacemit/bananapi_f3/MAINTAINERS | 6 + board/spacemit/bananapi_f3/Makefile | 5 + board/spacemit/bananapi_f3/board.c | 9 + configs/bananapi_f3_defconfig | 20 ++ doc/board/index.rst | 1 + doc/board/spacemit/bananapi_f3.rst | 78 +++++ doc/board/spacemit/index.rst | 8 + include/configs/bananapi_f3.h | 15 + 17 files changed, 660 insertions(+) create mode 100644 arch/riscv/cpu/k1/Kconfig create mode 100644 arch/riscv/cpu/k1/Makefile create mode 100644 arch/riscv/cpu/k1/cpu.c create mode 100644 arch/riscv/cpu/k1/dram.c create mode 100644 arch/riscv/dts/k1-bananapi-f3.dts create mode 100644 arch/riscv/dts/k1.dtsi create mode 100644 board/spacemit/bananapi_f3/Kconfig create mode 100644 board/spacemit/bananapi_f3/MAINTAINERS create mode 100644 board/spacemit/bananapi_f3/Makefile create mode 100644 board/spacemit/bananapi_f3/board.c create mode 100644 configs/bananapi_f3_defconfig create mode 100644 doc/board/spacemit/bananapi_f3.rst create mode 100644 doc/board/spacemit/index.rst create mode 100644 include/configs/bananapi_f3.h -- 2.41.0

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[PATCH 1/2] mtd: spi-nor-core: allow overriding 4-byte OPCODE support
by Robert Marko 12 Sep '24

12 Sep '24

Currently, the only way to indicate 4-byte OPCODE support is by setting the SPI_NOR_4B_OPCODES feature flag for each JEDEC ID in spi_nor_ids[]. However, its becoming increasingly common practice for vendors to reuse the same JEDEC ID for new revisions of current parts. For example Winbond W25Q256FV does not fully support 4-byte OPCODE-s while newer W25Q256JV revision does fully support them but they share the same JEDEC ID thus currently its not possible to advertise support for 4-byte OPCODE-s on W25Q256JV. Luckily for us, there usually is a way to differentiate between parts with the same JEDEC ID by differences in SFDP tables, so in order to be able to apply a fixup after they are parsed lets add a feature flag that we can override. Signed-off-by: Robert Marko <robert.marko(a)sartura.hr> --- drivers/mtd/spi/spi-nor-core.c | 6 ++++-- include/linux/mtd/spi-nor.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index f86003ca8c..7615ba602f 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3879,7 +3879,7 @@ static int spi_nor_init(struct spi_nor *nor) if (nor->addr_width == 4 && !(nor->info->flags & SPI_NOR_OCTAL_DTR_READ) && (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) && - !(nor->info->flags & SPI_NOR_4B_OPCODES)) { + !(nor->flags & SNOR_F_4B_OPCODES)) { /* * If the RESET# pin isn't hooked up properly, or the system * otherwise doesn't perform a reset command in the boot @@ -4118,6 +4118,8 @@ int spi_nor_scan(struct spi_nor *nor) nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; if (info->flags & USE_CLSR) nor->flags |= SNOR_F_USE_CLSR; + if (info->flags & SPI_NOR_4B_OPCODES) + nor->flags |= SNOR_F_4B_OPCODES; if (info->flags & SPI_NOR_NO_ERASE) mtd->flags |= MTD_NO_ERASE; @@ -4156,7 +4158,7 @@ int spi_nor_scan(struct spi_nor *nor) /* enable 4-byte addressing if the device exceeds 16MiB */ nor->addr_width = 4; if (JEDEC_MFR(info) == SNOR_MFR_SPANSION || - info->flags & SPI_NOR_4B_OPCODES) + nor->flags & SNOR_F_4B_OPCODES) spi_nor_set_4byte_opcodes(nor, info); #else /* Configure the BAR - discover bank cmds and read current bank */ diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index d1dbf3eadb..80e56cf308 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -294,6 +294,7 @@ enum spi_nor_option_flags { SNOR_F_BROKEN_RESET = BIT(6), SNOR_F_SOFT_RESET = BIT(7), SNOR_F_IO_MODE_EN_VOLATILE = BIT(8), + SNOR_F_4B_OPCODES = BIT(9), }; struct spi_nor; -- 2.44.0

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