July 2024 - U-Boot

Orphaning my patches
by John Watts 15 Jul '24

15 Jul '24

1 0

[PATCH] arm: sunxi: add support for I2C1 on V3s-based SoCs
by Tobias Schramm 15 Jul '24

15 Jul '24

Previously enabling I2C1 when using a V3s-based SoC had no effect. Set pinmux on PE21 and PE22 to I2C1 function when enabling I2C1 on V3s-based SoCs. Signed-off-by: Tobias Schramm <t.schramm(a)manjaro.org> --- board/sunxi/board.c | 4 ++++ include/sunxi_gpio.h | 1 + 2 files changed, 5 insertions(+) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 1313b01dce..df2faba3e5 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -98,6 +98,10 @@ void i2c_init_board(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN8I_V3S) + sunxi_gpio_set_cfgpin(SUNXI_GPE(21), SUN8I_V3S_GPE_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPE(22), SUN8I_V3S_GPE_TWI1); + clock_twi_onoff(1, 1); #elif defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h index db3742c039..175b13a887 100644 --- a/include/sunxi_gpio.h +++ b/include/sunxi_gpio.h @@ -113,6 +113,7 @@ enum sunxi_gpio_number { #define SUN4I_GPB_TWI1 2 #define SUN5I_GPB_TWI1 2 #define SUN8I_V3S_GPB_TWI0 2 +#define SUN8I_V3S_GPE_TWI1 3 #define SUN4I_GPB_UART0 2 #define SUN5I_GPB_UART0 2 #define SUN8I_GPB_UART2 2 -- 2.30.2

2 1

[PATCH v2 0/2] sunxi, usb: UDC/DM gadget model support
by Sam Edwards 15 Jul '24

15 Jul '24

Happy Thursday, U-Boot list! Here is attempt 2 at making this USB controller driver compatible with DM's gadget model, following what most of the other musb variants do. v2 removes the unwanted printfs in the probe func, per feedback from Marek. I received no other feedback against v1 of this patch. Cheers, Sam Sam Edwards (2): usb: musb-new: sunxi: remove unwanted printfs usb: musb-new: sunxi: make compatible with UDC/DM gadget model drivers/usb/musb-new/sunxi.c | 52 +++++++++++++++++++++--------------- 1 file changed, 31 insertions(+), 21 deletions(-) -- 2.39.2

3 9

[PATCH 0/2] riscv: spacemit: bananapi_f3: add support for Banana Pi F3 board
by Kongyang Liu 14 Jul '24

14 Jul '24

Banana Pi F3 board is a industrial grade RISC-V development board, it design with SpacemiT K1 8 core RISC-V chip, CPU integrates 2.0 TOPs AI computing power. 4G DDR and 16G eMMC onboard.2x GbE Ethernet prot, 4x USB 3.0 and PCIe for M.2 interface, support HDMI and Dual MIPI-CSI Camera. This patch introduces fundamental support for the Banana Pi F3 board, encompassing UART, CPU, and PLIC support. This ensures that U-Boot can operate in serial console mode. Kongyang Liu (2): riscv: spacemit: bananapi_f3: initial support added doc: spacemit: bananapi_f3: document Banana Pi F3 board arch/riscv/Kconfig | 5 + arch/riscv/cpu/k1/Kconfig | 18 ++ arch/riscv/cpu/k1/Makefile | 6 + arch/riscv/cpu/k1/cpu.c | 9 + arch/riscv/cpu/k1/dram.c | 39 +++ arch/riscv/dts/Makefile | 1 + arch/riscv/dts/k1-bananapi-f3.dts | 20 ++ arch/riscv/dts/k1.dtsi | 375 +++++++++++++++++++++++++ board/spacemit/bananapi_f3/Kconfig | 25 ++ board/spacemit/bananapi_f3/MAINTAINERS | 6 + board/spacemit/bananapi_f3/Makefile | 5 + board/spacemit/bananapi_f3/board.c | 9 + configs/bananapi_f3_defconfig | 20 ++ doc/board/index.rst | 1 + doc/board/spacemit/bananapi_f3.rst | 78 +++++ doc/board/spacemit/index.rst | 8 + include/configs/bananapi_f3.h | 15 + 17 files changed, 640 insertions(+) create mode 100644 arch/riscv/cpu/k1/Kconfig create mode 100644 arch/riscv/cpu/k1/Makefile create mode 100644 arch/riscv/cpu/k1/cpu.c create mode 100644 arch/riscv/cpu/k1/dram.c create mode 100644 arch/riscv/dts/k1-bananapi-f3.dts create mode 100644 arch/riscv/dts/k1.dtsi create mode 100644 board/spacemit/bananapi_f3/Kconfig create mode 100644 board/spacemit/bananapi_f3/MAINTAINERS create mode 100644 board/spacemit/bananapi_f3/Makefile create mode 100644 board/spacemit/bananapi_f3/board.c create mode 100644 configs/bananapi_f3_defconfig create mode 100644 doc/board/spacemit/bananapi_f3.rst create mode 100644 doc/board/spacemit/index.rst create mode 100644 include/configs/bananapi_f3.h -- 2.41.0

2 6

[RFC] usb: xhci: Some USB devices fail to initialize
by Elena Popa 14 Jul '24

14 Jul '24

Hello, We've noticed that, at least, on the i.MX8M* platforms, some USB devices (especially USB2.0 sticks) fail to initialize with one of the following errors: - scanning bus usb@38200000 for devices... Device not responding to set address. USB device not accepting new address (error=80000000) - scanning bus usb@38200000 for devices... WARN halted endpoint, queueing URB anyway. Unexpected XHCI event TRB, skipping... (fcf1a5f0 00000000 13000000 01008401) BUG at drivers/usb/host/xhci-ring.c:530/abort_td()! BUG! resetting ... It seems to be a timing problem, since if we enable the debug messages, the USB device initializes correctly. We found out that if we add a small delay of 5 milliseconds at the beginning of the _xhci_submit_control_msg() function from the drivers/usb/host/xhci.c file, all devices initialize properly. Essentially, each control message is delayed by 5ms. We tried a smaller delay (1ms), but it is not enough. static int _xhci_submit_control_msg(struct usb_device *udev, unsigned long pipe, void *buffer, int length, struct devrequest *setup, int root_portnr) { + mdelay(5); struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); int ret = 0; ... } We went a little further, and this delay seems to only be necessary for the requests of type: - USB_REQ_GET_STATUS (for the communication with the root) - USB_REQ_GET_DESCRIPTOR ( for the communication with the device) I don't have too much know-how about the USB, so I would appreciate your opinion related to this issue, and how can we find the root cause. I found several reports on the internet with the same problem on other boards. Maybe some of the USB timing specs are not implemented correctly? U-Boot is maybe sending control messages too aggressively? If you give me some suggestions of where to look, I could do some debugging myself. Of course, since printing debug messages makes the initialization work, complicates the debugging. Thank you, Elena

2 6

[PATCH] part: efi: Rely on a definition to specify the primary GPT position
by Roman Stratiienko 14 Jul '24

14 Jul '24

Use GPT_PRIMARY_PARTITION_TABLE_LBA as the only source for a primary GPT location instead of hardcoding it every time. Sometimes, we need to shift the primary GPT location. Having the location in the single place simplifies such shifting. Signed-off-by: Roman Stratiienko <r.stratiienko(a)gmail.com> --- disk/part_efi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/disk/part_efi.c b/disk/part_efi.c index 4ce9243ef2..b55e251ea1 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -387,7 +387,7 @@ int write_gpt_table(struct blk_desc *desc, gpt_header *gpt_h, gpt_entry *gpt_e) gpt_h->header_crc32 = cpu_to_le32(calc_crc32); /* Write the First GPT to the block right after the Legacy MBR */ - if (blk_dwrite(desc, 1, 1, gpt_h) != 1) + if (blk_dwrite(desc, (lbaint_t)le64_to_cpu(gpt_h->my_lba), 1, gpt_h) != 1) goto err; if (blk_dwrite(desc, le64_to_cpu(gpt_h->partition_entry_lba), @@ -534,7 +534,7 @@ int gpt_fill_pte(struct blk_desc *desc, static uint32_t partition_entries_offset(struct blk_desc *desc) { - uint32_t offset_blks = 2; + uint32_t offset_blks = GPT_PRIMARY_PARTITION_TABLE_LBA + 1; uint32_t __maybe_unused offset_bytes; int __maybe_unused config_offset; @@ -572,8 +572,8 @@ static uint32_t partition_entries_offset(struct blk_desc *desc) * The earliest LBA this can be at is LBA#2 (i.e. right behind * the (protective) MBR and the GPT header. */ - if (offset_blks < 2) - offset_blks = 2; + if (offset_blks < (GPT_PRIMARY_PARTITION_TABLE_LBA + 1)) + offset_blks = GPT_PRIMARY_PARTITION_TABLE_LBA + 1; return offset_blks; } @@ -584,7 +584,7 @@ int gpt_fill_header(struct blk_desc *desc, gpt_header *gpt_h, char *str_guid, gpt_h->signature = cpu_to_le64(GPT_HEADER_SIGNATURE_UBOOT); gpt_h->revision = cpu_to_le32(GPT_HEADER_REVISION_V1); gpt_h->header_size = cpu_to_le32(sizeof(gpt_header)); - gpt_h->my_lba = cpu_to_le64(1); + gpt_h->my_lba = cpu_to_le64(GPT_PRIMARY_PARTITION_TABLE_LBA); gpt_h->alternate_lba = cpu_to_le64(desc->lba - 1); gpt_h->last_usable_lba = cpu_to_le64(desc->lba - 34); gpt_h->partition_entry_lba = -- 2.40.1

2 4

[PATCH] clk: imx8mn: add video clocks support
by Michael Trimarchi 14 Jul '24

14 Jul '24

Add clocks support for the video subsystem. Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> --- drivers/clk/imx/clk-imx8mn.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 457acb8a40..baac79dd29 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -23,6 +23,7 @@ static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", }; static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; +static const char *video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", }; static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; @@ -30,6 +31,10 @@ static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", }; +static const char *imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll_out", "audio_pll2_out", + "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", + "sys_pll3_out", "clk_ext4", }; + static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", }; @@ -139,6 +144,9 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_SYS_PLL3_REF_SEL, imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + clk_dm(IMX8MN_VIDEO_PLL1_REF_SEL, + imx_clk_mux("video_pll_ref_sel", base + 0x28, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MN_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", @@ -155,6 +163,9 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll)); + clk_dm(IMX8MN_VIDEO_PLL1, + imx_clk_pll14xx("video_pll", "video_pll_ref_sel", + base + 0x28, &imx_1443x_pll)); /* PLL bypass out */ clk_dm(IMX8MN_DRAM_PLL_BYPASS, @@ -183,6 +194,12 @@ static int imx8mn_clk_probe(struct udevice *dev) ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT)); + clk_dm(IMX8MN_VIDEO_PLL1_BYPASS, + imx_clk_mux_flags("video_pll_bypass", base + 0x28, 16, 1, + video_pll_bypass_sels, + ARRAY_SIZE(video_pll_bypass_sels), + CLK_SET_RATE_PARENT)); + /* PLL out gate */ clk_dm(IMX8MN_DRAM_PLL_OUT, imx_clk_gate("dram_pll_out", "dram_pll_bypass", @@ -199,6 +216,9 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_SYS_PLL3_OUT, imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11)); + clk_dm(IMX8MN_VIDEO_PLL1_OUT, + imx_clk_gate("video_pll_out", "video_pll_bypass", + base + 0x28, 13)); /* SYS PLL fixed output */ clk_dm(IMX8MN_SYS_PLL1_40M, @@ -275,6 +295,9 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_CLK_USDHC2, imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels, base + 0xac80)); + + clk_dm(IMX8MN_CLK_DISP_PIXEL, + imx8m_clk_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500)); clk_dm(IMX8MN_CLK_I2C1, imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00)); clk_dm(IMX8MN_CLK_I2C2, -- 2.40.1

3 5

[PATCH uboot] dt-bindings: clock: rcar-gen2: Remove obsolete header files
by Geert Uytterhoeven 13 Jul '24

13 Jul '24

The clock definitions in <dt-bindings/clock/r8a779?-clock.h> were superseded by those in <dt-bindings/clock/r8a779?-cpg-mssr.h> a long time ago. In fact U-Boot never used <dt-bindings/clock/r8a779?-clock.h>. The unused headers, their replacements, and the corresponding r8a779?.dtsi files were introduced together in U-Boot v2018.03. Fixes: 16b6e4aa3732cee1 ("ARM: dts: rmobile: Import R8A7790 DTS from Linux 4.15-rc8") Fixes: edd15fcffba31452 ("ARM: dts: rmobile: Import R8A7791 DTS from Linux 4.15-rc8") Fixes: a3fb9ff3b33fae05 ("ARM: dts: rmobile: Import R8A7792 DTS from Linux 4.15-rc8") Fixes: 92aa09959271d08f ("ARM: dts: rmobile: Import R8A7793 DTS from Linux 4.15-rc8") Fixes: 9a26fc5a73fe2369 ("ARM: dts: rmobile: Import R8A7794 DTS from Linux 4.15-rc8") Signed-off-by: Geert Uytterhoeven <geert+renesas(a)glider.be> --- Cfr. https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git/commit/?h=clk… I assume the corresponding header files under dts/upstream/include/dt-bindings/clock/ will be removed automatically in a future "Subtree merge tag 'v6.11-dts' of devicetree-rebasing repo [1] into dts/upstream" commit? --- include/dt-bindings/clock/r8a7790-clock.h | 158 --------------------- include/dt-bindings/clock/r8a7791-clock.h | 161 ---------------------- include/dt-bindings/clock/r8a7792-clock.h | 98 ------------- include/dt-bindings/clock/r8a7793-clock.h | 159 --------------------- include/dt-bindings/clock/r8a7794-clock.h | 137 ------------------ 5 files changed, 713 deletions(-) delete mode 100644 include/dt-bindings/clock/r8a7790-clock.h delete mode 100644 include/dt-bindings/clock/r8a7791-clock.h delete mode 100644 include/dt-bindings/clock/r8a7792-clock.h delete mode 100644 include/dt-bindings/clock/r8a7793-clock.h delete mode 100644 include/dt-bindings/clock/r8a7794-clock.h diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h deleted file mode 100644 index c92ff1e6022369e5..0000000000000000 --- a/include/dt-bindings/clock/r8a7790-clock.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2013 Ideas On Board SPRL - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__ -#define __DT_BINDINGS_CLOCK_R8A7790_H__ - -/* CPG */ -#define R8A7790_CLK_MAIN 0 -#define R8A7790_CLK_PLL0 1 -#define R8A7790_CLK_PLL1 2 -#define R8A7790_CLK_PLL3 3 -#define R8A7790_CLK_LB 4 -#define R8A7790_CLK_QSPI 5 -#define R8A7790_CLK_SDH 6 -#define R8A7790_CLK_SD0 7 -#define R8A7790_CLK_SD1 8 -#define R8A7790_CLK_Z 9 -#define R8A7790_CLK_RCAN 10 -#define R8A7790_CLK_ADSP 11 - -/* MSTP0 */ -#define R8A7790_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7790_CLK_VCP1 0 -#define R8A7790_CLK_VCP0 1 -#define R8A7790_CLK_VPC1 2 -#define R8A7790_CLK_VPC0 3 -#define R8A7790_CLK_JPU 6 -#define R8A7790_CLK_SSP1 9 -#define R8A7790_CLK_TMU1 11 -#define R8A7790_CLK_3DG 12 -#define R8A7790_CLK_2DDMAC 15 -#define R8A7790_CLK_FDP1_2 17 -#define R8A7790_CLK_FDP1_1 18 -#define R8A7790_CLK_FDP1_0 19 -#define R8A7790_CLK_TMU3 21 -#define R8A7790_CLK_TMU2 22 -#define R8A7790_CLK_CMT0 24 -#define R8A7790_CLK_TMU0 25 -#define R8A7790_CLK_VSP1_DU1 27 -#define R8A7790_CLK_VSP1_DU0 28 -#define R8A7790_CLK_VSP1_R 30 -#define R8A7790_CLK_VSP1_S 31 - -/* MSTP2 */ -#define R8A7790_CLK_SCIFA2 2 -#define R8A7790_CLK_SCIFA1 3 -#define R8A7790_CLK_SCIFA0 4 -#define R8A7790_CLK_MSIOF2 5 -#define R8A7790_CLK_SCIFB0 6 -#define R8A7790_CLK_SCIFB1 7 -#define R8A7790_CLK_MSIOF1 8 -#define R8A7790_CLK_MSIOF3 15 -#define R8A7790_CLK_SCIFB2 16 -#define R8A7790_CLK_SYS_DMAC1 18 -#define R8A7790_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7790_CLK_IIC2 0 -#define R8A7790_CLK_TPU0 4 -#define R8A7790_CLK_MMCIF1 5 -#define R8A7790_CLK_SCIF2 10 -#define R8A7790_CLK_SDHI3 11 -#define R8A7790_CLK_SDHI2 12 -#define R8A7790_CLK_SDHI1 13 -#define R8A7790_CLK_SDHI0 14 -#define R8A7790_CLK_MMCIF0 15 -#define R8A7790_CLK_IIC0 18 -#define R8A7790_CLK_PCIEC 19 -#define R8A7790_CLK_IIC1 23 -#define R8A7790_CLK_SSUSB 28 -#define R8A7790_CLK_CMT1 29 -#define R8A7790_CLK_USBDMAC0 30 -#define R8A7790_CLK_USBDMAC1 31 - -/* MSTP4 */ -#define R8A7790_CLK_IRQC 7 -#define R8A7790_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7790_CLK_AUDIO_DMAC1 1 -#define R8A7790_CLK_AUDIO_DMAC0 2 -#define R8A7790_CLK_ADSP_MOD 6 -#define R8A7790_CLK_THERMAL 22 -#define R8A7790_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7790_CLK_EHCI 3 -#define R8A7790_CLK_HSUSB 4 -#define R8A7790_CLK_HSCIF1 16 -#define R8A7790_CLK_HSCIF0 17 -#define R8A7790_CLK_SCIF1 20 -#define R8A7790_CLK_SCIF0 21 -#define R8A7790_CLK_DU2 22 -#define R8A7790_CLK_DU1 23 -#define R8A7790_CLK_DU0 24 -#define R8A7790_CLK_LVDS1 25 -#define R8A7790_CLK_LVDS0 26 - -/* MSTP8 */ -#define R8A7790_CLK_MLB 2 -#define R8A7790_CLK_VIN3 8 -#define R8A7790_CLK_VIN2 9 -#define R8A7790_CLK_VIN1 10 -#define R8A7790_CLK_VIN0 11 -#define R8A7790_CLK_ETHERAVB 12 -#define R8A7790_CLK_ETHER 13 -#define R8A7790_CLK_SATA1 14 -#define R8A7790_CLK_SATA0 15 - -/* MSTP9 */ -#define R8A7790_CLK_GPIO5 7 -#define R8A7790_CLK_GPIO4 8 -#define R8A7790_CLK_GPIO3 9 -#define R8A7790_CLK_GPIO2 10 -#define R8A7790_CLK_GPIO1 11 -#define R8A7790_CLK_GPIO0 12 -#define R8A7790_CLK_RCAN1 15 -#define R8A7790_CLK_RCAN0 16 -#define R8A7790_CLK_QSPI_MOD 17 -#define R8A7790_CLK_IICDVFS 26 -#define R8A7790_CLK_I2C3 28 -#define R8A7790_CLK_I2C2 29 -#define R8A7790_CLK_I2C1 30 -#define R8A7790_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7790_CLK_SSI_ALL 5 -#define R8A7790_CLK_SSI9 6 -#define R8A7790_CLK_SSI8 7 -#define R8A7790_CLK_SSI7 8 -#define R8A7790_CLK_SSI6 9 -#define R8A7790_CLK_SSI5 10 -#define R8A7790_CLK_SSI4 11 -#define R8A7790_CLK_SSI3 12 -#define R8A7790_CLK_SSI2 13 -#define R8A7790_CLK_SSI1 14 -#define R8A7790_CLK_SSI0 15 -#define R8A7790_CLK_SCU_ALL 17 -#define R8A7790_CLK_SCU_DVC1 18 -#define R8A7790_CLK_SCU_DVC0 19 -#define R8A7790_CLK_SCU_CTU1_MIX1 20 -#define R8A7790_CLK_SCU_CTU0_MIX0 21 -#define R8A7790_CLK_SCU_SRC9 22 -#define R8A7790_CLK_SCU_SRC8 23 -#define R8A7790_CLK_SCU_SRC7 24 -#define R8A7790_CLK_SCU_SRC6 25 -#define R8A7790_CLK_SCU_SRC5 26 -#define R8A7790_CLK_SCU_SRC4 27 -#define R8A7790_CLK_SCU_SRC3 28 -#define R8A7790_CLK_SCU_SRC2 29 -#define R8A7790_CLK_SCU_SRC1 30 -#define R8A7790_CLK_SCU_SRC0 31 - -#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */ diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h deleted file mode 100644 index bb4f18b1b3d585cd..0000000000000000 --- a/include/dt-bindings/clock/r8a7791-clock.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2013 Ideas On Board SPRL - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__ -#define __DT_BINDINGS_CLOCK_R8A7791_H__ - -/* CPG */ -#define R8A7791_CLK_MAIN 0 -#define R8A7791_CLK_PLL0 1 -#define R8A7791_CLK_PLL1 2 -#define R8A7791_CLK_PLL3 3 -#define R8A7791_CLK_LB 4 -#define R8A7791_CLK_QSPI 5 -#define R8A7791_CLK_SDH 6 -#define R8A7791_CLK_SD0 7 -#define R8A7791_CLK_Z 8 -#define R8A7791_CLK_RCAN 9 -#define R8A7791_CLK_ADSP 10 - -/* MSTP0 */ -#define R8A7791_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7791_CLK_VCP0 1 -#define R8A7791_CLK_VPC0 3 -#define R8A7791_CLK_JPU 6 -#define R8A7791_CLK_SSP1 9 -#define R8A7791_CLK_TMU1 11 -#define R8A7791_CLK_3DG 12 -#define R8A7791_CLK_2DDMAC 15 -#define R8A7791_CLK_FDP1_1 18 -#define R8A7791_CLK_FDP1_0 19 -#define R8A7791_CLK_TMU3 21 -#define R8A7791_CLK_TMU2 22 -#define R8A7791_CLK_CMT0 24 -#define R8A7791_CLK_TMU0 25 -#define R8A7791_CLK_VSP1_DU1 27 -#define R8A7791_CLK_VSP1_DU0 28 -#define R8A7791_CLK_VSP1_S 31 - -/* MSTP2 */ -#define R8A7791_CLK_SCIFA2 2 -#define R8A7791_CLK_SCIFA1 3 -#define R8A7791_CLK_SCIFA0 4 -#define R8A7791_CLK_MSIOF2 5 -#define R8A7791_CLK_SCIFB0 6 -#define R8A7791_CLK_SCIFB1 7 -#define R8A7791_CLK_MSIOF1 8 -#define R8A7791_CLK_SCIFB2 16 -#define R8A7791_CLK_SYS_DMAC1 18 -#define R8A7791_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7791_CLK_TPU0 4 -#define R8A7791_CLK_SDHI2 11 -#define R8A7791_CLK_SDHI1 12 -#define R8A7791_CLK_SDHI0 14 -#define R8A7791_CLK_MMCIF0 15 -#define R8A7791_CLK_IIC0 18 -#define R8A7791_CLK_PCIEC 19 -#define R8A7791_CLK_IIC1 23 -#define R8A7791_CLK_SSUSB 28 -#define R8A7791_CLK_CMT1 29 -#define R8A7791_CLK_USBDMAC0 30 -#define R8A7791_CLK_USBDMAC1 31 - -/* MSTP4 */ -#define R8A7791_CLK_IRQC 7 -#define R8A7791_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7791_CLK_AUDIO_DMAC1 1 -#define R8A7791_CLK_AUDIO_DMAC0 2 -#define R8A7791_CLK_ADSP_MOD 6 -#define R8A7791_CLK_THERMAL 22 -#define R8A7791_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7791_CLK_EHCI 3 -#define R8A7791_CLK_HSUSB 4 -#define R8A7791_CLK_HSCIF2 13 -#define R8A7791_CLK_SCIF5 14 -#define R8A7791_CLK_SCIF4 15 -#define R8A7791_CLK_HSCIF1 16 -#define R8A7791_CLK_HSCIF0 17 -#define R8A7791_CLK_SCIF3 18 -#define R8A7791_CLK_SCIF2 19 -#define R8A7791_CLK_SCIF1 20 -#define R8A7791_CLK_SCIF0 21 -#define R8A7791_CLK_DU1 23 -#define R8A7791_CLK_DU0 24 -#define R8A7791_CLK_LVDS0 26 - -/* MSTP8 */ -#define R8A7791_CLK_IPMMU_SGX 0 -#define R8A7791_CLK_MLB 2 -#define R8A7791_CLK_VIN2 9 -#define R8A7791_CLK_VIN1 10 -#define R8A7791_CLK_VIN0 11 -#define R8A7791_CLK_ETHERAVB 12 -#define R8A7791_CLK_ETHER 13 -#define R8A7791_CLK_SATA1 14 -#define R8A7791_CLK_SATA0 15 - -/* MSTP9 */ -#define R8A7791_CLK_GYROADC 1 -#define R8A7791_CLK_GPIO7 4 -#define R8A7791_CLK_GPIO6 5 -#define R8A7791_CLK_GPIO5 7 -#define R8A7791_CLK_GPIO4 8 -#define R8A7791_CLK_GPIO3 9 -#define R8A7791_CLK_GPIO2 10 -#define R8A7791_CLK_GPIO1 11 -#define R8A7791_CLK_GPIO0 12 -#define R8A7791_CLK_RCAN1 15 -#define R8A7791_CLK_RCAN0 16 -#define R8A7791_CLK_QSPI_MOD 17 -#define R8A7791_CLK_I2C5 25 -#define R8A7791_CLK_IICDVFS 26 -#define R8A7791_CLK_I2C4 27 -#define R8A7791_CLK_I2C3 28 -#define R8A7791_CLK_I2C2 29 -#define R8A7791_CLK_I2C1 30 -#define R8A7791_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7791_CLK_SSI_ALL 5 -#define R8A7791_CLK_SSI9 6 -#define R8A7791_CLK_SSI8 7 -#define R8A7791_CLK_SSI7 8 -#define R8A7791_CLK_SSI6 9 -#define R8A7791_CLK_SSI5 10 -#define R8A7791_CLK_SSI4 11 -#define R8A7791_CLK_SSI3 12 -#define R8A7791_CLK_SSI2 13 -#define R8A7791_CLK_SSI1 14 -#define R8A7791_CLK_SSI0 15 -#define R8A7791_CLK_SCU_ALL 17 -#define R8A7791_CLK_SCU_DVC1 18 -#define R8A7791_CLK_SCU_DVC0 19 -#define R8A7791_CLK_SCU_CTU1_MIX1 20 -#define R8A7791_CLK_SCU_CTU0_MIX0 21 -#define R8A7791_CLK_SCU_SRC9 22 -#define R8A7791_CLK_SCU_SRC8 23 -#define R8A7791_CLK_SCU_SRC7 24 -#define R8A7791_CLK_SCU_SRC6 25 -#define R8A7791_CLK_SCU_SRC5 26 -#define R8A7791_CLK_SCU_SRC4 27 -#define R8A7791_CLK_SCU_SRC3 28 -#define R8A7791_CLK_SCU_SRC2 29 -#define R8A7791_CLK_SCU_SRC1 30 -#define R8A7791_CLK_SCU_SRC0 31 - -/* MSTP11 */ -#define R8A7791_CLK_SCIFA3 6 -#define R8A7791_CLK_SCIFA4 7 -#define R8A7791_CLK_SCIFA5 8 - -#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */ diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h deleted file mode 100644 index 2948d9ce3a14bb1e..0000000000000000 --- a/include/dt-bindings/clock/r8a7792-clock.h +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__ -#define __DT_BINDINGS_CLOCK_R8A7792_H__ - -/* CPG */ -#define R8A7792_CLK_MAIN 0 -#define R8A7792_CLK_PLL0 1 -#define R8A7792_CLK_PLL1 2 -#define R8A7792_CLK_PLL3 3 -#define R8A7792_CLK_LB 4 -#define R8A7792_CLK_QSPI 5 - -/* MSTP0 */ -#define R8A7792_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7792_CLK_JPU 6 -#define R8A7792_CLK_TMU1 11 -#define R8A7792_CLK_TMU3 21 -#define R8A7792_CLK_TMU2 22 -#define R8A7792_CLK_CMT0 24 -#define R8A7792_CLK_TMU0 25 -#define R8A7792_CLK_VSP1DU1 27 -#define R8A7792_CLK_VSP1DU0 28 -#define R8A7792_CLK_VSP1_SY 31 - -/* MSTP2 */ -#define R8A7792_CLK_MSIOF1 8 -#define R8A7792_CLK_SYS_DMAC1 18 -#define R8A7792_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7792_CLK_TPU0 4 -#define R8A7792_CLK_SDHI0 14 -#define R8A7792_CLK_CMT1 29 - -/* MSTP4 */ -#define R8A7792_CLK_IRQC 7 -#define R8A7792_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7792_CLK_AUDIO_DMAC0 2 -#define R8A7792_CLK_THERMAL 22 -#define R8A7792_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7792_CLK_HSCIF1 16 -#define R8A7792_CLK_HSCIF0 17 -#define R8A7792_CLK_SCIF3 18 -#define R8A7792_CLK_SCIF2 19 -#define R8A7792_CLK_SCIF1 20 -#define R8A7792_CLK_SCIF0 21 -#define R8A7792_CLK_DU1 23 -#define R8A7792_CLK_DU0 24 - -/* MSTP8 */ -#define R8A7792_CLK_VIN5 4 -#define R8A7792_CLK_VIN4 5 -#define R8A7792_CLK_VIN3 8 -#define R8A7792_CLK_VIN2 9 -#define R8A7792_CLK_VIN1 10 -#define R8A7792_CLK_VIN0 11 -#define R8A7792_CLK_ETHERAVB 12 - -/* MSTP9 */ -#define R8A7792_CLK_GPIO7 4 -#define R8A7792_CLK_GPIO6 5 -#define R8A7792_CLK_GPIO5 7 -#define R8A7792_CLK_GPIO4 8 -#define R8A7792_CLK_GPIO3 9 -#define R8A7792_CLK_GPIO2 10 -#define R8A7792_CLK_GPIO1 11 -#define R8A7792_CLK_GPIO0 12 -#define R8A7792_CLK_GPIO11 13 -#define R8A7792_CLK_GPIO10 14 -#define R8A7792_CLK_CAN1 15 -#define R8A7792_CLK_CAN0 16 -#define R8A7792_CLK_QSPI_MOD 17 -#define R8A7792_CLK_GPIO9 19 -#define R8A7792_CLK_GPIO8 21 -#define R8A7792_CLK_I2C5 25 -#define R8A7792_CLK_IICDVFS 26 -#define R8A7792_CLK_I2C4 27 -#define R8A7792_CLK_I2C3 28 -#define R8A7792_CLK_I2C2 29 -#define R8A7792_CLK_I2C1 30 -#define R8A7792_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7792_CLK_SSI_ALL 5 -#define R8A7792_CLK_SSI4 11 -#define R8A7792_CLK_SSI3 12 - -#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */ diff --git a/include/dt-bindings/clock/r8a7793-clock.h b/include/dt-bindings/clock/r8a7793-clock.h deleted file mode 100644 index 49c66d8ed1782fc0..0000000000000000 --- a/include/dt-bindings/clock/r8a7793-clock.h +++ /dev/null @@ -1,159 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * r8a7793 clock definition - * - * Copyright (C) 2014 Renesas Electronics Corporation - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__ -#define __DT_BINDINGS_CLOCK_R8A7793_H__ - -/* CPG */ -#define R8A7793_CLK_MAIN 0 -#define R8A7793_CLK_PLL0 1 -#define R8A7793_CLK_PLL1 2 -#define R8A7793_CLK_PLL3 3 -#define R8A7793_CLK_LB 4 -#define R8A7793_CLK_QSPI 5 -#define R8A7793_CLK_SDH 6 -#define R8A7793_CLK_SD0 7 -#define R8A7793_CLK_Z 8 -#define R8A7793_CLK_RCAN 9 -#define R8A7793_CLK_ADSP 10 - -/* MSTP0 */ -#define R8A7793_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7793_CLK_VCP0 1 -#define R8A7793_CLK_VPC0 3 -#define R8A7793_CLK_SSP1 9 -#define R8A7793_CLK_TMU1 11 -#define R8A7793_CLK_3DG 12 -#define R8A7793_CLK_2DDMAC 15 -#define R8A7793_CLK_FDP1_1 18 -#define R8A7793_CLK_FDP1_0 19 -#define R8A7793_CLK_TMU3 21 -#define R8A7793_CLK_TMU2 22 -#define R8A7793_CLK_CMT0 24 -#define R8A7793_CLK_TMU0 25 -#define R8A7793_CLK_VSP1_DU1 27 -#define R8A7793_CLK_VSP1_DU0 28 -#define R8A7793_CLK_VSP1_S 31 - -/* MSTP2 */ -#define R8A7793_CLK_SCIFA2 2 -#define R8A7793_CLK_SCIFA1 3 -#define R8A7793_CLK_SCIFA0 4 -#define R8A7793_CLK_MSIOF2 5 -#define R8A7793_CLK_SCIFB0 6 -#define R8A7793_CLK_SCIFB1 7 -#define R8A7793_CLK_MSIOF1 8 -#define R8A7793_CLK_SCIFB2 16 -#define R8A7793_CLK_SYS_DMAC1 18 -#define R8A7793_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7793_CLK_TPU0 4 -#define R8A7793_CLK_SDHI2 11 -#define R8A7793_CLK_SDHI1 12 -#define R8A7793_CLK_SDHI0 14 -#define R8A7793_CLK_MMCIF0 15 -#define R8A7793_CLK_IIC0 18 -#define R8A7793_CLK_PCIEC 19 -#define R8A7793_CLK_IIC1 23 -#define R8A7793_CLK_SSUSB 28 -#define R8A7793_CLK_CMT1 29 -#define R8A7793_CLK_USBDMAC0 30 -#define R8A7793_CLK_USBDMAC1 31 - -/* MSTP4 */ -#define R8A7793_CLK_IRQC 7 -#define R8A7793_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7793_CLK_AUDIO_DMAC1 1 -#define R8A7793_CLK_AUDIO_DMAC0 2 -#define R8A7793_CLK_ADSP_MOD 6 -#define R8A7793_CLK_THERMAL 22 -#define R8A7793_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7793_CLK_EHCI 3 -#define R8A7793_CLK_HSUSB 4 -#define R8A7793_CLK_HSCIF2 13 -#define R8A7793_CLK_SCIF5 14 -#define R8A7793_CLK_SCIF4 15 -#define R8A7793_CLK_HSCIF1 16 -#define R8A7793_CLK_HSCIF0 17 -#define R8A7793_CLK_SCIF3 18 -#define R8A7793_CLK_SCIF2 19 -#define R8A7793_CLK_SCIF1 20 -#define R8A7793_CLK_SCIF0 21 -#define R8A7793_CLK_DU1 23 -#define R8A7793_CLK_DU0 24 -#define R8A7793_CLK_LVDS0 26 - -/* MSTP8 */ -#define R8A7793_CLK_IPMMU_SGX 0 -#define R8A7793_CLK_VIN2 9 -#define R8A7793_CLK_VIN1 10 -#define R8A7793_CLK_VIN0 11 -#define R8A7793_CLK_ETHER 13 -#define R8A7793_CLK_SATA1 14 -#define R8A7793_CLK_SATA0 15 - -/* MSTP9 */ -#define R8A7793_CLK_GPIO7 4 -#define R8A7793_CLK_GPIO6 5 -#define R8A7793_CLK_GPIO5 7 -#define R8A7793_CLK_GPIO4 8 -#define R8A7793_CLK_GPIO3 9 -#define R8A7793_CLK_GPIO2 10 -#define R8A7793_CLK_GPIO1 11 -#define R8A7793_CLK_GPIO0 12 -#define R8A7793_CLK_RCAN1 15 -#define R8A7793_CLK_RCAN0 16 -#define R8A7793_CLK_QSPI_MOD 17 -#define R8A7793_CLK_I2C5 25 -#define R8A7793_CLK_IICDVFS 26 -#define R8A7793_CLK_I2C4 27 -#define R8A7793_CLK_I2C3 28 -#define R8A7793_CLK_I2C2 29 -#define R8A7793_CLK_I2C1 30 -#define R8A7793_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7793_CLK_SSI_ALL 5 -#define R8A7793_CLK_SSI9 6 -#define R8A7793_CLK_SSI8 7 -#define R8A7793_CLK_SSI7 8 -#define R8A7793_CLK_SSI6 9 -#define R8A7793_CLK_SSI5 10 -#define R8A7793_CLK_SSI4 11 -#define R8A7793_CLK_SSI3 12 -#define R8A7793_CLK_SSI2 13 -#define R8A7793_CLK_SSI1 14 -#define R8A7793_CLK_SSI0 15 -#define R8A7793_CLK_SCU_ALL 17 -#define R8A7793_CLK_SCU_DVC1 18 -#define R8A7793_CLK_SCU_DVC0 19 -#define R8A7793_CLK_SCU_CTU1_MIX1 20 -#define R8A7793_CLK_SCU_CTU0_MIX0 21 -#define R8A7793_CLK_SCU_SRC9 22 -#define R8A7793_CLK_SCU_SRC8 23 -#define R8A7793_CLK_SCU_SRC7 24 -#define R8A7793_CLK_SCU_SRC6 25 -#define R8A7793_CLK_SCU_SRC5 26 -#define R8A7793_CLK_SCU_SRC4 27 -#define R8A7793_CLK_SCU_SRC3 28 -#define R8A7793_CLK_SCU_SRC2 29 -#define R8A7793_CLK_SCU_SRC1 30 -#define R8A7793_CLK_SCU_SRC0 31 - -/* MSTP11 */ -#define R8A7793_CLK_SCIFA3 6 -#define R8A7793_CLK_SCIFA4 7 -#define R8A7793_CLK_SCIFA5 8 - -#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */ diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h deleted file mode 100644 index 649f005782d05213..0000000000000000 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ - * - * Copyright (C) 2014 Renesas Electronics Corporation - * Copyright 2013 Ideas On Board SPRL - */ - -#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__ -#define __DT_BINDINGS_CLOCK_R8A7794_H__ - -/* CPG */ -#define R8A7794_CLK_MAIN 0 -#define R8A7794_CLK_PLL0 1 -#define R8A7794_CLK_PLL1 2 -#define R8A7794_CLK_PLL3 3 -#define R8A7794_CLK_LB 4 -#define R8A7794_CLK_QSPI 5 -#define R8A7794_CLK_SDH 6 -#define R8A7794_CLK_SD0 7 -#define R8A7794_CLK_RCAN 8 - -/* MSTP0 */ -#define R8A7794_CLK_MSIOF0 0 - -/* MSTP1 */ -#define R8A7794_CLK_VCP0 1 -#define R8A7794_CLK_VPC0 3 -#define R8A7794_CLK_TMU1 11 -#define R8A7794_CLK_3DG 12 -#define R8A7794_CLK_2DDMAC 15 -#define R8A7794_CLK_FDP1_0 19 -#define R8A7794_CLK_TMU3 21 -#define R8A7794_CLK_TMU2 22 -#define R8A7794_CLK_CMT0 24 -#define R8A7794_CLK_TMU0 25 -#define R8A7794_CLK_VSP1_DU0 28 -#define R8A7794_CLK_VSP1_S 31 - -/* MSTP2 */ -#define R8A7794_CLK_SCIFA2 2 -#define R8A7794_CLK_SCIFA1 3 -#define R8A7794_CLK_SCIFA0 4 -#define R8A7794_CLK_MSIOF2 5 -#define R8A7794_CLK_SCIFB0 6 -#define R8A7794_CLK_SCIFB1 7 -#define R8A7794_CLK_MSIOF1 8 -#define R8A7794_CLK_SCIFB2 16 -#define R8A7794_CLK_SYS_DMAC1 18 -#define R8A7794_CLK_SYS_DMAC0 19 - -/* MSTP3 */ -#define R8A7794_CLK_SDHI2 11 -#define R8A7794_CLK_SDHI1 12 -#define R8A7794_CLK_SDHI0 14 -#define R8A7794_CLK_MMCIF0 15 -#define R8A7794_CLK_IIC0 18 -#define R8A7794_CLK_IIC1 23 -#define R8A7794_CLK_CMT1 29 -#define R8A7794_CLK_USBDMAC0 30 -#define R8A7794_CLK_USBDMAC1 31 - -/* MSTP4 */ -#define R8A7794_CLK_IRQC 7 -#define R8A7794_CLK_INTC_SYS 8 - -/* MSTP5 */ -#define R8A7794_CLK_AUDIO_DMAC0 2 -#define R8A7794_CLK_PWM 23 - -/* MSTP7 */ -#define R8A7794_CLK_EHCI 3 -#define R8A7794_CLK_HSUSB 4 -#define R8A7794_CLK_HSCIF2 13 -#define R8A7794_CLK_SCIF5 14 -#define R8A7794_CLK_SCIF4 15 -#define R8A7794_CLK_HSCIF1 16 -#define R8A7794_CLK_HSCIF0 17 -#define R8A7794_CLK_SCIF3 18 -#define R8A7794_CLK_SCIF2 19 -#define R8A7794_CLK_SCIF1 20 -#define R8A7794_CLK_SCIF0 21 -#define R8A7794_CLK_DU1 23 -#define R8A7794_CLK_DU0 24 - -/* MSTP8 */ -#define R8A7794_CLK_VIN1 10 -#define R8A7794_CLK_VIN0 11 -#define R8A7794_CLK_ETHERAVB 12 -#define R8A7794_CLK_ETHER 13 - -/* MSTP9 */ -#define R8A7794_CLK_GPIO6 5 -#define R8A7794_CLK_GPIO5 7 -#define R8A7794_CLK_GPIO4 8 -#define R8A7794_CLK_GPIO3 9 -#define R8A7794_CLK_GPIO2 10 -#define R8A7794_CLK_GPIO1 11 -#define R8A7794_CLK_GPIO0 12 -#define R8A7794_CLK_RCAN1 15 -#define R8A7794_CLK_RCAN0 16 -#define R8A7794_CLK_QSPI_MOD 17 -#define R8A7794_CLK_I2C5 25 -#define R8A7794_CLK_I2C4 27 -#define R8A7794_CLK_I2C3 28 -#define R8A7794_CLK_I2C2 29 -#define R8A7794_CLK_I2C1 30 -#define R8A7794_CLK_I2C0 31 - -/* MSTP10 */ -#define R8A7794_CLK_SSI_ALL 5 -#define R8A7794_CLK_SSI9 6 -#define R8A7794_CLK_SSI8 7 -#define R8A7794_CLK_SSI7 8 -#define R8A7794_CLK_SSI6 9 -#define R8A7794_CLK_SSI5 10 -#define R8A7794_CLK_SSI4 11 -#define R8A7794_CLK_SSI3 12 -#define R8A7794_CLK_SSI2 13 -#define R8A7794_CLK_SSI1 14 -#define R8A7794_CLK_SSI0 15 -#define R8A7794_CLK_SCU_ALL 17 -#define R8A7794_CLK_SCU_DVC1 18 -#define R8A7794_CLK_SCU_DVC0 19 -#define R8A7794_CLK_SCU_CTU1_MIX1 20 -#define R8A7794_CLK_SCU_CTU0_MIX0 21 -#define R8A7794_CLK_SCU_SRC6 25 -#define R8A7794_CLK_SCU_SRC5 26 -#define R8A7794_CLK_SCU_SRC4 27 -#define R8A7794_CLK_SCU_SRC3 28 -#define R8A7794_CLK_SCU_SRC2 29 -#define R8A7794_CLK_SCU_SRC1 30 - -/* MSTP11 */ -#define R8A7794_CLK_SCIFA3 6 -#define R8A7794_CLK_SCIFA4 7 -#define R8A7794_CLK_SCIFA5 8 - -#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */ -- 2.34.1

3 2

[PATCH] eth: asix88179: reset during probe
by Caleb Connolly 13 Jul '24

13 Jul '24

In some cases (consistently in my case with an embedded board) the ethernet controller will time out on the first init but always succeed after reset. Let's reset the controller during probe so we always start with it in a known state, and don't have wait for the first asix_wait_link() to time out. Signed-off-by: Caleb Connolly <caleb.connolly(a)linaro.org> --- I see this behaviour consistently across three Qualcomm platforms that use this controller. --- drivers/usb/eth/asix88179.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c index 7bfd285b3aa4..a0aa5c25e428 100644 --- a/drivers/usb/eth/asix88179.c +++ b/drivers/usb/eth/asix88179.c @@ -628,8 +628,14 @@ static int ax88179_eth_probe(struct udevice *dev) usb_dev = priv->ueth.pusb_dev; priv->maxpacketsize = usb_dev->epmaxpacketout[AX_ENDPOINT_OUT]; + ret = asix_basic_reset(&priv->ueth, priv); + if (ret) { + printf("Failed to reset ethernet device\n"); + return ret; + } + /* Get the MAC address */ ret = asix_read_mac(&priv->ueth, pdata->enetaddr); if (ret) return ret; -- 2.45.0

3 5

[PATCH] turris_1x: Normalize Kconfig usage
by Tom Rini 13 Jul '24

13 Jul '24

We don't set many options in the board Kconfig entry file but instead use defconfigs, select in some cases on the target itself, or update the "default" options of the main entries when needed. In this case we can remove most of the board Kconfig entries and just add them to the defconfig like other platforms. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- I'd be open to someone else taking this patch and doing a v2 that has one of the defconfig's #include the other and then make the required changes (see other defconfigs which use #include for the constraints however) as an alternative. Cc: "Marek Mojík" <marek.mojik(a)nic.cz> Cc: "Marek Behún" <kabel(a)kernel.org> --- arch/powerpc/cpu/mpc85xx/Kconfig | 4 + board/CZ.NIC/turris_1x/Kconfig | 139 ----------------------------- configs/turris_1x_nor_defconfig | 35 ++++++++ configs/turris_1x_sdcard_defconfig | 47 ++++++++++ 4 files changed, 86 insertions(+), 139 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index b441ba9840ad..fd0ef3633b77 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -177,6 +177,10 @@ config TARGET_TURRIS_1X bool "Support Turris 1.x" select SUPPORT_SPL select ARCH_P2020 + select BOARD_EARLY_INIT_F + select BOARD_EARLY_INIT_R + select LAST_STAGE_INIT + select OF_BOARD_SETUP select SYS_L2_SIZE_512KB config TARGET_P2041RDB diff --git a/board/CZ.NIC/turris_1x/Kconfig b/board/CZ.NIC/turris_1x/Kconfig index baea4d80d1c5..d769c42c1a3b 100644 --- a/board/CZ.NIC/turris_1x/Kconfig +++ b/board/CZ.NIC/turris_1x/Kconfig @@ -13,143 +13,4 @@ config SYS_CONFIG_NAME config DEFAULT_DEVICE_TREE default "turris1x" -# Board functions -config ATSHA204A - default y -config BOARD_EARLY_INIT_F - default y -config BOARD_EARLY_INIT_R - default y -config LAST_STAGE_INIT - default y -config MISC - default y -config OF_BOARD_FIXUP - default y -config OF_BOARD_SETUP - default y - -# ENV -config ENV_SIZE - default 0x2000 -config ENV_SECT_SIZE - default 0x20000 -config ENV_OVERWRITE - default y -config ENV_IS_IN_FLASH - default y -config ENV_ADDR - default 0xeff20000 # in NOR -config SYS_RELOC_GD_ENV_ADDR - default y - -# DDR -config DDR_CLK_FREQ - default 66666666 -config NR_DRAM_BANKS - default 5 - -# UART -config DEBUG_UART_BASE - default 0xffe04500 if DEBUG_UART -config DEBUG_UART_CLOCK - default 37500000 if DEBUG_UART -config SYS_NS16550 - default y - -# I2C -config I2C_SET_DEFAULT_BUS_NUM - default y -config SYS_FSL_I2C_OFFSET - default 0x3000 -config SYS_FSL_HAS_I2C2_OFFSET - default y -config SYS_FSL_I2C2_OFFSET - default 0x3100 -config SYS_I2C_FSL - default y - -# GPIO -config MPC8XXX_GPIO - default y - -# WDT -config WDT_MAX6370 - default y - -# PCIe -config PCI_INIT_R - default y -config PCIE_FSL - default y - -# Ethernet -config MII - default y -config PHY_FIXED - default y -config TSEC_ENET - default y - -# USB -config USB_EHCI_FSL - default y -config USB_XHCI_HCD - default y -config USB_XHCI_PCI - default y - -# SDHC -config FSL_ESDHC - default y -config SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH - default 4 - -# NOR -config MTD_NOR_FLASH - default y -config CFI_FLASH - default y -config FLASH_CFI_MTD - default y -config SYS_FLASH_USE_BUFFER_WRITE - default y - -# NAND -config MTD_RAW_NAND - default y -config NAND_FSL_ELBC - default y -config NAND_FSL_ELBC_DT - default y -config BCH - default y -config SYS_FLASH_CFI - default y -config NAND_ECC_BCH - default y -config SYS_LOAD_ADDR - default 0x1000000 - -if SPL - -config SPL_ENV_SUPPORT - default y -config SPL_FRAMEWORK - default n -config SPL_I2C - default y -config SPL_LIBCOMMON_SUPPORT - default y -config SPL_LIBGENERIC_SUPPORT - default y -config SPL_MPC8XXX_INIT_DDR - default y -config SPL_SERIAL - default y -config SPL_SYS_I2C_LEGACY - default y - -endif - endif diff --git a/configs/turris_1x_nor_defconfig b/configs/turris_1x_nor_defconfig index f06daaaca601..52819b11c8c2 100644 --- a/configs/turris_1x_nor_defconfig +++ b/configs/turris_1x_nor_defconfig @@ -1,7 +1,12 @@ CONFIG_PPC=y CONFIG_TEXT_BASE=0xeff40000 CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_NR_DRAM_BANKS=5 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_SYS_MONITOR_LEN=786432 +CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_ENV_ADDR=0xeff20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set @@ -10,6 +15,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_AHCI=y +CONFIG_OF_BOARD_FIXUP=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -25,6 +31,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run distro_bootcmd" CONFIG_USE_PREBOOT=y +CONFIG_PCI_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_EEPROM is not set @@ -50,6 +57,9 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_FS_UUID=y CONFIG_OF_CONTROL=y CONFIG_OF_INITIAL_DTB_READONLY=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth2" # CONFIG_DM_DEVICE_REMOVE is not set @@ -57,6 +67,7 @@ CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xef001001 @@ -67,21 +78,45 @@ CONFIG_SYS_OR1_PRELIM=0xfffc0796 CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xffa00801 CONFIG_SYS_OR3_PRELIM=0xfffe09f7 +CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_MISC=y +CONFIG_ATSHA204A=y # CONFIG_MMC_HW_PARTITIONING is not set # CONFIG_MMC_VERBOSE is not set +CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_FLASH_QUIET_TEST=y CONFIG_SYS_MAX_FLASH_SECT=128 +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_FSL_ELBC=y +CONFIG_NAND_FSL_ELBC_DT=y CONFIG_MTD_UBI=y +CONFIG_PHY_FIXED=y CONFIG_DM_MDIO=y +CONFIG_MII=y +CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y +CONFIG_PCIE_FSL=y CONFIG_SCSI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_EHCI_FSL=y CONFIG_USB_STORAGE=y CONFIG_WDT=y +CONFIG_WDT_MAX6370=y +CONFIG_BCH=y # CONFIG_BINMAN_FDT is not set diff --git a/configs/turris_1x_sdcard_defconfig b/configs/turris_1x_sdcard_defconfig index fb42e024c50a..b402004f588a 100644 --- a/configs/turris_1x_sdcard_defconfig +++ b/configs/turris_1x_sdcard_defconfig @@ -1,10 +1,20 @@ CONFIG_PPC=y CONFIG_TEXT_BASE=0x11000000 CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=5 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_SPL_TEXT_BASE=0xf8f80000 CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xffe04500 +CONFIG_DEBUG_UART_CLOCK=37500000 +CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_ENV_ADDR=0xeff20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR=y @@ -16,6 +26,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y +CONFIG_OF_BOARD_FIXUP=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -28,6 +39,8 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_USE_PREBOOT=y +CONFIG_PCI_INIT_R=y +# CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_MAX_SIZE=0x80200 CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_MMC_BOOT=y @@ -36,6 +49,9 @@ CONFIG_SPL_RELOC_STACK=0xf8f9d000 CONFIG_SPL_RELOC_MALLOC=y CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000 CONFIG_SPL_RELOC_MALLOC_SIZE=0x5b000 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C=y +CONFIG_SPL_MPC8XXX_INIT_DDR=y CONFIG_SPL_TARGET="u-boot-with-spl.bin" CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y @@ -66,6 +82,9 @@ CONFIG_CMD_SQUASHFS=y CONFIG_CMD_FS_UUID=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth2" CONFIG_NETCONSOLE=y @@ -73,6 +92,7 @@ CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y +CONFIG_DDR_CLK_FREQ=66666666 CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xef001001 @@ -84,15 +104,37 @@ CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xffa00801 CONFIG_SYS_OR3_PRELIM=0xfffe09f7 CONFIG_DM_PCA953X=y +CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_FSL_I2C_OFFSET=0x3000 +CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y +CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 +CONFIG_MISC=y +CONFIG_ATSHA204A=y CONFIG_SYS_I2C_EEPROM_ADDR=0x52 +CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_FLASH_QUIET_TEST=y CONFIG_SYS_MAX_FLASH_SECT=128 +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_FSL_ELBC=y +CONFIG_NAND_FSL_ELBC_DT=y +CONFIG_PHY_FIXED=y CONFIG_DM_MDIO=y +CONFIG_MII=y +CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y +CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y CONFIG_SCSI=y @@ -102,5 +144,10 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_EHCI_FSL=y CONFIG_WDT=y +CONFIG_WDT_MAX6370=y CONFIG_FAT_WRITE=y +CONFIG_BCH=y -- 2.34.1

1 1