June 2024 - U-Boot

[PATCH] arm: dts: k3-*-binman: Make default DM file optional
by Neha Malcom Francis 14 Jun '24

14 Jun '24

The default DM firmware path is non-optional as of now. Make it optional so that users that choose to provide DM via TI_DM argument instead of BINMAN_INDIRS can do so without build errors. Signed-off-by: Neha Malcom Francis <n-francis(a)ti.com> --- arch/arm/dts/k3-am625-sk-binman.dtsi | 1 + arch/arm/dts/k3-am62a-sk-binman.dtsi | 1 + arch/arm/dts/k3-am62p-sk-binman.dtsi | 1 + arch/arm/dts/k3-j7200-binman.dtsi | 1 + arch/arm/dts/k3-j721e-binman.dtsi | 1 + arch/arm/dts/k3-j721s2-binman.dtsi | 1 + arch/arm/dts/k3-j784s4-binman.dtsi | 1 + 7 files changed, 7 insertions(+) diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index dfd38d64f63..eddf05594d5 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -149,6 +149,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi index ec3bf7ce913..6f82f26bf85 100644 --- a/arch/arm/dts/k3-am62a-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -152,6 +152,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi index dea14945bf5..2233921d320 100644 --- a/arch/arm/dts/k3-am62p-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi @@ -72,6 +72,7 @@ blob-ext { filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi index e8020fec2dc..a524b246187 100644 --- a/arch/arm/dts/k3-j7200-binman.dtsi +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -281,6 +281,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi index 1514d897634..0483fc5dd3f 100644 --- a/arch/arm/dts/k3-j721e-binman.dtsi +++ b/arch/arm/dts/k3-j721e-binman.dtsi @@ -310,6 +310,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi index 46297ebef9e..d121d8c0c54 100644 --- a/arch/arm/dts/k3-j721s2-binman.dtsi +++ b/arch/arm/dts/k3-j721s2-binman.dtsi @@ -149,6 +149,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi index e4dd6e14a66..146cd7652c9 100644 --- a/arch/arm/dts/k3-j784s4-binman.dtsi +++ b/arch/arm/dts/k3-j784s4-binman.dtsi @@ -170,6 +170,7 @@ blob-ext { filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; -- 2.34.1

3 2

[PATCH] env: ti: k3_dfu: Drup mmcpart for rootfs
by Neha Malcom Francis 14 Jun '24

14 Jun '24

According to [0], raw access to mmc should not have mmcpart in the entry. This was fixed in k3_dfu_combined.env but k3_dfu.env had been overlooked. [0] doc/usage/dfu.rst Fixes: 53b406369e9d ("DFU: Check the number of arguments and argument string strictly") Signed-off-by: Neha Malcom Francis <n-francis(a)ti.com> --- Boot Logs: https://gist.github.com/nehamalcom/163122d2b9d63607cbb383475978364a include/env/ti/k3_dfu.env | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/env/ti/k3_dfu.env b/include/env/ti/k3_dfu.env index 201529636cc..b42cf21d986 100644 --- a/include/env/ti/k3_dfu.env +++ b/include/env/ti/k3_dfu.env @@ -9,7 +9,7 @@ dfu_alt_info_mmc= dfu_alt_info_emmc= rawemmc raw 0 0x800000 mmcpart 1; - rootfs part 0 1 mmcpart 0; + rootfs part 0 1; tiboot3.bin.raw raw 0x0 0x400 mmcpart 1; tispl.bin.raw raw 0x400 0x1000 mmcpart 1; u-boot.img.raw raw 0x1400 0x2000 mmcpart 1; -- 2.34.1

2 1

[PATCH] arm: dts: k3-j721s2-r5: Change GTC clock parent
by Neha Malcom Francis 14 Jun '24

14 Jun '24

MAIN_PLL0 has a flag set in DM (Device Manager) that removes its capability to re-initialise clock frequencies. A72 CPU clock (GTC) and RGMII has MAIN_PLL3 as their parent which does not have this flag. While RGMII needs re-initialization to default frequency to be able to get 250MHz with its divider, GTC can not get its required 200MHz with its dividers. Thus move GTC clock parent on J721S2 from MAIN_PLL3_HSDIV1 to MAIN_PLL0_HSDIV6. This was already done on CPTS node in kernel which was similarly affected (linked). Link: https://lore.kernel.org/all/20230605110443.84568-1-n-francis@ti.com/ Signed-off-by: Neha Malcom Francis <n-francis(a)ti.com> --- Boot logs: https://gist.github.com/nehamalcom/70676857dc3816a415af9861c38c76eb arch/arm/dts/k3-j721s2-r5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/k3-j721s2-r5.dtsi b/arch/arm/dts/k3-j721s2-r5.dtsi index eb0df42583a..40272abfc7c 100644 --- a/arch/arm/dts/k3-j721s2-r5.dtsi +++ b/arch/arm/dts/k3-j721s2-r5.dtsi @@ -22,7 +22,7 @@ resets = <&k3_reset 202 0>; clocks = <&k3_clks 61 1>; assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>; - assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-parents = <&k3_clks 61 3>; assigned-clock-rates = <200000000>, <2000000000>; ti,sci = <&sms>; ti,sci-proc-id = <32>; -- 2.34.1

2 1

[PATCH 1/1] mmc: consider cd-gpios in Synopsys DesignWare driver
by Heinrich Schuchardt 14 Jun '24

14 Jun '24

The JH7110 SoC uses a GPIO for card detect. * In the of_to_plat function check if a cd-gpios definition exists and request the GPIO. * In the getcd function return the GPIO value in this case. Reported-by: Conor Dooley <conor.dooley(a)microchip.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- drivers/mmc/snps_dw_mmc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c index 9bdbe5070b1..2f0133f22c9 100644 --- a/drivers/mmc/snps_dw_mmc.c +++ b/drivers/mmc/snps_dw_mmc.c @@ -12,6 +12,7 @@ #include <dwmmc.h> #include <errno.h> #include <fdtdec.h> +#include <asm/gpio.h> #include <dm/device_compat.h> #include <linux/libfdt.h> #include <linux/err.h> @@ -29,6 +30,7 @@ struct snps_dwmci_plat { struct snps_dwmci_priv_data { struct dwmci_host host; u32 f_max; + struct gpio_desc cd_gpio; }; static int snps_dwmmc_clk_setup(struct udevice *dev) @@ -106,6 +108,8 @@ static int snps_dwmmc_of_to_plat(struct udevice *dev) if (!ret && priv->f_max < CLOCK_MIN) return -EINVAL; + gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); + host->fifo_mode = dev_read_bool(dev, "fifo-mode"); host->name = dev->name; host->dev_index = 0; @@ -119,6 +123,9 @@ int snps_dwmmc_getcd(struct udevice *dev) struct snps_dwmci_priv_data *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; + if (dm_gpio_is_valid(&priv->cd_gpio)) + return dm_gpio_get_value(&priv->cd_gpio); + return !(dwmci_readl(host, DWMCI_CDETECT) & 1); } -- 2.43.0

1 0

[PATCH v2] doc: describe UEFI measured boot
by Ilias Apalodimas 14 Jun '24

14 Jun '24

We currently only describe the process to enable measured boot using bootm. Describe the UEFI requirements as well which predate bootm. Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- Changes since v1: - fixed remarks from Heinrich on titling and DTB measured PCR doc/usage/measured_boot.rst | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/doc/usage/measured_boot.rst b/doc/usage/measured_boot.rst index 9691904a9d8a..b5f7b05aeb02 100644 --- a/doc/usage/measured_boot.rst +++ b/doc/usage/measured_boot.rst @@ -7,19 +7,39 @@ U-Boot can perform a measured boot, the process of hashing various components of the boot process, extending the results in the TPM and logging the component's measurement in memory for the operating system to consume. +The functionality is available when booting via the EFI subsystem or 'bootm' +command. + +UEFI measured boot +------------------ +The EFI subsystem implements the `EFI TCG protocol +<https://trustedcomputinggroup.org/resource/tcg-efi-protocol-specification/>`_ +and the `TCG PC Client Specific Platform Firmware Profile Specification +<https://trustedcomputinggroup.org/resource/pc-client-specific-platform-firm…>`_ +which defines the binaries to be measured and the corresponding PCRs to be used. + +Requirements +~~~~~~~~~~~~ +* A hardware TPM 2.0 supported by an enabled U-Boot driver +* CONFIG_EFI_TCG2_PROTOCOL=y +* CONFIG_EFI_TCG2_PROTOCOL_EVENTLOG_SIZE=y +* optional CONFIG_EFI_TCG2_PROTOCOL_MEASURE_DTB=y will measure the loaded DTB in PCR 1 + +Measured legacy boot with bootm command +---------------------------------------- By default, U-Boot will measure the operating system (linux) image, the initrd image, and the "bootargs" environment variable. By enabling -CONFIG_MEASURE_DEVICETREE, U-Boot will also measure the devicetree image. +CONFIG_MEASURE_DEVICETREE, U-Boot will also measure the devicetree image in PCR1. The operating system typically would verify that the hashes found in the TPM PCRs match the contents of the event log. This can further be checked against the hash results of previous boots. Requirements ------------- +~~~~~~~~~~~~ -* A hardware TPM 2.0 supported by the U-Boot drivers -* CONFIG_TPM=y +* A hardware TPM 2.0 supported by an enabled U-Boot driver +* CONFIG_TPMv2=y * CONFIG_MEASURED_BOOT=y * Device-tree configuration of the TPM device to specify the memory area for event logging. The TPM device node must either contain a phandle to -- 2.45.1

2 2

[PATCH] video: Add support for NewVision NV3052C SPI panels
by John Watts 14 Jun '24

14 Jun '24

This driver is mostly copied from the Linux kernel and includes support for two physical panels that use this driver. Signed-off-by: John Watts <contact(a)jookia.org> --- This patch is a straightforward port of the kernel NV3052C SPI driver to U-Boot, keeping full compatibility with mainline device tree bindings. --- drivers/video/Kconfig | 6 + drivers/video/Makefile | 1 + drivers/video/newvision-nv3052c.c | 608 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 615 insertions(+) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index e9d069d440..67409a39d2 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -612,6 +612,12 @@ config VIDEO_LCD_HITACHI_TX18D42VM lcd controller which needs to be initialized over SPI, once that is done they work like a regular LVDS panel. +config VIDEO_LCD_NEWVISION_NV3052C + bool "NewVision NV3052C RGB/SPI panel support" + select VIDEO_MIPI_DBI + ---help--- + Support for panels built around the NewVision NV3052C controller. + config VIDEO_LCD_SPI_CS string "SPI CS pin for LCD related config job" depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM diff --git a/drivers/video/Makefile b/drivers/video/Makefile index ad77c60973..c82588ba0b 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -66,6 +66,7 @@ obj-$(CONFIG_VIDEO_LCD_RENESAS_R69328) += renesas-r69328.o obj-$(CONFIG_VIDEO_LCD_SAMSUNG_LTL106HL02) += samsung-ltl106hl02.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o +obj-$(CONFIG_VIDEO_LCD_NEWVISION_NV3052C) += newvision-nv3052c.o obj-$(CONFIG_VIDEO_MCDE_SIMPLE) += mcde_simple.o obj-${CONFIG_VIDEO_MESON} += meson/ obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o diff --git a/drivers/video/newvision-nv3052c.c b/drivers/video/newvision-nv3052c.c new file mode 100644 index 0000000000..2ffa6ae9ed --- /dev/null +++ b/drivers/video/newvision-nv3052c.c @@ -0,0 +1,608 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NewVision NV3052C IPS LCD panel driver + * + * Copyright (C) 2020, Paul Cercueil <paul(a)crapouillou.net> + * Copyright (C) 2022, Christophe Branchereau <cbranchereau(a)gmail.com> + */ + +#include <asm/gpio.h> +#include <backlight.h> +#include <dm/device_compat.h> +#include <dm.h> +#include <linux/delay.h> +#include <mipi_dbi.h> +#include <panel.h> +#include <power/regulator.h> + +struct nv3052c_reg { + u8 cmd; + u8 val; +}; + +struct nv3052c_panel_info { + struct display_timing default_timing; + const struct nv3052c_reg *panel_regs; + unsigned int panel_regs_len; +}; + +struct nv3052c { + const struct nv3052c_panel_info *panel_info; + struct udevice *supply; + struct gpio_desc reset_gpio; + struct udevice *backlight; + struct spi_slave *spi; + struct mipi_dbi dbi; +}; + +static const struct nv3052c_reg ltk035c5444t_panel_regs[] = { + // EXTC Command set enable, select page 1 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 }, + // Mostly unknown registers + { 0xe3, 0x00 }, + { 0x40, 0x00 }, + { 0x03, 0x40 }, + { 0x04, 0x00 }, + { 0x05, 0x03 }, + { 0x08, 0x00 }, + { 0x09, 0x07 }, + { 0x0a, 0x01 }, + { 0x0b, 0x32 }, + { 0x0c, 0x32 }, + { 0x0d, 0x0b }, + { 0x0e, 0x00 }, + { 0x23, 0xa0 }, + { 0x24, 0x0c }, + { 0x25, 0x06 }, + { 0x26, 0x14 }, + { 0x27, 0x14 }, + { 0x38, 0xcc }, // VCOM_ADJ1 + { 0x39, 0xd7 }, // VCOM_ADJ2 + { 0x3a, 0x4a }, // VCOM_ADJ3 + { 0x28, 0x40 }, + { 0x29, 0x01 }, + { 0x2a, 0xdf }, + { 0x49, 0x3c }, + { 0x91, 0x77 }, // EXTPW_CTRL2 + { 0x92, 0x77 }, // EXTPW_CTRL3 + { 0xa0, 0x55 }, + { 0xa1, 0x50 }, + { 0xa4, 0x9c }, + { 0xa7, 0x02 }, + { 0xa8, 0x01 }, + { 0xa9, 0x01 }, + { 0xaa, 0xfc }, + { 0xab, 0x28 }, + { 0xac, 0x06 }, + { 0xad, 0x06 }, + { 0xae, 0x06 }, + { 0xaf, 0x03 }, + { 0xb0, 0x08 }, + { 0xb1, 0x26 }, + { 0xb2, 0x28 }, + { 0xb3, 0x28 }, + { 0xb4, 0x33 }, + { 0xb5, 0x08 }, + { 0xb6, 0x26 }, + { 0xb7, 0x08 }, + { 0xb8, 0x26 }, + { 0xf0, 0x00 }, + { 0xf6, 0xc0 }, + // EXTC Command set enable, select page 2 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, + // Set gray scale voltage to adjust gamma + { 0xb0, 0x0b }, // PGAMVR0 + { 0xb1, 0x16 }, // PGAMVR1 + { 0xb2, 0x17 }, // PGAMVR2 + { 0xb3, 0x2c }, // PGAMVR3 + { 0xb4, 0x32 }, // PGAMVR4 + { 0xb5, 0x3b }, // PGAMVR5 + { 0xb6, 0x29 }, // PGAMPR0 + { 0xb7, 0x40 }, // PGAMPR1 + { 0xb8, 0x0d }, // PGAMPK0 + { 0xb9, 0x05 }, // PGAMPK1 + { 0xba, 0x12 }, // PGAMPK2 + { 0xbb, 0x10 }, // PGAMPK3 + { 0xbc, 0x12 }, // PGAMPK4 + { 0xbd, 0x15 }, // PGAMPK5 + { 0xbe, 0x19 }, // PGAMPK6 + { 0xbf, 0x0e }, // PGAMPK7 + { 0xc0, 0x16 }, // PGAMPK8 + { 0xc1, 0x0a }, // PGAMPK9 + // Set gray scale voltage to adjust gamma + { 0xd0, 0x0c }, // NGAMVR0 + { 0xd1, 0x17 }, // NGAMVR0 + { 0xd2, 0x14 }, // NGAMVR1 + { 0xd3, 0x2e }, // NGAMVR2 + { 0xd4, 0x32 }, // NGAMVR3 + { 0xd5, 0x3c }, // NGAMVR4 + { 0xd6, 0x22 }, // NGAMPR0 + { 0xd7, 0x3d }, // NGAMPR1 + { 0xd8, 0x0d }, // NGAMPK0 + { 0xd9, 0x07 }, // NGAMPK1 + { 0xda, 0x13 }, // NGAMPK2 + { 0xdb, 0x13 }, // NGAMPK3 + { 0xdc, 0x11 }, // NGAMPK4 + { 0xdd, 0x15 }, // NGAMPK5 + { 0xde, 0x19 }, // NGAMPK6 + { 0xdf, 0x10 }, // NGAMPK7 + { 0xe0, 0x17 }, // NGAMPK8 + { 0xe1, 0x0a }, // NGAMPK9 + // EXTC Command set enable, select page 3 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 }, + // Set various timing settings + { 0x00, 0x2a }, // GIP_VST_1 + { 0x01, 0x2a }, // GIP_VST_2 + { 0x02, 0x2a }, // GIP_VST_3 + { 0x03, 0x2a }, // GIP_VST_4 + { 0x04, 0x61 }, // GIP_VST_5 + { 0x05, 0x80 }, // GIP_VST_6 + { 0x06, 0xc7 }, // GIP_VST_7 + { 0x07, 0x01 }, // GIP_VST_8 + { 0x08, 0x03 }, // GIP_VST_9 + { 0x09, 0x04 }, // GIP_VST_10 + { 0x70, 0x22 }, // GIP_ECLK1 + { 0x71, 0x80 }, // GIP_ECLK2 + { 0x30, 0x2a }, // GIP_CLK_1 + { 0x31, 0x2a }, // GIP_CLK_2 + { 0x32, 0x2a }, // GIP_CLK_3 + { 0x33, 0x2a }, // GIP_CLK_4 + { 0x34, 0x61 }, // GIP_CLK_5 + { 0x35, 0xc5 }, // GIP_CLK_6 + { 0x36, 0x80 }, // GIP_CLK_7 + { 0x37, 0x23 }, // GIP_CLK_8 + { 0x40, 0x03 }, // GIP_CLKA_1 + { 0x41, 0x04 }, // GIP_CLKA_2 + { 0x42, 0x05 }, // GIP_CLKA_3 + { 0x43, 0x06 }, // GIP_CLKA_4 + { 0x44, 0x11 }, // GIP_CLKA_5 + { 0x45, 0xe8 }, // GIP_CLKA_6 + { 0x46, 0xe9 }, // GIP_CLKA_7 + { 0x47, 0x11 }, // GIP_CLKA_8 + { 0x48, 0xea }, // GIP_CLKA_9 + { 0x49, 0xeb }, // GIP_CLKA_10 + { 0x50, 0x07 }, // GIP_CLKB_1 + { 0x51, 0x08 }, // GIP_CLKB_2 + { 0x52, 0x09 }, // GIP_CLKB_3 + { 0x53, 0x0a }, // GIP_CLKB_4 + { 0x54, 0x11 }, // GIP_CLKB_5 + { 0x55, 0xec }, // GIP_CLKB_6 + { 0x56, 0xed }, // GIP_CLKB_7 + { 0x57, 0x11 }, // GIP_CLKB_8 + { 0x58, 0xef }, // GIP_CLKB_9 + { 0x59, 0xf0 }, // GIP_CLKB_10 + // Map internal GOA signals to GOA output pad + { 0xb1, 0x01 }, // PANELD2U2 + { 0xb4, 0x15 }, // PANELD2U5 + { 0xb5, 0x16 }, // PANELD2U6 + { 0xb6, 0x09 }, // PANELD2U7 + { 0xb7, 0x0f }, // PANELD2U8 + { 0xb8, 0x0d }, // PANELD2U9 + { 0xb9, 0x0b }, // PANELD2U10 + { 0xba, 0x00 }, // PANELD2U11 + { 0xc7, 0x02 }, // PANELD2U24 + { 0xca, 0x17 }, // PANELD2U27 + { 0xcb, 0x18 }, // PANELD2U28 + { 0xcc, 0x0a }, // PANELD2U29 + { 0xcd, 0x10 }, // PANELD2U30 + { 0xce, 0x0e }, // PANELD2U31 + { 0xcf, 0x0c }, // PANELD2U32 + { 0xd0, 0x00 }, // PANELD2U33 + // Map internal GOA signals to GOA output pad + { 0x81, 0x00 }, // PANELU2D2 + { 0x84, 0x15 }, // PANELU2D5 + { 0x85, 0x16 }, // PANELU2D6 + { 0x86, 0x10 }, // PANELU2D7 + { 0x87, 0x0a }, // PANELU2D8 + { 0x88, 0x0c }, // PANELU2D9 + { 0x89, 0x0e }, // PANELU2D10 + { 0x8a, 0x02 }, // PANELU2D11 + { 0x97, 0x00 }, // PANELU2D24 + { 0x9a, 0x17 }, // PANELU2D27 + { 0x9b, 0x18 }, // PANELU2D28 + { 0x9c, 0x0f }, // PANELU2D29 + { 0x9d, 0x09 }, // PANELU2D30 + { 0x9e, 0x0b }, // PANELU2D31 + { 0x9f, 0x0d }, // PANELU2D32 + { 0xa0, 0x01 }, // PANELU2D33 + // EXTC Command set enable, select page 2 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, + // Unknown registers + { 0x01, 0x01 }, + { 0x02, 0xda }, + { 0x03, 0xba }, + { 0x04, 0xa8 }, + { 0x05, 0x9a }, + { 0x06, 0x70 }, + { 0x07, 0xff }, + { 0x08, 0x91 }, + { 0x09, 0x90 }, + { 0x0a, 0xff }, + { 0x0b, 0x8f }, + { 0x0c, 0x60 }, + { 0x0d, 0x58 }, + { 0x0e, 0x48 }, + { 0x0f, 0x38 }, + { 0x10, 0x2b }, + // EXTC Command set enable, select page 0 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 }, + // Display Access Control + { 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0 +}; + +static const struct nv3052c_reg fs035vg158_panel_regs[] = { + // EXTC Command set enable, select page 1 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 }, + // Mostly unknown registers + { 0xe3, 0x00 }, + { 0x40, 0x00 }, + { 0x03, 0x40 }, + { 0x04, 0x00 }, + { 0x05, 0x03 }, + { 0x08, 0x00 }, + { 0x09, 0x07 }, + { 0x0a, 0x01 }, + { 0x0b, 0x32 }, + { 0x0c, 0x32 }, + { 0x0d, 0x0b }, + { 0x0e, 0x00 }, + { 0x23, 0x20 }, // RGB interface control: DE MODE PCLK-N + { 0x24, 0x0c }, + { 0x25, 0x06 }, + { 0x26, 0x14 }, + { 0x27, 0x14 }, + { 0x38, 0x9c }, //VCOM_ADJ1, different to ltk035c5444t + { 0x39, 0xa7 }, //VCOM_ADJ2, different to ltk035c5444t + { 0x3a, 0x50 }, //VCOM_ADJ3, different to ltk035c5444t + { 0x28, 0x40 }, + { 0x29, 0x01 }, + { 0x2a, 0xdf }, + { 0x49, 0x3c }, + { 0x91, 0x57 }, //EXTPW_CTRL2, different to ltk035c5444t + { 0x92, 0x57 }, //EXTPW_CTRL3, different to ltk035c5444t + { 0xa0, 0x55 }, + { 0xa1, 0x50 }, + { 0xa4, 0x9c }, + { 0xa7, 0x02 }, + { 0xa8, 0x01 }, + { 0xa9, 0x01 }, + { 0xaa, 0xfc }, + { 0xab, 0x28 }, + { 0xac, 0x06 }, + { 0xad, 0x06 }, + { 0xae, 0x06 }, + { 0xaf, 0x03 }, + { 0xb0, 0x08 }, + { 0xb1, 0x26 }, + { 0xb2, 0x28 }, + { 0xb3, 0x28 }, + { 0xb4, 0x03 }, // Unknown, different to ltk035c5444 + { 0xb5, 0x08 }, + { 0xb6, 0x26 }, + { 0xb7, 0x08 }, + { 0xb8, 0x26 }, + { 0xf0, 0x00 }, + { 0xf6, 0xc0 }, + // EXTC Command set enable, select page 0 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, + // Set gray scale voltage to adjust gamma + { 0xb0, 0x0b }, // PGAMVR0 + { 0xb1, 0x16 }, // PGAMVR1 + { 0xb2, 0x17 }, // PGAMVR2 + { 0xb3, 0x2c }, // PGAMVR3 + { 0xb4, 0x32 }, // PGAMVR4 + { 0xb5, 0x3b }, // PGAMVR5 + { 0xb6, 0x29 }, // PGAMPR0 + { 0xb7, 0x40 }, // PGAMPR1 + { 0xb8, 0x0d }, // PGAMPK0 + { 0xb9, 0x05 }, // PGAMPK1 + { 0xba, 0x12 }, // PGAMPK2 + { 0xbb, 0x10 }, // PGAMPK3 + { 0xbc, 0x12 }, // PGAMPK4 + { 0xbd, 0x15 }, // PGAMPK5 + { 0xbe, 0x19 }, // PGAMPK6 + { 0xbf, 0x0e }, // PGAMPK7 + { 0xc0, 0x16 }, // PGAMPK8 + { 0xc1, 0x0a }, // PGAMPK9 + // Set gray scale voltage to adjust gamma + { 0xd0, 0x0c }, // NGAMVR0 + { 0xd1, 0x17 }, // NGAMVR0 + { 0xd2, 0x14 }, // NGAMVR1 + { 0xd3, 0x2e }, // NGAMVR2 + { 0xd4, 0x32 }, // NGAMVR3 + { 0xd5, 0x3c }, // NGAMVR4 + { 0xd6, 0x22 }, // NGAMPR0 + { 0xd7, 0x3d }, // NGAMPR1 + { 0xd8, 0x0d }, // NGAMPK0 + { 0xd9, 0x07 }, // NGAMPK1 + { 0xda, 0x13 }, // NGAMPK2 + { 0xdb, 0x13 }, // NGAMPK3 + { 0xdc, 0x11 }, // NGAMPK4 + { 0xdd, 0x15 }, // NGAMPK5 + { 0xde, 0x19 }, // NGAMPK6 + { 0xdf, 0x10 }, // NGAMPK7 + { 0xe0, 0x17 }, // NGAMPK8 + { 0xe1, 0x0a }, // NGAMPK9 + // EXTC Command set enable, select page 3 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 }, + // Set various timing settings + { 0x00, 0x2a }, // GIP_VST_1 + { 0x01, 0x2a }, // GIP_VST_2 + { 0x02, 0x2a }, // GIP_VST_3 + { 0x03, 0x2a }, // GIP_VST_4 + { 0x04, 0x61 }, // GIP_VST_5 + { 0x05, 0x80 }, // GIP_VST_6 + { 0x06, 0xc7 }, // GIP_VST_7 + { 0x07, 0x01 }, // GIP_VST_8 + { 0x08, 0x03 }, // GIP_VST_9 + { 0x09, 0x04 }, // GIP_VST_10 + { 0x70, 0x22 }, // GIP_ECLK1 + { 0x71, 0x80 }, // GIP_ECLK2 + { 0x30, 0x2a }, // GIP_CLK_1 + { 0x31, 0x2a }, // GIP_CLK_2 + { 0x32, 0x2a }, // GIP_CLK_3 + { 0x33, 0x2a }, // GIP_CLK_4 + { 0x34, 0x61 }, // GIP_CLK_5 + { 0x35, 0xc5 }, // GIP_CLK_6 + { 0x36, 0x80 }, // GIP_CLK_7 + { 0x37, 0x23 }, // GIP_CLK_8 + { 0x40, 0x03 }, // GIP_CLKA_1 + { 0x41, 0x04 }, // GIP_CLKA_2 + { 0x42, 0x05 }, // GIP_CLKA_3 + { 0x43, 0x06 }, // GIP_CLKA_4 + { 0x44, 0x11 }, // GIP_CLKA_5 + { 0x45, 0xe8 }, // GIP_CLKA_6 + { 0x46, 0xe9 }, // GIP_CLKA_7 + { 0x47, 0x11 }, // GIP_CLKA_8 + { 0x48, 0xea }, // GIP_CLKA_9 + { 0x49, 0xeb }, // GIP_CLKA_10 + { 0x50, 0x07 }, // GIP_CLKB_1 + { 0x51, 0x08 }, // GIP_CLKB_2 + { 0x52, 0x09 }, // GIP_CLKB_3 + { 0x53, 0x0a }, // GIP_CLKB_4 + { 0x54, 0x11 }, // GIP_CLKB_5 + { 0x55, 0xec }, // GIP_CLKB_6 + { 0x56, 0xed }, // GIP_CLKB_7 + { 0x57, 0x11 }, // GIP_CLKB_8 + { 0x58, 0xef }, // GIP_CLKB_9 + { 0x59, 0xf0 }, // GIP_CLKB_10 + // Map internal GOA signals to GOA output pad + { 0xb1, 0x01 }, // PANELD2U2 + { 0xb4, 0x15 }, // PANELD2U5 + { 0xb5, 0x16 }, // PANELD2U6 + { 0xb6, 0x09 }, // PANELD2U7 + { 0xb7, 0x0f }, // PANELD2U8 + { 0xb8, 0x0d }, // PANELD2U9 + { 0xb9, 0x0b }, // PANELD2U10 + { 0xba, 0x00 }, // PANELD2U11 + { 0xc7, 0x02 }, // PANELD2U24 + { 0xca, 0x17 }, // PANELD2U27 + { 0xcb, 0x18 }, // PANELD2U28 + { 0xcc, 0x0a }, // PANELD2U29 + { 0xcd, 0x10 }, // PANELD2U30 + { 0xce, 0x0e }, // PANELD2U31 + { 0xcf, 0x0c }, // PANELD2U32 + { 0xd0, 0x00 }, // PANELD2U33 + // Map internal GOA signals to GOA output pad + { 0x81, 0x00 }, // PANELU2D2 + { 0x84, 0x15 }, // PANELU2D5 + { 0x85, 0x16 }, // PANELU2D6 + { 0x86, 0x10 }, // PANELU2D7 + { 0x87, 0x0a }, // PANELU2D8 + { 0x88, 0x0c }, // PANELU2D9 + { 0x89, 0x0e }, // PANELU2D10 + { 0x8a, 0x02 }, // PANELU2D11 + { 0x97, 0x00 }, // PANELU2D24 + { 0x9a, 0x17 }, // PANELU2D27 + { 0x9b, 0x18 }, // PANELU2D28 + { 0x9c, 0x0f }, // PANELU2D29 + { 0x9d, 0x09 }, // PANELU2D30 + { 0x9e, 0x0b }, // PANELU2D31 + { 0x9f, 0x0d }, // PANELU2D32 + { 0xa0, 0x01 }, // PANELU2D33 + // EXTC Command set enable, select page 2 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, + // Unknown registers + { 0x01, 0x01 }, + { 0x02, 0xda }, + { 0x03, 0xba }, + { 0x04, 0xa8 }, + { 0x05, 0x9a }, + { 0x06, 0x70 }, + { 0x07, 0xff }, + { 0x08, 0x91 }, + { 0x09, 0x90 }, + { 0x0a, 0xff }, + { 0x0b, 0x8f }, + { 0x0c, 0x60 }, + { 0x0d, 0x58 }, + { 0x0e, 0x48 }, + { 0x0f, 0x38 }, + { 0x10, 0x2b }, + // EXTC Command set enable, select page 0 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 }, + // Display Access Control + { 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0 +}; + +static const struct nv3052c_panel_info ltk035c5444t_panel_info = { + .default_timing = { + .pixelclock.typ = 24000000, + .hactive.typ = 640, + .hfront_porch.typ = 96, + .hback_porch.typ = 16, + .hsync_len.typ = 48, + .vactive.typ = 480, + .vfront_porch.typ = 5, + .vback_porch.typ = 2, + .vsync_len.typ = 13, + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE, + }, + .panel_regs = ltk035c5444t_panel_regs, + .panel_regs_len = ARRAY_SIZE(ltk035c5444t_panel_regs), +}; + +static const struct nv3052c_panel_info fs035vg158_panel_info = { + .default_timing = { + .pixelclock.typ = 21000000, + .hactive.typ = 640, + .hfront_porch.typ = 34, + .hback_porch.typ = 20, + .hsync_len.typ = 4, + .vactive.typ = 480, + .vfront_porch.typ = 12, + .vback_porch.typ = 6, + .vsync_len.typ = 4, + .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE, + }, + .panel_regs = fs035vg158_panel_regs, + .panel_regs_len = ARRAY_SIZE(fs035vg158_panel_regs), +}; + +static const struct nv3052c_panel_info *panel_infos[] = { + &ltk035c5444t_panel_info, + &fs035vg158_panel_info, +}; + +static int nv3052c_panel_enable_backlight(struct udevice *dev) +{ + struct nv3052c *priv = dev_get_priv(dev); + struct mipi_dbi *dbi = &priv->dbi; + int err; + + err = mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON); + if (err) { + dev_err(dev, "Unable to enable display: %d\n", err); + return err; + } + + if (priv->backlight) { + /* Wait for the picture to be ready before enabling backlight */ + mdelay(120); + err = backlight_enable(priv->backlight); + } + + return err; +} + +static int nv3052c_panel_get_display_timing(struct udevice *dev, + struct display_timing *timing) +{ + struct nv3052c *priv = dev_get_priv(dev); + const struct nv3052c_panel_info *info = priv->panel_info; + const struct display_timing *our_timing = &info->default_timing; + + memcpy(timing, our_timing, sizeof(*our_timing)); + + return 0; +} + +static int nv3052c_panel_of_to_plat(struct udevice *dev) +{ + struct nv3052c *priv = dev_get_priv(dev); + int panel_info_index = dev_get_driver_data(dev); + int err; + + priv->spi = dev_get_parent_priv(dev); + priv->panel_info = panel_infos[panel_info_index]; + + if (CONFIG_IS_ENABLED(DM_REGULATOR)) { + err = device_get_supply_regulator(dev, "power-supply", + &priv->supply); + if (err) { + dev_err(dev, "Failed to get power supply: %d\n", err); + return err; + } + } + + err = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio, + GPIOD_IS_OUT); + if (err) { + dev_err(dev, "Failed to get reset GPIO: %d\n", err); + return err; + } + + err = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, + "backlight", &priv->backlight); + if (err) { + dev_err(dev, "Failed to get backlight: %d\n", err); + return err; + } + + return 0; +} + +static int nv3052c_panel_probe(struct udevice *dev) +{ + struct nv3052c *priv = dev_get_priv(dev); + const struct nv3052c_reg *panel_regs = priv->panel_info->panel_regs; + unsigned int panel_regs_len = priv->panel_info->panel_regs_len; + struct mipi_dbi *dbi = &priv->dbi; + unsigned int i; + int err; + + err = mipi_dbi_spi_init(priv->spi, &priv->dbi, NULL); + if (err) { + dev_err(dev, "MPI DBI init failed: %d\n", err); + return err; + } + + if (CONFIG_IS_ENABLED(DM_REGULATOR)) { + err = regulator_set_enable(priv->supply, true); + if (err) { + dev_err(dev, "Failed to enable power supply: %d\n", err); + return err; + } + } + + /* Reset the chip */ + dm_gpio_set_value(&priv->reset_gpio, true); + mdelay(1); + dm_gpio_set_value(&priv->reset_gpio, false); + mdelay(150); + + for (i = 0; i < panel_regs_len; i++) { + err = mipi_dbi_command(dbi, panel_regs[i].cmd, + panel_regs[i].val); + + if (err) { + dev_err(dev, "Unable to set register: %d\n", err); + goto err_disable_regulator; + } + } + + err = mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE); + if (err) { + dev_err(dev, "Unable to exit sleep mode: %d\n", err); + goto err_disable_regulator; + } + + return 0; + +err_disable_regulator: + if (CONFIG_IS_ENABLED(DM_REGULATOR)) + regulator_set_enable(priv->supply, false); + + return err; +} + +static const struct panel_ops nv3052c_panel_ops = { + .enable_backlight = nv3052c_panel_enable_backlight, + .get_display_timing = nv3052c_panel_get_display_timing, +}; + +static const struct udevice_id nv3052c_panel_ids[] = { + { .compatible = "leadtek,ltk035c5444t", .data = 0 }, + { .compatible = "fascontek,fs035vg158", .data = 1 }, + { } +}; + +U_BOOT_DRIVER(nv3052c_panel) = { + .name = "nv3052c_panel", + .id = UCLASS_PANEL, + .of_match = nv3052c_panel_ids, + .ops = &nv3052c_panel_ops, + .of_to_plat = nv3052c_panel_of_to_plat, + .probe = nv3052c_panel_probe, + .priv_auto = sizeof(struct nv3052c), +}; --- base-commit: 0cc0eab0a140b5e660c25a27e116c9be538c1c12 change-id: 20240601-panel_nv3052c-76bab2b2c358 Best regards, -- John Watts <contact(a)jookia.org>

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[PATCH 0/2] sunxi: video: Fix lcdc polarity display flags
by John Watts 14 Jun '24

14 Jun '24

The current LCD controller driver has incorrect polarity masks, so I've provided a fix for that. While I was there I also added support for two new display flags related to polarities. Signed-off-by: John Watts <contact(a)jookia.org> --- John Watts (2): sunxi: video: Properly invert hsync and vsync polarity sunxi: video: Support DE_LOW and PIXDATA_NEGEDGE display flags arch/arm/include/asm/arch-sunxi/lcdc.h | 2 ++ drivers/video/sunxi/lcdc.c | 8 ++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) --- base-commit: c0ea27bccfb7d2d37fd36806ac2a2f7389099420 change-id: 20240614-sunxipolarities-a9a21c30c82b Best regards, -- John Watts <contact(a)jookia.org>

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[PATCH] sunxi: video: Support driver model LCDs
by John Watts 14 Jun '24

14 Jun '24

Currently the LCD code only supports reading panel timings from the device tree. Change that so it can use a real panel. Signed-off-by: John Watts <contact(a)jookia.org> --- I've been working on a panel driver port from Linux for the T113 and found I need this code to have the panel boot correctly. --- drivers/video/sunxi/sunxi_lcd.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/video/sunxi/sunxi_lcd.c b/drivers/video/sunxi/sunxi_lcd.c index 7a01cc343c..605ea90de1 100644 --- a/drivers/video/sunxi/sunxi_lcd.c +++ b/drivers/video/sunxi/sunxi_lcd.c @@ -8,6 +8,7 @@ #include <common.h> #include <display.h> #include <log.h> +#include <panel.h> #include <video_bridge.h> #include <backlight.h> #include <dm.h> @@ -45,6 +46,7 @@ static int sunxi_lcd_enable(struct udevice *dev, int bpp, (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; struct sunxi_lcd_priv *priv = dev_get_priv(dev); struct udevice *backlight; + struct udevice *panel; int clk_div, clk_double, ret; /* Reset off */ @@ -60,6 +62,12 @@ static int sunxi_lcd_enable(struct udevice *dev, int bpp, priv->panel_bpp, CONFIG_VIDEO_LCD_DCLK_PHASE); lcdc_enable(lcdc, priv->panel_bpp); + ret = uclass_get_device(UCLASS_PANEL, 0, &panel); + if (ret == 0) { + if (panel_enable_backlight(panel) == 0) + return 0; + } + ret = uclass_get_device(UCLASS_PANEL_BACKLIGHT, 0, &backlight); if (!ret) backlight_enable(backlight); @@ -116,6 +124,11 @@ static int sunxi_lcd_probe(struct udevice *dev) return ret; } + if (panel_get_display_timing(cdev, &priv->timing) == 0) { + priv->panel_bpp = 32; + return 0; + } + if (fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(cdev), 0, &priv->timing)) { debug("%s: Failed to decode display timing\n", __func__); --- base-commit: c0ea27bccfb7d2d37fd36806ac2a2f7389099420 change-id: 20240601-sunxi_lcd-d39a4fb81c94 Best regards, -- John Watts <contact(a)jookia.org>

1 0

[PATCH 0/5] video: add support for MIPI DBI interface
by John Watts 14 Jun '24

14 Jun '24

Many simple RGB panels use a MIPI DBI interface over SPI, so this patch adds support for this interface using an API compatible with Linux. The MIPI DBI interface works similar to SPI using 8-bit words in the format of: COMMAND DATA1 DATA2 ... However the interface has two variations on this. The first variation is implemented by this patch series: Using 9-bit words, with the first bit signalling whether the word is a COMMAND or DATA. The second variation is not implemented by this series: A GPIO is held at a value during an 8-bit word to indicate if it's a COMMAND or WORD. Adding support for this wouldn't be too hard, but I don't have any hardware to test it on. Linux seems to not implement the specification correctly: It sets CS inactive between words instead of keeping it active for the entire transaction. I'm copying this behaviour to keep compatibility in porting panels across from the kernel. Signed-off-by: John Watts <contact(a)jookia.org> --- John Watts (5): spi: Return old wordlen in spit_set_wordlen spi: Limit spi_set_wordlen to SPI_DEFAULT_WORDLEN spi: Implement spi_set_wordlen for driver model spi: softspi: Support setting wordlen video: add support for MIPI DBI interface drivers/spi/soft_spi.c | 7 +++++ drivers/spi/spi-uclass.c | 29 +++++++++++++++++++ drivers/spi/spi.c | 6 ++-- drivers/video/Kconfig | 6 ++++ drivers/video/Makefile | 1 + drivers/video/mipi_dbi.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++ include/mipi_dbi.h | 73 ++++++++++++++++++++++++++++++++++++++++++++++++ include/spi.h | 2 +- 8 files changed, 191 insertions(+), 3 deletions(-) --- base-commit: c0ea27bccfb7d2d37fd36806ac2a2f7389099420 change-id: 20240601-mipi_dbi-aeda98f2f9d5 Best regards, -- John Watts <contact(a)jookia.org>

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[PATCH] doc: describe UEFI measured boot
by Ilias Apalodimas 14 Jun '24

14 Jun '24

We currently only describe the process to enable measured boot using bootm. Describe the UEFI requirements as well which predate bootm. Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- doc/usage/measured_boot.rst | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/doc/usage/measured_boot.rst b/doc/usage/measured_boot.rst index 9691904a9d8a..1b5dd1dcc438 100644 --- a/doc/usage/measured_boot.rst +++ b/doc/usage/measured_boot.rst @@ -7,6 +7,26 @@ U-Boot can perform a measured boot, the process of hashing various components of the boot process, extending the results in the TPM and logging the component's measurement in memory for the operating system to consume. +The functionality is available when booting via the EFI subsystem or 'bootm' +command. + +UEFI subsystem +-------------- +The EFI subsystem implements the `EFI TCG protocol +<https://trustedcomputinggroup.org/resource/tcg-efi-protocol-specification/>`_ +and the `TCG PC Client Specific Platform Firmware Profile Specification +<https://trustedcomputinggroup.org/resource/pc-client-specific-platform-firm…>`_ +which defines the binaries to be measured and the corresponding PCRs used. + +UEFI requirements +~~~~~~~~~~~~~~~~~ +* A hardware TPM 2.0 supported by the U-Boot drivers +* CONFIG_EFI_TCG2_PROTOCOL=y +* CONFIG_EFI_TCG2_PROTOCOL_EVENTLOG_SIZE=y +* optional CONFIG_EFI_TCG2_PROTOCOL_MEASURE_DTB=y will measure the loaded DTB in PCR 0 + +bootm +----- By default, U-Boot will measure the operating system (linux) image, the initrd image, and the "bootargs" environment variable. By enabling CONFIG_MEASURE_DEVICETREE, U-Boot will also measure the devicetree image. @@ -15,8 +35,8 @@ The operating system typically would verify that the hashes found in the TPM PCRs match the contents of the event log. This can further be checked against the hash results of previous boots. -Requirements ------------- +bootm requirements +~~~~~~~~~~~~~~~~~~ * A hardware TPM 2.0 supported by the U-Boot drivers * CONFIG_TPM=y -- 2.45.1

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