April 2024 - U-Boot

Re: [PATCH 07/11] net: dwc_eth_qos: Use consistent logging prints
by Christophe ROULLIER 05 Apr '24

05 Apr '24

> On 3/9/24 03:11, Marek Vasut wrote: >> Use dev_*() only to print all the logs from this glue code, instead of >> mixing dev_*(), log_*(), pr_*() all in one code. >> >> Signed-off-by: Marek Vasut <marex(a)denx.de> >> --- >> Cc: Christophe Roullier <christophe.roullier(a)st.com> >> Cc: Joe Hershberger <joe.hershberger(a)ni.com> >> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> >> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> >> Cc: Ramon Fried <rfried.dev(a)gmail.com> >> Cc: u-boot(a)dh-electronics.com >> Cc: uboot-stm32(a)st-md-mailman.stormreply.com >> --- >> drivers/net/dwc_eth_qos_stm32.c | 52 >> ++++++++++++++++++--------------- >> 1 file changed, 28 insertions(+), 24 deletions(-) >> >> diff --git a/drivers/net/dwc_eth_qos_stm32.c >> b/drivers/net/dwc_eth_qos_stm32.c index 38037c47954..72f65f80540 >> 100644 >> --- a/drivers/net/dwc_eth_qos_stm32.c >> +++ b/drivers/net/dwc_eth_qos_stm32.c >> @@ -63,36 +63,36 @@ static int eqos_start_clks_stm32(struct udevice *dev) >> if (!CONFIG_IS_ENABLED(CLK)) >> return 0; >> >> - debug("%s(dev=%p):\n", __func__, dev); >> + dev_dbg(dev, "%s:\n", __func__); >> >> ret = clk_enable(&eqos->clk_master_bus); >> if (ret < 0) { >> - pr_err("clk_enable(clk_master_bus) failed: %d", ret); >> + dev_err(dev, "clk_enable(clk_master_bus) failed: %d\n", ret); >> goto err; >> } >> >> ret = clk_enable(&eqos->clk_rx); >> if (ret < 0) { >> - pr_err("clk_enable(clk_rx) failed: %d", ret); >> + dev_err(dev, "clk_enable(clk_rx) failed: %d\n", ret); >> goto err_disable_clk_master_bus; >> } >> >> ret = clk_enable(&eqos->clk_tx); >> if (ret < 0) { >> - pr_err("clk_enable(clk_tx) failed: %d", ret); >> + dev_err(dev, "clk_enable(clk_tx) failed: %d\n", ret); >> goto err_disable_clk_rx; >> } >> >> if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) { >> ret = clk_enable(&eqos->clk_ck); >> if (ret < 0) { >> - pr_err("clk_enable(clk_ck) failed: %d", ret); >> + dev_err(dev, "clk_enable(clk_ck) failed: %d\n", ret); >> goto err_disable_clk_tx; >> } >> eqos->clk_ck_enabled = true; >> } >> >> - debug("%s: OK\n", __func__); >> + dev_dbg(dev, "%s: OK\n", __func__); >> return 0; >> >> err_disable_clk_tx: >> @@ -102,7 +102,8 @@ err_disable_clk_rx: >> err_disable_clk_master_bus: >> clk_disable(&eqos->clk_master_bus); >> err: >> - debug("%s: FAILED: %d\n", __func__, ret); >> + dev_dbg(dev, "%s: FAILED: %d\n", __func__, ret); >> + >> return ret; >> } >> >> @@ -113,13 +114,14 @@ static int eqos_stop_clks_stm32(struct udevice *dev) >> if (!CONFIG_IS_ENABLED(CLK)) >> return 0; >> >> - debug("%s(dev=%p):\n", __func__, dev); >> + dev_dbg(dev, "%s:\n", __func__); >> >> clk_disable(&eqos->clk_tx); >> clk_disable(&eqos->clk_rx); >> clk_disable(&eqos->clk_master_bus); >> >> - debug("%s: OK\n", __func__); >> + dev_dbg(dev, "%s: OK\n", __func__); >> + >> return 0; >> } >> >> @@ -143,20 +145,20 @@ static int eqos_probe_syscfg_stm32(struct >> udevice *dev, >> >> switch (interface_type) { >> case PHY_INTERFACE_MODE_MII: >> - log_debug("PHY_INTERFACE_MODE_MII\n"); >> + dev_dbg(dev, "PHY_INTERFACE_MODE_MII\n"); >> value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, >> SYSCFG_PMCSETR_ETH_SEL_GMII_MII); >> value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> break; >> case PHY_INTERFACE_MODE_GMII: >> - log_debug("PHY_INTERFACE_MODE_GMII\n"); >> + dev_dbg(dev, "PHY_INTERFACE_MODE_GMII\n"); >> value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, >> SYSCFG_PMCSETR_ETH_SEL_GMII_MII); >> if (eth_clk_sel_reg) >> value |= SYSCFG_PMCSETR_ETH_CLK_SEL; >> break; >> case PHY_INTERFACE_MODE_RMII: >> - log_debug("PHY_INTERFACE_MODE_RMII\n"); >> + dev_dbg(dev, "PHY_INTERFACE_MODE_RMII\n"); >> value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, >> SYSCFG_PMCSETR_ETH_SEL_RMII); >> if (eth_ref_clk_sel_reg) >> @@ -166,15 +168,15 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev, >> case PHY_INTERFACE_MODE_RGMII_ID: >> case PHY_INTERFACE_MODE_RGMII_RXID: >> case PHY_INTERFACE_MODE_RGMII_TXID: >> - log_debug("PHY_INTERFACE_MODE_RGMII\n"); >> + dev_dbg(dev, "PHY_INTERFACE_MODE_RGMII\n"); >> value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, >> SYSCFG_PMCSETR_ETH_SEL_RGMII); >> if (eth_clk_sel_reg) >> value |= SYSCFG_PMCSETR_ETH_CLK_SEL; >> break; >> default: >> - log_debug("Do not manage %d interface\n", >> - interface_type); >> + dev_dbg(dev, "Do not manage %d interface\n", >> + interface_type); >> /* Do not manage others interfaces */ >> return -EINVAL; >> } >> @@ -194,12 +196,12 @@ static int eqos_probe_resources_stm32(struct udevice *dev) >> phy_interface_t interface; >> int ret; >> >> - debug("%s(dev=%p):\n", __func__, dev); >> + dev_dbg(dev, "%s:\n", __func__); >> >> interface = eqos->config->interface(dev); >> >> if (interface == PHY_INTERFACE_MODE_NA) { >> - pr_err("Invalid PHY interface\n"); >> + dev_err(dev, "Invalid PHY interface\n"); >> return -EINVAL; >> } >> >> @@ -209,39 +211,41 @@ static int eqos_probe_resources_stm32(struct >> udevice *dev) >> >> ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus); >> if (ret) { >> - pr_err("clk_get_by_name(master_bus) failed: %d", ret); >> + dev_err(dev, "clk_get_by_name(master_bus) failed: %d\n", ret); >> goto err_probe; >> } >> >> ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx); >> if (ret) { >> - pr_err("clk_get_by_name(rx) failed: %d", ret); >> + dev_err(dev, "clk_get_by_name(rx) failed: %d\n", ret); >> goto err_probe; >> } >> >> ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx); >> if (ret) { >> - pr_err("clk_get_by_name(tx) failed: %d", ret); >> + dev_err(dev, "clk_get_by_name(tx) failed: %d\n", ret); >> goto err_probe; >> } >> >> /* Get ETH_CLK clocks (optional) */ >> ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck); >> if (ret) >> - pr_warn("No phy clock provided %d", ret); >> + dev_warn(dev, "No phy clock provided %d\n", ret); >> + >> + dev_dbg(dev, "%s: OK\n", __func__); >> >> - debug("%s: OK\n", __func__); >> return 0; >> >> err_probe: >> >> - debug("%s: returns %d\n", __func__, ret); >> + dev_dbg(dev, "%s: returns %d\n", __func__, ret); >> + >> return ret; >> } >> >> static int eqos_remove_resources_stm32(struct udevice *dev) { >> - debug("%s(dev=%p):\n", __func__, dev); >> + dev_dbg(dev, "%s:\n", __func__); >> >> return 0; >> } > Reviewed-by: Christophe ROULLIER <christophe.roullier(a)foss.st.com>

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Re: [PATCH 06/11] net: dwc_eth_qos: Move log_debug statements on top of case block
by Christophe ROULLIER 05 Apr '24

05 Apr '24

> On 3/9/24 03:11, Marek Vasut wrote: >> Move the log_debug() calls on top of the bit manipulation code. >> No functional change. >> >> Signed-off-by: Marek Vasut <marex(a)denx.de> >> --- >> Cc: Christophe Roullier <christophe.roullier(a)st.com> >> Cc: Joe Hershberger <joe.hershberger(a)ni.com> >> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> >> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> >> Cc: Ramon Fried <rfried.dev(a)gmail.com> >> Cc: u-boot(a)dh-electronics.com >> Cc: uboot-stm32(a)st-md-mailman.stormreply.com >> --- >> drivers/net/dwc_eth_qos_stm32.c | 8 ++++---- >> 1 file changed, 4 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/net/dwc_eth_qos_stm32.c >> b/drivers/net/dwc_eth_qos_stm32.c index 7545026b158..38037c47954 >> 100644 >> --- a/drivers/net/dwc_eth_qos_stm32.c >> +++ b/drivers/net/dwc_eth_qos_stm32.c >> @@ -143,34 +143,34 @@ static int eqos_probe_syscfg_stm32(struct >> udevice *dev, >> >> switch (interface_type) { >> case PHY_INTERFACE_MODE_MII: >> + log_debug("PHY_INTERFACE_MODE_MII\n"); >> value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, >> SYSCFG_PMCSETR_ETH_SEL_GMII_MII); >> value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> - log_debug("PHY_INTERFACE_MODE_MII\n"); >> break; >> case PHY_INTERFACE_MODE_GMII: >> + log_debug("PHY_INTERFACE_MODE_GMII\n"); >> value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, >> SYSCFG_PMCSETR_ETH_SEL_GMII_MII); >> if (eth_clk_sel_reg) >> value |= SYSCFG_PMCSETR_ETH_CLK_SEL; >> - log_debug("PHY_INTERFACE_MODE_GMII\n"); >> break; >> case PHY_INTERFACE_MODE_RMII: >> + log_debug("PHY_INTERFACE_MODE_RMII\n"); >> value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, >> SYSCFG_PMCSETR_ETH_SEL_RMII); >> if (eth_ref_clk_sel_reg) >> value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> - log_debug("PHY_INTERFACE_MODE_RMII\n"); >> break; >> case PHY_INTERFACE_MODE_RGMII: >> case PHY_INTERFACE_MODE_RGMII_ID: >> case PHY_INTERFACE_MODE_RGMII_RXID: >> case PHY_INTERFACE_MODE_RGMII_TXID: >> + log_debug("PHY_INTERFACE_MODE_RGMII\n"); >> value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, >> SYSCFG_PMCSETR_ETH_SEL_RGMII); >> if (eth_clk_sel_reg) >> value |= SYSCFG_PMCSETR_ETH_CLK_SEL; >> - log_debug("PHY_INTERFACE_MODE_RGMII\n"); >> break; >> default: >> log_debug("Do not manage %d interface\n", > Reviewed-by: Christophe ROULLIER <christophe.roullier(a)foss.st.com>

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Re: [PATCH 05/11] net: dwc_eth_qos: Use FIELD_PREP for ETH_SEL bitfield
by Christophe ROULLIER 05 Apr '24

05 Apr '24

> On 3/9/24 03:11, Marek Vasut wrote: >> Use FIELD_PREP to configure content of ETH_SEL bitfield in >> SYSCFG_PMCSETR register. No functional change. >> >> Signed-off-by: Marek Vasut <marex(a)denx.de> >> --- >> Cc: Christophe Roullier <christophe.roullier(a)st.com> >> Cc: Joe Hershberger <joe.hershberger(a)ni.com> >> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> >> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> >> Cc: Ramon Fried <rfried.dev(a)gmail.com> >> Cc: u-boot(a)dh-electronics.com >> Cc: uboot-stm32(a)st-md-mailman.stormreply.com >> --- >> drivers/net/dwc_eth_qos_stm32.c | 33 >> ++++++++++++++++----------------- >> 1 file changed, 16 insertions(+), 17 deletions(-) >> >> diff --git a/drivers/net/dwc_eth_qos_stm32.c >> b/drivers/net/dwc_eth_qos_stm32.c index d7ec0c9be36..7545026b158 >> 100644 >> --- a/drivers/net/dwc_eth_qos_stm32.c >> +++ b/drivers/net/dwc_eth_qos_stm32.c >> @@ -26,6 +26,7 @@ >> #include <reset.h> >> #include <syscon.h> >> #include <wait_bit.h> >> +#include <linux/bitfield.h> >> #include <linux/delay.h> >> >> #include "dwc_eth_qos.h" >> @@ -40,9 +41,9 @@ >> #define SYSCFG_PMCSETR_ETH_SELMII BIT(20) >> >> #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) >> -#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0 >> -#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) >> -#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) >> +#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0x0 >> +#define SYSCFG_PMCSETR_ETH_SEL_RGMII 0x1 >> +#define SYSCFG_PMCSETR_ETH_SEL_RMII 0x4 >> >> static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev) { @@ >> -142,35 +143,33 @@ static int eqos_probe_syscfg_stm32(struct udevice >> *dev, >> >> switch (interface_type) { >> case PHY_INTERFACE_MODE_MII: >> - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | >> - SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> + value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, >> + SYSCFG_PMCSETR_ETH_SEL_GMII_MII); >> + value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> log_debug("PHY_INTERFACE_MODE_MII\n"); >> break; >> case PHY_INTERFACE_MODE_GMII: >> + value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, >> + SYSCFG_PMCSETR_ETH_SEL_GMII_MII); >> if (eth_clk_sel_reg) >> - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | >> - SYSCFG_PMCSETR_ETH_CLK_SEL; >> - else >> - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII; >> + value |= SYSCFG_PMCSETR_ETH_CLK_SEL; >> log_debug("PHY_INTERFACE_MODE_GMII\n"); >> break; >> case PHY_INTERFACE_MODE_RMII: >> + value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, >> + SYSCFG_PMCSETR_ETH_SEL_RMII); >> if (eth_ref_clk_sel_reg) >> - value = SYSCFG_PMCSETR_ETH_SEL_RMII | >> - SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> - else >> - value = SYSCFG_PMCSETR_ETH_SEL_RMII; >> + value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> log_debug("PHY_INTERFACE_MODE_RMII\n"); >> break; >> case PHY_INTERFACE_MODE_RGMII: >> case PHY_INTERFACE_MODE_RGMII_ID: >> case PHY_INTERFACE_MODE_RGMII_RXID: >> case PHY_INTERFACE_MODE_RGMII_TXID: >> + value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, >> + SYSCFG_PMCSETR_ETH_SEL_RGMII); >> if (eth_clk_sel_reg) >> - value = SYSCFG_PMCSETR_ETH_SEL_RGMII | >> - SYSCFG_PMCSETR_ETH_CLK_SEL; >> - else >> - value = SYSCFG_PMCSETR_ETH_SEL_RGMII; >> + value |= SYSCFG_PMCSETR_ETH_CLK_SEL; >> log_debug("PHY_INTERFACE_MODE_RGMII\n"); >> break; >> default: > Reviewed-by: Christophe ROULLIER <christophe.roullier(a)foss.st.com> >

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Re: [PATCH 04/11] net: dwc_eth_qos: Scrub ifdeffery
by Christophe ROULLIER 05 Apr '24

05 Apr '24

> On 3/9/24 03:11, Marek Vasut wrote: >> Replace ifdef CONFIG_CLK with if (CONFIG_IS_ENABLED(CLK)) to improve >> code build coverage. Some of the functions printed debug("%s: OK\n", >> __func__); on exit with and without CLK enabled, some did not, make it >> consistent and print nothing if CLK is disabled. >> >> Signed-off-by: Marek Vasut <marex(a)denx.de> >> --- >> Cc: Christophe Roullier <christophe.roullier(a)st.com> >> Cc: Joe Hershberger <joe.hershberger(a)ni.com> >> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> >> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> >> Cc: Ramon Fried <rfried.dev(a)gmail.com> >> Cc: u-boot(a)dh-electronics.com >> Cc: uboot-stm32(a)st-md-mailman.stormreply.com >> --- >> drivers/net/dwc_eth_qos_stm32.c | 25 ++++++++++++------------- >> 1 file changed, 12 insertions(+), 13 deletions(-) >> >> diff --git a/drivers/net/dwc_eth_qos_stm32.c >> b/drivers/net/dwc_eth_qos_stm32.c index 7520a136ed0..d7ec0c9be36 >> 100644 >> --- a/drivers/net/dwc_eth_qos_stm32.c >> +++ b/drivers/net/dwc_eth_qos_stm32.c >> @@ -46,21 +46,22 @@ >> >> static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev) { >> -#ifdef CONFIG_CLK >> - struct eqos_priv *eqos = dev_get_priv(dev); >> + struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev); >> + >> + if (!CONFIG_IS_ENABLED(CLK)) >> + return 0; >> >> return clk_get_rate(&eqos->clk_master_bus); >> -#else >> - return 0; >> -#endif >> } >> >> static int eqos_start_clks_stm32(struct udevice *dev) { -#ifdef >> CONFIG_CLK >> - struct eqos_priv *eqos = dev_get_priv(dev); >> + struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev); >> int ret; >> >> + if (!CONFIG_IS_ENABLED(CLK)) >> + return 0; >> + >> debug("%s(dev=%p):\n", __func__, dev); >> >> ret = clk_enable(&eqos->clk_master_bus); >> @@ -89,12 +90,10 @@ static int eqos_start_clks_stm32(struct udevice *dev) >> } >> eqos->clk_ck_enabled = true; >> } >> -#endif >> >> debug("%s: OK\n", __func__); >> return 0; >> >> -#ifdef CONFIG_CLK >> err_disable_clk_tx: >> clk_disable(&eqos->clk_tx); >> err_disable_clk_rx: >> @@ -104,20 +103,20 @@ err_disable_clk_master_bus: >> err: >> debug("%s: FAILED: %d\n", __func__, ret); >> return ret; >> -#endif >> } >> >> static int eqos_stop_clks_stm32(struct udevice *dev) { -#ifdef >> CONFIG_CLK >> - struct eqos_priv *eqos = dev_get_priv(dev); >> + struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev); >> + >> + if (!CONFIG_IS_ENABLED(CLK)) >> + return 0; >> >> debug("%s(dev=%p):\n", __func__, dev); >> >> clk_disable(&eqos->clk_tx); >> clk_disable(&eqos->clk_rx); >> clk_disable(&eqos->clk_master_bus); >> -#endif >> >> debug("%s: OK\n", __func__); >> return 0; > > Reviewed-by: Christophe ROULLIER <christophe.roullier(a)foss.st.com> >

1 0

Re: [PATCH 03/11] net: dwc_eth_qos: Fold board_interface_eth_init into STM32 glue code
by Christophe ROULLIER 05 Apr '24

05 Apr '24

> On 3/9/24 03:11, Marek Vasut wrote: >> Move board_interface_eth_init() into eqos_probe_syscfg_stm32() in >> STM32 driver glue code. The eqos_probe_syscfg_stm32() parses STM32 >> specific DT properties of this MAC and configures SYSCFG registers >> accordingly, there is nothing board specific happening in this >> function, move it into generic driver code instead. Drop the now unused duplicates from board files. >> >> Signed-off-by: Marek Vasut <marex(a)denx.de> >> --- >> Cc: Christophe Roullier <christophe.roullier(a)st.com> >> Cc: Joe Hershberger <joe.hershberger(a)ni.com> >> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> >> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> >> Cc: Ramon Fried <rfried.dev(a)gmail.com> >> Cc: u-boot(a)dh-electronics.com >> Cc: uboot-stm32(a)st-md-mailman.stormreply.com >> --- >> board/dhelectronics/dh_stm32mp1/board.c | 82 ----------------------- >> board/st/stm32mp1/stm32mp1.c | 82 ----------------------- >> drivers/net/dwc_eth_qos_stm32.c | 86 ++++++++++++++++++++++++- >> 3 files changed, 84 insertions(+), 166 deletions(-) >> >> diff --git a/board/dhelectronics/dh_stm32mp1/board.c >> b/board/dhelectronics/dh_stm32mp1/board.c >> index d1f662d9701..f179c857116 100644 >> --- a/board/dhelectronics/dh_stm32mp1/board.c >> +++ b/board/dhelectronics/dh_stm32mp1/board.c >> @@ -48,12 +48,10 @@ >> >> /* SYSCFG registers */ >> #define SYSCFG_BOOTR 0x00 >> -#define SYSCFG_PMCSETR 0x04 >> #define SYSCFG_IOCTRLSETR 0x18 >> #define SYSCFG_ICNR 0x1C >> #define SYSCFG_CMPCR 0x20 >> #define SYSCFG_CMPENSETR 0x24 >> -#define SYSCFG_PMCCLRR 0x44 >> >> #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0) >> #define SYSCFG_BOOTR_BOOTPD_SHIFT 4 >> @@ -69,16 +67,6 @@ >> >> #define SYSCFG_CMPENSETR_MPU_EN BIT(0) >> >> -#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16) >> -#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17) >> - >> -#define SYSCFG_PMCSETR_ETH_SELMII BIT(20) >> - >> -#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) >> -#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0 >> -#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) >> -#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) >> - >> #define KS_CCR 0x08 >> #define KS_CCR_EEPROM BIT(9) >> #define KS_BE0 BIT(12) >> @@ -679,76 +667,6 @@ void board_quiesce_devices(void) #endif } >> >> -/* eth init function : weak called in eqos driver */ -int >> board_interface_eth_init(struct udevice *dev, >> - phy_interface_t interface_type) >> -{ >> - u8 *syscfg; >> - u32 value; >> - bool eth_clk_sel_reg = false; >> - bool eth_ref_clk_sel_reg = false; >> - >> - /* Gigabit Ethernet 125MHz clock selection. */ >> - eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel"); >> - >> - /* Ethernet 50Mhz RMII clock selection */ >> - eth_ref_clk_sel_reg = >> - dev_read_bool(dev, "st,eth-ref-clk-sel"); >> - >> - syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); >> - >> - if (!syscfg) >> - return -ENODEV; >> - >> - switch (interface_type) { >> - case PHY_INTERFACE_MODE_MII: >> - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | >> - SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> - debug("%s: PHY_INTERFACE_MODE_MII\n", __func__); >> - break; >> - case PHY_INTERFACE_MODE_GMII: >> - if (eth_clk_sel_reg) >> - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | >> - SYSCFG_PMCSETR_ETH_CLK_SEL; >> - else >> - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII; >> - debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__); >> - break; >> - case PHY_INTERFACE_MODE_RMII: >> - if (eth_ref_clk_sel_reg) >> - value = SYSCFG_PMCSETR_ETH_SEL_RMII | >> - SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> - else >> - value = SYSCFG_PMCSETR_ETH_SEL_RMII; >> - debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__); >> - break; >> - case PHY_INTERFACE_MODE_RGMII: >> - case PHY_INTERFACE_MODE_RGMII_ID: >> - case PHY_INTERFACE_MODE_RGMII_RXID: >> - case PHY_INTERFACE_MODE_RGMII_TXID: >> - if (eth_clk_sel_reg) >> - value = SYSCFG_PMCSETR_ETH_SEL_RGMII | >> - SYSCFG_PMCSETR_ETH_CLK_SEL; >> - else >> - value = SYSCFG_PMCSETR_ETH_SEL_RGMII; >> - debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__); >> - break; >> - default: >> - debug("%s: Do not manage %d interface\n", >> - __func__, interface_type); >> - /* Do not manage others interfaces */ >> - return -EINVAL; >> - } >> - >> - /* clear and set ETH configuration bits */ >> - writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII | >> - SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL, >> - syscfg + SYSCFG_PMCCLRR); >> - writel(value, syscfg + SYSCFG_PMCSETR); >> - >> - return 0; >> -} >> - >> #if defined(CONFIG_OF_BOARD_SETUP) >> int ft_board_setup(void *blob, struct bd_info *bd) { diff --git >> a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index >> a17c314daeb..f284b0dfd28 100644 >> --- a/board/st/stm32mp1/stm32mp1.c >> +++ b/board/st/stm32mp1/stm32mp1.c >> @@ -52,12 +52,10 @@ >> >> /* SYSCFG registers */ >> #define SYSCFG_BOOTR 0x00 >> -#define SYSCFG_PMCSETR 0x04 >> #define SYSCFG_IOCTRLSETR 0x18 >> #define SYSCFG_ICNR 0x1C >> #define SYSCFG_CMPCR 0x20 >> #define SYSCFG_CMPENSETR 0x24 >> -#define SYSCFG_PMCCLRR 0x44 >> >> #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0) >> #define SYSCFG_BOOTR_BOOTPD_SHIFT 4 >> @@ -73,16 +71,6 @@ >> >> #define SYSCFG_CMPENSETR_MPU_EN BIT(0) >> >> -#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16) >> -#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17) >> - >> -#define SYSCFG_PMCSETR_ETH_SELMII BIT(20) >> - >> -#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) >> -#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0 >> -#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) >> -#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) >> - >> #define USB_LOW_THRESHOLD_UV 200000 >> #define USB_WARNING_LOW_THRESHOLD_UV 660000 >> #define USB_START_LOW_THRESHOLD_UV 1230000 >> @@ -742,76 +730,6 @@ void board_quiesce_devices(void) >> setup_led(LEDST_OFF); >> } >> >> -/* eth init function : weak called in eqos driver */ -int >> board_interface_eth_init(struct udevice *dev, >> - phy_interface_t interface_type) >> -{ >> - u8 *syscfg; >> - u32 value; >> - bool eth_clk_sel_reg = false; >> - bool eth_ref_clk_sel_reg = false; >> - >> - /* Gigabit Ethernet 125MHz clock selection. */ >> - eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel"); >> - >> - /* Ethernet 50Mhz RMII clock selection */ >> - eth_ref_clk_sel_reg = >> - dev_read_bool(dev, "st,eth-ref-clk-sel"); >> - >> - syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); >> - >> - if (!syscfg) >> - return -ENODEV; >> - >> - switch (interface_type) { >> - case PHY_INTERFACE_MODE_MII: >> - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | >> - SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> - log_debug("PHY_INTERFACE_MODE_MII\n"); >> - break; >> - case PHY_INTERFACE_MODE_GMII: >> - if (eth_clk_sel_reg) >> - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | >> - SYSCFG_PMCSETR_ETH_CLK_SEL; >> - else >> - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII; >> - log_debug("PHY_INTERFACE_MODE_GMII\n"); >> - break; >> - case PHY_INTERFACE_MODE_RMII: >> - if (eth_ref_clk_sel_reg) >> - value = SYSCFG_PMCSETR_ETH_SEL_RMII | >> - SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> - else >> - value = SYSCFG_PMCSETR_ETH_SEL_RMII; >> - log_debug("PHY_INTERFACE_MODE_RMII\n"); >> - break; >> - case PHY_INTERFACE_MODE_RGMII: >> - case PHY_INTERFACE_MODE_RGMII_ID: >> - case PHY_INTERFACE_MODE_RGMII_RXID: >> - case PHY_INTERFACE_MODE_RGMII_TXID: >> - if (eth_clk_sel_reg) >> - value = SYSCFG_PMCSETR_ETH_SEL_RGMII | >> - SYSCFG_PMCSETR_ETH_CLK_SEL; >> - else >> - value = SYSCFG_PMCSETR_ETH_SEL_RGMII; >> - log_debug("PHY_INTERFACE_MODE_RGMII\n"); >> - break; >> - default: >> - log_debug("Do not manage %d interface\n", >> - interface_type); >> - /* Do not manage others interfaces */ >> - return -EINVAL; >> - } >> - >> - /* clear and set ETH configuration bits */ >> - writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII | >> - SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL, >> - syscfg + SYSCFG_PMCCLRR); >> - writel(value, syscfg + SYSCFG_PMCSETR); >> - >> - return 0; >> -} >> - >> enum env_location env_get_location(enum env_operation op, int prio) >> { >> u32 bootmode = get_bootmode(); >> diff --git a/drivers/net/dwc_eth_qos_stm32.c >> b/drivers/net/dwc_eth_qos_stm32.c index fd29a604987..7520a136ed0 >> 100644 >> --- a/drivers/net/dwc_eth_qos_stm32.c >> +++ b/drivers/net/dwc_eth_qos_stm32.c >> @@ -24,11 +24,26 @@ >> #include <netdev.h> >> #include <phy.h> >> #include <reset.h> >> +#include <syscon.h> >> #include <wait_bit.h> >> #include <linux/delay.h> >> >> #include "dwc_eth_qos.h" >> >> +/* SYSCFG registers */ >> +#define SYSCFG_PMCSETR 0x04 >> +#define SYSCFG_PMCCLRR 0x44 >> + >> +#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16) >> +#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17) >> + >> +#define SYSCFG_PMCSETR_ETH_SELMII BIT(20) >> + >> +#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) >> +#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0 >> +#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) >> +#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) >> + >> static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev) { >> #ifdef CONFIG_CLK @@ -108,11 +123,78 @@ static int >> eqos_stop_clks_stm32(struct udevice *dev) >> return 0; >> } >> >> +static int eqos_probe_syscfg_stm32(struct udevice *dev, >> + phy_interface_t interface_type) { >> + bool eth_ref_clk_sel_reg = false; >> + bool eth_clk_sel_reg = false; >> + u8 *syscfg; >> + u32 value; >> + >> + /* Gigabit Ethernet 125MHz clock selection. */ >> + eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel"); >> + >> + /* Ethernet 50Mhz RMII clock selection */ >> + eth_ref_clk_sel_reg = dev_read_bool(dev, "st,eth-ref-clk-sel"); >> + >> + syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); >> + if (!syscfg) >> + return -ENODEV; >> + >> + switch (interface_type) { >> + case PHY_INTERFACE_MODE_MII: >> + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | >> + SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> + log_debug("PHY_INTERFACE_MODE_MII\n"); >> + break; >> + case PHY_INTERFACE_MODE_GMII: >> + if (eth_clk_sel_reg) >> + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | >> + SYSCFG_PMCSETR_ETH_CLK_SEL; >> + else >> + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII; >> + log_debug("PHY_INTERFACE_MODE_GMII\n"); >> + break; >> + case PHY_INTERFACE_MODE_RMII: >> + if (eth_ref_clk_sel_reg) >> + value = SYSCFG_PMCSETR_ETH_SEL_RMII | >> + SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> + else >> + value = SYSCFG_PMCSETR_ETH_SEL_RMII; >> + log_debug("PHY_INTERFACE_MODE_RMII\n"); >> + break; >> + case PHY_INTERFACE_MODE_RGMII: >> + case PHY_INTERFACE_MODE_RGMII_ID: >> + case PHY_INTERFACE_MODE_RGMII_RXID: >> + case PHY_INTERFACE_MODE_RGMII_TXID: >> + if (eth_clk_sel_reg) >> + value = SYSCFG_PMCSETR_ETH_SEL_RGMII | >> + SYSCFG_PMCSETR_ETH_CLK_SEL; >> + else >> + value = SYSCFG_PMCSETR_ETH_SEL_RGMII; >> + log_debug("PHY_INTERFACE_MODE_RGMII\n"); >> + break; >> + default: >> + log_debug("Do not manage %d interface\n", >> + interface_type); >> + /* Do not manage others interfaces */ >> + return -EINVAL; >> + } >> + >> + /* clear and set ETH configuration bits */ >> + writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII | >> + SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL, >> + syscfg + SYSCFG_PMCCLRR); >> + writel(value, syscfg + SYSCFG_PMCSETR); >> + >> + return 0; >> +} >> + >> static int eqos_probe_resources_stm32(struct udevice *dev) { >> struct eqos_priv *eqos = dev_get_priv(dev); >> - int ret; >> phy_interface_t interface; >> + int ret; >> >> debug("%s(dev=%p):\n", __func__, dev); >> >> @@ -123,7 +205,7 @@ static int eqos_probe_resources_stm32(struct udevice *dev) >> return -EINVAL; >> } >> >> - ret = board_interface_eth_init(dev, interface); >> + ret = eqos_probe_syscfg_stm32(dev, interface); >> if (ret) >> return -EINVAL; >> > Reviewed-by: Christophe Roullier <christophe.roullier(a)foss.st.com> >

1 0

Re: [PATCH 03/11] net: dwc_eth_qos: Fold board_interface_eth_init into STM32 glue code
by Christophe ROULLIER 05 Apr '24

05 Apr '24

> On 3/9/24 03:11, Marek Vasut wrote: >> Move board_interface_eth_init() into eqos_probe_syscfg_stm32() in >> STM32 driver glue code. The eqos_probe_syscfg_stm32() parses STM32 >> specific DT properties of this MAC and configures SYSCFG registers >> accordingly, there is nothing board specific happening in this >> function, move it into generic driver code instead. Drop the now unused duplicates from board files. >> >> Signed-off-by: Marek Vasut <marex(a)denx.de> >> --- >> Cc: Christophe Roullier <christophe.roullier(a)st.com> >> Cc: Joe Hershberger <joe.hershberger(a)ni.com> >> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> >> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> >> Cc: Ramon Fried <rfried.dev(a)gmail.com> >> Cc: u-boot(a)dh-electronics.com >> Cc: uboot-stm32(a)st-md-mailman.stormreply.com >> --- >> board/dhelectronics/dh_stm32mp1/board.c | 82 ----------------------- >> board/st/stm32mp1/stm32mp1.c | 82 ----------------------- >> drivers/net/dwc_eth_qos_stm32.c | 86 ++++++++++++++++++++++++- >> 3 files changed, 84 insertions(+), 166 deletions(-) >> >> diff --git a/board/dhelectronics/dh_stm32mp1/board.c >> b/board/dhelectronics/dh_stm32mp1/board.c >> index d1f662d9701..f179c857116 100644 >> --- a/board/dhelectronics/dh_stm32mp1/board.c >> +++ b/board/dhelectronics/dh_stm32mp1/board.c >> @@ -48,12 +48,10 @@ >> >> /* SYSCFG registers */ >> #define SYSCFG_BOOTR 0x00 >> -#define SYSCFG_PMCSETR 0x04 >> #define SYSCFG_IOCTRLSETR 0x18 >> #define SYSCFG_ICNR 0x1C >> #define SYSCFG_CMPCR 0x20 >> #define SYSCFG_CMPENSETR 0x24 >> -#define SYSCFG_PMCCLRR 0x44 >> >> #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0) >> #define SYSCFG_BOOTR_BOOTPD_SHIFT 4 >> @@ -69,16 +67,6 @@ >> >> #define SYSCFG_CMPENSETR_MPU_EN BIT(0) >> >> -#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16) >> -#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17) >> - >> -#define SYSCFG_PMCSETR_ETH_SELMII BIT(20) >> - >> -#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) >> -#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0 >> -#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) >> -#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) >> - >> #define KS_CCR 0x08 >> #define KS_CCR_EEPROM BIT(9) >> #define KS_BE0 BIT(12) >> @@ -679,76 +667,6 @@ void board_quiesce_devices(void) #endif } >> >> -/* eth init function : weak called in eqos driver */ -int >> board_interface_eth_init(struct udevice *dev, >> - phy_interface_t interface_type) >> -{ >> - u8 *syscfg; >> - u32 value; >> - bool eth_clk_sel_reg = false; >> - bool eth_ref_clk_sel_reg = false; >> - >> - /* Gigabit Ethernet 125MHz clock selection. */ >> - eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel"); >> - >> - /* Ethernet 50Mhz RMII clock selection */ >> - eth_ref_clk_sel_reg = >> - dev_read_bool(dev, "st,eth-ref-clk-sel"); >> - >> - syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); >> - >> - if (!syscfg) >> - return -ENODEV; >> - >> - switch (interface_type) { >> - case PHY_INTERFACE_MODE_MII: >> - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | >> - SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> - debug("%s: PHY_INTERFACE_MODE_MII\n", __func__); >> - break; >> - case PHY_INTERFACE_MODE_GMII: >> - if (eth_clk_sel_reg) >> - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | >> - SYSCFG_PMCSETR_ETH_CLK_SEL; >> - else >> - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII; >> - debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__); >> - break; >> - case PHY_INTERFACE_MODE_RMII: >> - if (eth_ref_clk_sel_reg) >> - value = SYSCFG_PMCSETR_ETH_SEL_RMII | >> - SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> - else >> - value = SYSCFG_PMCSETR_ETH_SEL_RMII; >> - debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__); >> - break; >> - case PHY_INTERFACE_MODE_RGMII: >> - case PHY_INTERFACE_MODE_RGMII_ID: >> - case PHY_INTERFACE_MODE_RGMII_RXID: >> - case PHY_INTERFACE_MODE_RGMII_TXID: >> - if (eth_clk_sel_reg) >> - value = SYSCFG_PMCSETR_ETH_SEL_RGMII | >> - SYSCFG_PMCSETR_ETH_CLK_SEL; >> - else >> - value = SYSCFG_PMCSETR_ETH_SEL_RGMII; >> - debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__); >> - break; >> - default: >> - debug("%s: Do not manage %d interface\n", >> - __func__, interface_type); >> - /* Do not manage others interfaces */ >> - return -EINVAL; >> - } >> - >> - /* clear and set ETH configuration bits */ >> - writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII | >> - SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL, >> - syscfg + SYSCFG_PMCCLRR); >> - writel(value, syscfg + SYSCFG_PMCSETR); >> - >> - return 0; >> -} >> - >> #if defined(CONFIG_OF_BOARD_SETUP) >> int ft_board_setup(void *blob, struct bd_info *bd) { diff --git >> a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index >> a17c314daeb..f284b0dfd28 100644 >> --- a/board/st/stm32mp1/stm32mp1.c >> +++ b/board/st/stm32mp1/stm32mp1.c >> @@ -52,12 +52,10 @@ >> >> /* SYSCFG registers */ >> #define SYSCFG_BOOTR 0x00 >> -#define SYSCFG_PMCSETR 0x04 >> #define SYSCFG_IOCTRLSETR 0x18 >> #define SYSCFG_ICNR 0x1C >> #define SYSCFG_CMPCR 0x20 >> #define SYSCFG_CMPENSETR 0x24 >> -#define SYSCFG_PMCCLRR 0x44 >> >> #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0) >> #define SYSCFG_BOOTR_BOOTPD_SHIFT 4 >> @@ -73,16 +71,6 @@ >> >> #define SYSCFG_CMPENSETR_MPU_EN BIT(0) >> >> -#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16) >> -#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17) >> - >> -#define SYSCFG_PMCSETR_ETH_SELMII BIT(20) >> - >> -#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) >> -#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0 >> -#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) >> -#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) >> - >> #define USB_LOW_THRESHOLD_UV 200000 >> #define USB_WARNING_LOW_THRESHOLD_UV 660000 >> #define USB_START_LOW_THRESHOLD_UV 1230000 >> @@ -742,76 +730,6 @@ void board_quiesce_devices(void) >> setup_led(LEDST_OFF); >> } >> >> -/* eth init function : weak called in eqos driver */ -int >> board_interface_eth_init(struct udevice *dev, >> - phy_interface_t interface_type) >> -{ >> - u8 *syscfg; >> - u32 value; >> - bool eth_clk_sel_reg = false; >> - bool eth_ref_clk_sel_reg = false; >> - >> - /* Gigabit Ethernet 125MHz clock selection. */ >> - eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel"); >> - >> - /* Ethernet 50Mhz RMII clock selection */ >> - eth_ref_clk_sel_reg = >> - dev_read_bool(dev, "st,eth-ref-clk-sel"); >> - >> - syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); >> - >> - if (!syscfg) >> - return -ENODEV; >> - >> - switch (interface_type) { >> - case PHY_INTERFACE_MODE_MII: >> - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | >> - SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> - log_debug("PHY_INTERFACE_MODE_MII\n"); >> - break; >> - case PHY_INTERFACE_MODE_GMII: >> - if (eth_clk_sel_reg) >> - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | >> - SYSCFG_PMCSETR_ETH_CLK_SEL; >> - else >> - value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII; >> - log_debug("PHY_INTERFACE_MODE_GMII\n"); >> - break; >> - case PHY_INTERFACE_MODE_RMII: >> - if (eth_ref_clk_sel_reg) >> - value = SYSCFG_PMCSETR_ETH_SEL_RMII | >> - SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> - else >> - value = SYSCFG_PMCSETR_ETH_SEL_RMII; >> - log_debug("PHY_INTERFACE_MODE_RMII\n"); >> - break; >> - case PHY_INTERFACE_MODE_RGMII: >> - case PHY_INTERFACE_MODE_RGMII_ID: >> - case PHY_INTERFACE_MODE_RGMII_RXID: >> - case PHY_INTERFACE_MODE_RGMII_TXID: >> - if (eth_clk_sel_reg) >> - value = SYSCFG_PMCSETR_ETH_SEL_RGMII | >> - SYSCFG_PMCSETR_ETH_CLK_SEL; >> - else >> - value = SYSCFG_PMCSETR_ETH_SEL_RGMII; >> - log_debug("PHY_INTERFACE_MODE_RGMII\n"); >> - break; >> - default: >> - log_debug("Do not manage %d interface\n", >> - interface_type); >> - /* Do not manage others interfaces */ >> - return -EINVAL; >> - } >> - >> - /* clear and set ETH configuration bits */ >> - writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII | >> - SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL, >> - syscfg + SYSCFG_PMCCLRR); >> - writel(value, syscfg + SYSCFG_PMCSETR); >> - >> - return 0; >> -} >> - >> enum env_location env_get_location(enum env_operation op, int prio) >> { >> u32 bootmode = get_bootmode(); >> diff --git a/drivers/net/dwc_eth_qos_stm32.c >> b/drivers/net/dwc_eth_qos_stm32.c index fd29a604987..7520a136ed0 >> 100644 >> --- a/drivers/net/dwc_eth_qos_stm32.c >> +++ b/drivers/net/dwc_eth_qos_stm32.c >> @@ -24,11 +24,26 @@ >> #include <netdev.h> >> #include <phy.h> >> #include <reset.h> >> +#include <syscon.h> >> #include <wait_bit.h> >> #include <linux/delay.h> >> >> #include "dwc_eth_qos.h" >> >> +/* SYSCFG registers */ >> +#define SYSCFG_PMCSETR 0x04 >> +#define SYSCFG_PMCCLRR 0x44 >> + >> +#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16) >> +#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17) >> + >> +#define SYSCFG_PMCSETR_ETH_SELMII BIT(20) >> + >> +#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) >> +#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0 >> +#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) >> +#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) >> + >> static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev) { >> #ifdef CONFIG_CLK @@ -108,11 +123,78 @@ static int >> eqos_stop_clks_stm32(struct udevice *dev) >> return 0; >> } >> >> +static int eqos_probe_syscfg_stm32(struct udevice *dev, >> + phy_interface_t interface_type) { >> + bool eth_ref_clk_sel_reg = false; >> + bool eth_clk_sel_reg = false; >> + u8 *syscfg; >> + u32 value; >> + >> + /* Gigabit Ethernet 125MHz clock selection. */ >> + eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel"); >> + >> + /* Ethernet 50Mhz RMII clock selection */ >> + eth_ref_clk_sel_reg = dev_read_bool(dev, "st,eth-ref-clk-sel"); >> + >> + syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); >> + if (!syscfg) >> + return -ENODEV; >> + >> + switch (interface_type) { >> + case PHY_INTERFACE_MODE_MII: >> + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | >> + SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> + log_debug("PHY_INTERFACE_MODE_MII\n"); >> + break; >> + case PHY_INTERFACE_MODE_GMII: >> + if (eth_clk_sel_reg) >> + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII | >> + SYSCFG_PMCSETR_ETH_CLK_SEL; >> + else >> + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII; >> + log_debug("PHY_INTERFACE_MODE_GMII\n"); >> + break; >> + case PHY_INTERFACE_MODE_RMII: >> + if (eth_ref_clk_sel_reg) >> + value = SYSCFG_PMCSETR_ETH_SEL_RMII | >> + SYSCFG_PMCSETR_ETH_REF_CLK_SEL; >> + else >> + value = SYSCFG_PMCSETR_ETH_SEL_RMII; >> + log_debug("PHY_INTERFACE_MODE_RMII\n"); >> + break; >> + case PHY_INTERFACE_MODE_RGMII: >> + case PHY_INTERFACE_MODE_RGMII_ID: >> + case PHY_INTERFACE_MODE_RGMII_RXID: >> + case PHY_INTERFACE_MODE_RGMII_TXID: >> + if (eth_clk_sel_reg) >> + value = SYSCFG_PMCSETR_ETH_SEL_RGMII | >> + SYSCFG_PMCSETR_ETH_CLK_SEL; >> + else >> + value = SYSCFG_PMCSETR_ETH_SEL_RGMII; >> + log_debug("PHY_INTERFACE_MODE_RGMII\n"); >> + break; >> + default: >> + log_debug("Do not manage %d interface\n", >> + interface_type); >> + /* Do not manage others interfaces */ >> + return -EINVAL; >> + } >> + >> + /* clear and set ETH configuration bits */ >> + writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII | >> + SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL, >> + syscfg + SYSCFG_PMCCLRR); >> + writel(value, syscfg + SYSCFG_PMCSETR); >> + >> + return 0; >> +} >> + >> static int eqos_probe_resources_stm32(struct udevice *dev) { >> struct eqos_priv *eqos = dev_get_priv(dev); >> - int ret; >> phy_interface_t interface; >> + int ret; >> >> debug("%s(dev=%p):\n", __func__, dev); >> >> @@ -123,7 +205,7 @@ static int eqos_probe_resources_stm32(struct udevice *dev) >> return -EINVAL; >> } >> >> - ret = board_interface_eth_init(dev, interface); >> + ret = eqos_probe_syscfg_stm32(dev, interface); >> if (ret) >> return -EINVAL; >> > Reviewed-by: Christophe Roullier <christophe.roullier(a)foss.st.com> >

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Re: [PATCH 02/11] net: dwc_eth_qos: Rename eqos_stm32_config to eqos_stm32mp15_config
by Christophe ROULLIER 05 Apr '24

05 Apr '24

> On 3/9/24 03:11, Marek Vasut wrote: >> The current glue code is specific to STM32MP15xx, the upcoming >> STM32MP13xx will introduce another entry specific to the STM32MP13xx. >> Rename the current entry to eqos_stm32mp15_config in preparation for >> STM32MP13xx addition. No functional change. >> >> Signed-off-by: Marek Vasut<marex(a)denx.de> >> --- >> Cc: Christophe Roullier<christophe.roullier(a)st.com> >> Cc: Joe Hershberger<joe.hershberger(a)ni.com> >> Cc: Patrice Chotard<patrice.chotard(a)foss.st.com> >> Cc: Patrick Delaunay<patrick.delaunay(a)foss.st.com> >> Cc: Ramon Fried<rfried.dev(a)gmail.com> >> Cc:u-boot@dh-electronics.com >> Cc:uboot-stm32@st-md-mailman.stormreply.com >> --- >> drivers/net/dwc_eth_qos.c | 2 +- >> drivers/net/dwc_eth_qos.h | 2 +- >> drivers/net/dwc_eth_qos_stm32.c | 2 +- >> 3 files changed, 3 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c >> index 533c2bf070b..203bfc0848c 100644 >> --- a/drivers/net/dwc_eth_qos.c >> +++ b/drivers/net/dwc_eth_qos.c >> @@ -1507,7 +1507,7 @@ static const struct udevice_id eqos_ids[] = { >> #if IS_ENABLED(CONFIG_DWC_ETH_QOS_STM32) >> { >> .compatible = "st,stm32mp1-dwmac", >> - .data = (ulong)&eqos_stm32_config >> + .data = (ulong)&eqos_stm32mp15_config >> }, >> #endif >> #if IS_ENABLED(CONFIG_DWC_ETH_QOS_IMX) >> diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h >> index a6087f191ab..bafd0d339fb 100644 >> --- a/drivers/net/dwc_eth_qos.h >> +++ b/drivers/net/dwc_eth_qos.h >> @@ -290,5 +290,5 @@ int eqos_null_ops(struct udevice *dev); extern >> struct eqos_config eqos_imx_config; extern struct eqos_config >> eqos_rockchip_config; extern struct eqos_config eqos_qcom_config; >> -extern struct eqos_config eqos_stm32_config; >> +extern struct eqos_config eqos_stm32mp15_config; >> extern struct eqos_config eqos_jh7110_config; diff --git >> a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c >> index cfda757133e..fd29a604987 100644 >> --- a/drivers/net/dwc_eth_qos_stm32.c >> +++ b/drivers/net/dwc_eth_qos_stm32.c >> @@ -184,7 +184,7 @@ static struct eqos_ops eqos_stm32_ops = { >> .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32 }; >> >> -struct eqos_config __maybe_unused eqos_stm32_config = { >> +struct eqos_config __maybe_unused eqos_stm32mp15_config = { >> .reg_access_always_ok = false, >> .mdio_wait = 10000, >> .swr_wait = 50, > Reviewed-by: Christophe Roullier<christophe.roullier(a)foss.st.com> >

1 0

[RFC PATCH 00/15] Add basic U-Boot Support for J722S-EVM
by Jayesh Choudhary 05 Apr '24

05 Apr '24

Hello there, This series add the U-Boot support for our new platform of K3-SOC family - J722S-EVM which is a superset of AM62P. It shares the same memory map and thus the nodes are being reused from AM62P includes instead of duplicating the definitions. Some highlights of J722S SoC (in addition to AM62P SoC features) are: - Two Cortex-R5F for Functional Safety or general-purpose usage and two C7x floating point vector DSP with Matrix Multiply Accelerator for deep learning. - Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC). - 7xUARTs, 3xSPI, 5xI2C, 2xUSB2, 2xCAN-FD, 3xMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 5xMcASP for audio, 4xCSI-RX for Camera, 1 PCIe Gen3 controller, USB3.0 eCAP/eQEP, ePWM, among other peripherals. TRM: <https://www.ti.com/lit/zip/sprujb3> Schematics: <https://www.ti.com/lit/zip/sprr495> Bootlog test: <https://gist.github.com/Jayesh2000/3a662b380e64aaa227256dbbcef3fe0d> NOTE: This series depends on the latest dts pull form upstream that will add the dts changes for J722S-EVM. So the first patch adds the relavent dts updates which is *NOT SUPPOSED TO BE MERGED* Jayesh Choudhary (15): DO-NOT-MERGE: dts: upstream: src: Necessary pulls from upstream dts arm: mach-k3: Sort CONFIG_SOC* and K3_SOC_ID entries soc: ti: k3-socinfo: Fix SOC JTAG entry order soc: add info to identify the J722S SoC family clk: ti: clk-k3: use IS_ENABLED macro and fix the clock-data order power: domain: ti: Fix the order for platform data entries arm: mach-k3: r5: Makefile: Fix the order for entries arm: mach-k3: j722s: introduce clock and device files for wkup spl ram: k3-ddrss: Enable the am62ax's DDR controller for J722S arch: mach-k3: Introduce basic files to support J722S SoC family board: ti: Introduce basic board files for the J722S family firmware: ti_sci_static_data: Add static DMA channel arm: dts: Introduce J722S U-Boot dts files configs: introduce configs needed for the J722S doc: board: ti: Add J722S-EVM documentation arch/arm/dts/Makefile | 2 + arch/arm/dts/k3-j722s-binman.dtsi | 171 + arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi | 2795 +++++++++++++++++ arch/arm/dts/k3-j722s-evm-u-boot.dtsi | 36 + arch/arm/dts/k3-j722s-r5-evm.dts | 82 + arch/arm/mach-k3/Kconfig | 7 +- arch/arm/mach-k3/Makefile | 1 + arch/arm/mach-k3/include/mach/hardware.h | 43 +- .../arm/mach-k3/include/mach/j722s_hardware.h | 83 + arch/arm/mach-k3/include/mach/j722s_spl.h | 49 + arch/arm/mach-k3/include/mach/spl.h | 4 + arch/arm/mach-k3/j722s/Kconfig | 32 + arch/arm/mach-k3/j722s_init.c | 276 ++ arch/arm/mach-k3/r5/Makefile | 7 +- arch/arm/mach-k3/r5/j722s/Makefile | 6 + arch/arm/mach-k3/r5/j722s/clk-data.c | 312 ++ arch/arm/mach-k3/r5/j722s/dev-data.c | 69 + board/ti/j722s/Kconfig | 26 + board/ti/j722s/MAINTAINERS | 9 + board/ti/j722s/Makefile | 7 + board/ti/j722s/board-cfg.yaml | 36 + board/ti/j722s/evm.c | 29 + board/ti/j722s/j722s.env | 15 + board/ti/j722s/pm-cfg.yaml | 12 + board/ti/j722s/rm-cfg.yaml | 1119 +++++++ board/ti/j722s/sec-cfg.yaml | 379 +++ board/ti/j722s/tifs-rm-cfg.yaml | 981 ++++++ configs/j722s_evm_a53_defconfig | 177 ++ configs/j722s_evm_r5_defconfig | 137 + doc/board/ti/j722s_evm.rst | 262 ++ doc/board/ti/k3.rst | 1 + drivers/clk/ti/clk-k3.c | 41 +- drivers/firmware/ti_sci_static_data.h | 2 +- drivers/power/domain/ti-power-domain.c | 36 +- drivers/ram/Kconfig | 2 +- drivers/soc/soc_ti_k3.c | 29 +- dts/upstream/Bindings/arm/ti/k3.yaml | 6 + dts/upstream/src/arm64/ti/k3-j722s-evm.dts | 383 +++ dts/upstream/src/arm64/ti/k3-j722s.dtsi | 89 + dts/upstream/src/arm64/ti/k3-pinctrl.h | 3 + include/configs/j722s_evm.h | 14 + include/k3-clk.h | 1 + include/k3-dev.h | 1 + 43 files changed, 7703 insertions(+), 69 deletions(-) create mode 100644 arch/arm/dts/k3-j722s-binman.dtsi create mode 100644 arch/arm/dts/k3-j722s-ddr-lp4-50-3733.dtsi create mode 100644 arch/arm/dts/k3-j722s-evm-u-boot.dtsi create mode 100644 arch/arm/dts/k3-j722s-r5-evm.dts create mode 100644 arch/arm/mach-k3/include/mach/j722s_hardware.h create mode 100644 arch/arm/mach-k3/include/mach/j722s_spl.h create mode 100644 arch/arm/mach-k3/j722s/Kconfig create mode 100644 arch/arm/mach-k3/j722s_init.c create mode 100644 arch/arm/mach-k3/r5/j722s/Makefile create mode 100644 arch/arm/mach-k3/r5/j722s/clk-data.c create mode 100644 arch/arm/mach-k3/r5/j722s/dev-data.c create mode 100644 board/ti/j722s/Kconfig create mode 100644 board/ti/j722s/MAINTAINERS create mode 100644 board/ti/j722s/Makefile create mode 100644 board/ti/j722s/board-cfg.yaml create mode 100644 board/ti/j722s/evm.c create mode 100644 board/ti/j722s/j722s.env create mode 100644 board/ti/j722s/pm-cfg.yaml create mode 100644 board/ti/j722s/rm-cfg.yaml create mode 100644 board/ti/j722s/sec-cfg.yaml create mode 100644 board/ti/j722s/tifs-rm-cfg.yaml create mode 100644 configs/j722s_evm_a53_defconfig create mode 100644 configs/j722s_evm_r5_defconfig create mode 100644 doc/board/ti/j722s_evm.rst create mode 100644 dts/upstream/src/arm64/ti/k3-j722s-evm.dts create mode 100644 dts/upstream/src/arm64/ti/k3-j722s.dtsi create mode 100644 include/configs/j722s_evm.h -- 2.25.1

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[V2 PATCH 0/2] Update RAM Bank Logic for RK3568/RK3588
by Chris Morgan 05 Apr '24

05 Apr '24

From: Chris Morgan <macromorgan(a)hotmail.com> Use the ATAG info provided by the Rockchip binary TPL to identify RAM banks on the RK3568 and RK3588 when using the ROCKCHIP_TPL binary. This is needed because there are specific addresses that should not be written to for all RK3588 based devices with >=16GB of RAM, writing to these addresses immediately results in a crash. Additionally on the RK3568 and RK3588 this allows us to reclaim 256MB of RAM when RAM >= 4GB. Changes since V1: - After additional feedback, removed RFC tag. - Made code work for both RK3568 and RK3588. - Removed memory hole code for all RK3588 boards. - Updated CONFIG_NR_DRAM_BANKS for 3568 and 3588 boards as it is the max number of banks supported by the ATAGS code. Chris Morgan (2): rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588 rockchip: Switch RK3568 and RK3588 to new RAM bank logic arch/arm/mach-rockchip/sdram.c | 100 ++++++++++++++++++ board/friendlyelec/nanopc-t6-rk3588/Makefile | 6 -- .../nanopc-t6-rk3588/nanopc-t6-rk3588.c | 39 ------- board/pine64/quartzpro64-rk3588/Makefile | 3 - .../quartzpro64-rk3588/quartzpro64-rk3588.c | 39 ------- board/radxa/rock5a-rk3588s/Makefile | 6 -- board/radxa/rock5a-rk3588s/rock5a-rk3588s.c | 39 ------- board/radxa/rock5b-rk3588/Makefile | 6 -- board/radxa/rock5b-rk3588/rock5b-rk3588.c | 39 ------- board/rockchip/evb_rk3588/Makefile | 6 -- board/rockchip/evb_rk3588/evb-rk3588.c | 39 ------- board/turing/turing-rk1-rk3588/Makefile | 6 -- .../turing-rk1-rk3588/turing-rk1-rk3588.c | 39 ------- configs/anbernic-rgxx3-rk3566_defconfig | 2 +- configs/bpi-r2-pro-rk3568_defconfig | 2 +- configs/evb-rk3568_defconfig | 2 +- configs/evb-rk3588_defconfig | 3 +- configs/generic-rk3568_defconfig | 2 +- configs/lubancat-2-rk3568_defconfig | 2 +- configs/nanopc-t6-rk3588_defconfig | 3 +- configs/nanopi-r5c-rk3568_defconfig | 2 +- configs/nanopi-r5s-rk3568_defconfig | 2 +- configs/neu6a-io-rk3588_defconfig | 2 +- configs/neu6b-io-rk3588_defconfig | 2 +- configs/odroid-m1-rk3568_defconfig | 2 +- configs/orangepi-5-plus-rk3588_defconfig | 3 +- configs/orangepi-5-rk3588s_defconfig | 3 +- configs/quartz64-a-rk3566_defconfig | 2 +- configs/quartz64-b-rk3566_defconfig | 2 +- configs/quartzpro64-rk3588_defconfig | 3 +- configs/radxa-cm3-io-rk3566_defconfig | 2 +- configs/radxa-e25-rk3568_defconfig | 2 +- configs/rock-3a-rk3568_defconfig | 2 +- configs/rock5a-rk3588s_defconfig | 3 +- configs/rock5b-rk3588_defconfig | 3 +- configs/soquartz-blade-rk3566_defconfig | 2 +- configs/soquartz-cm4-rk3566_defconfig | 2 +- configs/soquartz-model-a-rk3566_defconfig | 2 +- configs/turing-rk1-rk3588_defconfig | 3 +- 39 files changed, 126 insertions(+), 301 deletions(-) delete mode 100644 board/friendlyelec/nanopc-t6-rk3588/Makefile delete mode 100644 board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c delete mode 100644 board/pine64/quartzpro64-rk3588/Makefile delete mode 100644 board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c delete mode 100644 board/radxa/rock5a-rk3588s/Makefile delete mode 100644 board/radxa/rock5a-rk3588s/rock5a-rk3588s.c delete mode 100644 board/radxa/rock5b-rk3588/Makefile delete mode 100644 board/radxa/rock5b-rk3588/rock5b-rk3588.c delete mode 100644 board/rockchip/evb_rk3588/Makefile delete mode 100644 board/rockchip/evb_rk3588/evb-rk3588.c delete mode 100644 board/turing/turing-rk1-rk3588/Makefile delete mode 100644 board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c -- 2.34.1

3 6

[PATCH 0/3] qcom: support SPMI buttons on SM8550 and SM8650
by Neil Armstrong 05 Apr '24

05 Apr '24

First add PMIC gpio variant on pm8550-gpio, then rework the qcom-pmic button driver to support data structs for each PMIC variant and finally add the data for the pmk8350 button configs. Signed-off-by: Neil Armstrong <neil.armstrong(a)linaro.org> --- Neil Armstrong (3): gpio: qcom_pmic_gpio: add support for pm8550-gpio button: qcom-pmic: move node name checks to btn_data struct button: qcom-pmic: add support for pmk8350 button configs drivers/button/button-qcom-pmic.c | 98 ++++++++++++++++++++++++++++----------- drivers/gpio/qcom_pmic_gpio.c | 18 ++++++- 2 files changed, 86 insertions(+), 30 deletions(-) --- base-commit: f0e6aba1218bca578605697eed8aa94582bf57bb change-id: 20240404-topic-sm8x50-spmi-clients-d9a085aae979 Best regards, -- Neil Armstrong <neil.armstrong(a)linaro.org>

1 4