April 2024 - U-Boot

[PATCH] configs: am6*_evm_a53_defconfig: Enable config to support mmc rescan
by Judith Mendez 12 Apr '24

12 Apr '24

Enable MMC_SPEED_MODE_SET config option in defconfig to enable mmc rescan for various Sitara devices. Signed-off-by: Judith Mendez <jm(a)ti.com> --- configs/am62px_evm_a53_defconfig | 1 + configs/am62x_evm_a53_defconfig | 1 + configs/am64x_evm_a53_defconfig | 1 + configs/am65x_evm_a53_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig index 2621abb8ce..6dbdd427ec 100644 --- a/configs/am62px_evm_a53_defconfig +++ b/configs/am62px_evm_a53_defconfig @@ -73,6 +73,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y +CONFIG_MMC_SPEED_MODE_SET=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_MULTI_DTB_FIT=y diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index 4c1e4d7cc4..a25f7b2223 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -50,6 +50,7 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_MMC=y +CONFIG_MMC_SPEED_MODE_SET=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_MULTI_DTB_FIT=y diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index b7057be3d6..179c42a544 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -72,6 +72,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y +CONFIG_MMC_SPEED_MODE_SET=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="ti/k3-am642-evm ti/k3-am642-sk" diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 500335f7e6..3afa80f45a 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -73,6 +73,7 @@ CONFIG_CMD_TIME=y CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs)" CONFIG_CMD_UBI=y +CONFIG_MMC_SPEED_MODE_SET=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y base-commit: b145877c22b391a4872c875145a8f86f6ffebaba -- 2.43.2

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[PATCH RFC 00/15] Support SPI NAND booting on the T113
by John Watts 12 Apr '24

12 Apr '24

This series is my current working and tested setup for booting from SPI NAND chips on the Allwinner T113. I have included the following patches from others. I may have modified them to work with the latest mainline: https://lore.kernel.org/all/20221014030520.3067228-1-uwu@icenowy.me/ https://lore.kernel.org/all/20231111133432.755363-2-bigunclemax@gmail.com/ Hopefully this can get the ball rolling on how to properly implement SPI NAND support in mainline U-Boot. Signed-off-by: John Watts <contact(a)jookia.org> --- Icenowy Zheng (5): sunxi: SPL SPI: extract code for doing SPI transfer sunxi: SPL SPI: add support for read command with 2 byte address sunxi: SPL SPI: allow multiple boot attempt sunxi: SPL SPI: add initial support for booting from SPI NAND sunxi: enable support for SPI NAND booting on SUNIV John Watts (9): sunxi: Separate boot device and boot position spl: Add BOOT_DEVICE_SPINAND option sunxi: Implement BOOT_DEVICE_SPINAND in SPL spl: Add SPL_SPINAND configuration options sunxi: Use SPL_SPINAND for configuration nand: Add spinand_ helper functions sunxi: Implement spinand_ helpers spl: Support SPI NAND boot in UBI spl: Support loading FIT images in UBI Maksim Kiselev (1): sunxi: SPL SPI: Add SPI boot support for the Allwinner R528/T113 SoCs arch/arm/include/asm/arch-sunxi/spl.h | 3 +- arch/arm/include/asm/spl.h | 1 + arch/arm/mach-sunxi/Kconfig | 2 +- arch/arm/mach-sunxi/board.c | 31 +-- arch/arm/mach-sunxi/spl_spi_sunxi.c | 348 +++++++++++++++++++++++++--------- arch/mips/include/asm/spl.h | 1 + arch/riscv/include/asm/spl.h | 1 + arch/sandbox/include/asm/spl.h | 1 + common/spl/Kconfig | 21 ++ common/spl/spl_ubi.c | 49 ++++- include/nand.h | 3 + 11 files changed, 354 insertions(+), 107 deletions(-) --- base-commit: 777c28460947371ada40868dc994dfe8537d7115 change-id: 20240411-spinand-eb7d8319813b Best regards, -- John Watts <contact(a)jookia.org>

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Re: [PATCH v2] board: rockchip: Add the Turing RK1 SoM
by Florian Klink 12 Apr '24

12 Apr '24

Hey Sam, On 24-04-11 16:35:57, Sam Edwards wrote: >On Thu, Apr 11, 2024 at 1:29 AM Florian Klink <flokli(a)flokli.de> wrote: >> >> On 23-12-14 18:46:47, Joshua Riek wrote: >> >The Turing RK1 is a Rockchip RK3588 based SoM from Turing Machines. >> > >> >Specifications: >> > >> > Rockchip RK3588 SoC >> > 4x ARM Cortex-A76, 4x ARM Cortex-A55 >> > 8/16/32GB memory LPDDR4x >> > Mali G610MC4 GPU >> > 32GB eMMC HS400 >> > 2x USB 2.0, 2x USB 3.0 >> > 2x MIPI CSI 4x lanes >> > 1x MIPI-DSI DPHY 2x lanes >> > PCIe 2.0 x1, PCIe 3.0 x4 >> > 1x HDMI 2.1 output, 1x DP 1.4 output >> > Gigabit Ethernet >> > Size: 69.6mm x 45mm (260-pin SO-DIMM connector) >> > >> >Kernel commit: >> >2806a69f3fef ("arm64: dts: rockchip: Add Turing RK1 SoM support") >> >> […] >> >> >diff --git a/configs/turing-rk1-rk3588_defconfig b/configs/turing-rk1-rk3588_defconfig >> >new file mode 100644 >> >index 0000000000..289f2da775 >> >--- /dev/null >> >+++ b/configs/turing-rk1-rk3588_defconfig >> >@@ -0,0 +1,133 @@ >> >+CONFIG_ARM=y >> >+CONFIG_SKIP_LOWLEVEL_INIT=y >> >+CONFIG_SYS_HAS_NONCACHED_MEMORY=y >> >+CONFIG_COUNTER_FREQUENCY=24000000 >> >+CONFIG_ARCH_ROCKCHIP=y >> >+CONFIG_TEXT_BASE=0x00a00000 >> >+CONFIG_SPL_LIBCOMMON_SUPPORT=y >> >+CONFIG_SPL_LIBGENERIC_SUPPORT=y >> >+CONFIG_NR_DRAM_BANKS=2 >> >+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y >> >+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 >> >+CONFIG_SF_DEFAULT_SPEED=24000000 >> >+CONFIG_SF_DEFAULT_MODE=0x2000 >> >+CONFIG_DEFAULT_DEVICE_TREE="rk3588-turing-rk1" >> >+CONFIG_ROCKCHIP_RK3588=y >> >+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y >> >+CONFIG_ROCKCHIP_SPI_IMAGE=y >> > >Hi Florian, > >Thanks for getting in touch! > >> Does the RK1 have an SPI chip attached, and is is possible to flash >> u-boot into SPI and boot from it? > >The answer you want is "no." Though the RK1 does have an unpopulated >pad for SPI flash, actually installing one would be a pretty involved >user modification, and those users almost certainly can/will build the >SPI boot image themselves. > >> This has sparked some confusion on whether "u-boot-rockchip-spi.bin" >> should be provided in a downstream build or not. > >Ah yeah the CONFIG_ROCKCHIP_SPI_IMAGE=y might not be a sensible >default given that 99.9% of users don't need it. Is that config entry >the main thing creating the confusion? I think it should be removed >here in U-Boot if so. Yes, it caused a "u-boot-rockchip-spi.bin" to be produced, and we were wondering on whether it should be provided as a result of our build to downstream users [1]. Removing it from the `defconfig` sounds like the best way to prevent this confusion. If people solder on a SPI Flash manually, they probably know how to re-add it to the uboot config ;-) Could you send a patch for that? >Note that the RK1 is a little different from most RK3588 boards in >that UART9 at 115200 baud is the generally-accepted debug UART (due >both to the popularity of pairing it with the Turing Pi 2 >clusterboard, and for pin-compatibility with most NVIDIA Jetson SoMs), >and setting this very early in boot requires using Rockchip's >"ddrbin_tool" to change the configuration embedded in the ddrbin/TPL >image. If you're already supporting other targets that require ddrbin >configuration changes, please add these for RK1: > >uart id=9 >uart iomux=0 >uart baudrate=115200 > >...but if this would require going significantly out of your way, >don't worry about it. IIUC this is only required to get TPL+SPL output >routed correctly: the U-Boot monitor + kernel will still >(re)initialize UART9 appropriately. We currently simply use `bin/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin` from https://github.com/rockchip-linux/rkbin for all RK3588 targets as `ROCKCHIP_TPL`. There doesn't seem to be a RK1-specific blob in the repo, and so far we're not invoking the closed-source x86_64-linux-only `tools/ddrbin_tool` binary to produce an alternative version of the SPL for other targets either. So if it also works without doing that (maybe with a little bit less debug serial output during early boot) we'd probably keep it like this ;-) Thanks, Florian [1]: https://github.com/NixOS/nixpkgs/pull/302138#discussion_r1560349114

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Re: [PATCH v2 0/2] sunxi, usb: UDC/DM gadget model support
by Sam Edwards 12 Apr '24

12 Apr '24

On Thu, Apr 11, 2024 at 1:40 AM John Watts <contact(a)jookia.org> wrote: > > On Thu, Apr 11, 2024 at 12:52:14AM -0600, Sam Edwards wrote: > > Hi John, > > > > This patch was developed against (and used very heavily on) the Turing > > Pi 2, which has an Allwinner T113-s3 SoC. Likely it should work for > > any T113/D1 board. I haven't been encountering any USB errors but also > > my use case hasn't gone much beyond the `udc` command. What > > device/errors do you have over there? > > > > Cheers, > > Sam > > Hi Sam, > > I made a list of things that do work: > > - DFU (slowly, probably due to no DMA) to RAM > - CDC serial console > > Running a command like this: > > ubi part ubi; ubifsmount ubi:root; ums 0 ubi 0; Hi John, Ahh I see the problem. In U-Boot, `ubi` isn't actually a block device: it's implemented as a stub in the block layer, and the filesystem layer redirects `ubi` accesses to the currently-mounted ubifs instead. But the `ums` command works on the block layer, so it's not being intercepted, and instead hitting that stub and likely crashing. In the spirit of the Linux ubiblock driver, I have another patchset[1] I've been working on[2] to expose static ubivols as true read-only block devices. Note that this only works for static volumes: the access semantics of dynamic volumes are too flash-like to support block device access, so accessing them with `ums` likely will never work like users expect. Still, there could be some interaction issue between `ums`<->USB that I haven't identified. Could you try with mmc (if available) or a ramdisk (otherwise) just to confirm that `ums` is fine? Regards, Sam [1] https://lore.kernel.org/u-boot/20230812000606.72319-1-CFSworks@gmail.com/T/ [2] Not very diligently; if you're interested in helping test it, I'd love to get back to it. > > Gives this output in dmesg: > > [3633079.772330] usb-storage 1-1.1:1.0: USB Mass Storage device detected > [3633079.772506] scsi host9: usb-storage 1-1.1:1.0 > [3633080.794607] scsi 9:0:0:0: Direct-Access Linux UMS disk 0 ffff PQ: 0 ANSI: 2 > [3633080.794941] sd 9:0:0:0: Attached scsi generic sg6 type 0 > [3633080.795214] sd 9:0:0:0: [sdg] 3942645758 512-byte logical blocks: (2.02 TB/1.83 TiB) > [3633080.795220] sd 9:0:0:0: [sdg] 3925868545-byte physical blocks > [3633080.795341] sd 9:0:0:0: [sdg] Write Protect is off > [3633080.795345] sd 9:0:0:0: [sdg] Mode Sense: 0f 00 00 00 > [3633080.795462] sd 9:0:0:0: [sdg] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA > [3633080.907359] usb 1-1.1: reset high-speed USB device number 44 using xhci_hcd > [3633081.021905] usb 1-1.1: device descriptor read/64, error -71 > [3633081.238566] usb 1-1.1: device descriptor read/64, error -71 > [3633081.448573] usb 1-1.1: reset high-speed USB device number 44 using xhci_hcd > [3633081.558566] usb 1-1.1: device descriptor read/64, error -71 > [3633081.775236] usb 1-1.1: device descriptor read/64, error -71 > [3633081.988559] usb 1-1.1: reset high-speed USB device number 44 using xhci_hcd > [3633086.788615] usb 1-1.1: Device not responding to setup address. > [3633091.799190] usb 1-1.1: Device not responding to setup address. > [3633092.008482] usb 1-1.1: device not accepting address 44, error -71 > [3633092.747719] usb 1-1.1: USB disconnect, device number 44 > [3633092.748488] device offline error, dev sdg, sector 0 op 0x0:(READ) flags 0x0 phys_seg 2 prio class 2 > [3633092.748502] buffer_io_error: 10 callbacks suppressed > [3633092.748504] Buffer I/O error on dev sdg, logical block 0, async page read > [3633092.748511] Buffer I/O error on dev sdg, logical block 1, async page read > [3633092.748520] device offline error, dev sdg, sector 4 op 0x0:(READ) flags 0x0 phys_seg 2 prio class 2 > [3633092.748525] Buffer I/O error on dev sdg, logical block 2, async page read > [3633092.748529] Buffer I/O error on dev sdg, logical block 3, async page read > [3633092.748582] device offline error, dev sdg, sector 0 op 0x0:(READ) flags 0x0 phys_seg 4 prio class 2 > [3633092.748594] Buffer I/O error on dev sdg, logical block 0, async page read > [3633092.748600] Buffer I/O error on dev sdg, logical block 1, async page read > [3633092.748605] Buffer I/O error on dev sdg, logical block 2, async page read > [3633092.748609] Buffer I/O error on dev sdg, logical block 3, async page read > [3633092.748621] ldm_validate_partition_table(): Disk read failed. > [3633092.748638] device offline error, dev sdg, sector 0 op 0x0:(READ) flags 0x0 phys_seg 2 prio class 2 > [3633092.748644] Buffer I/O error on dev sdg, logical block 0, async page read > [3633092.748649] Buffer I/O error on dev sdg, logical block 1, async page read > [3633092.748665] device offline error, dev sdg, sector 4 op 0x0:(READ) flags 0x0 phys_seg 2 prio class 2 > [3633092.748686] device offline error, dev sdg, sector 0 op 0x0:(READ) flags 0x0 phys_seg 2 prio class 2 > [3633092.748704] device offline error, dev sdg, sector 4 op 0x0:(READ) flags 0x0 phys_seg 2 prio class 2 > [3633092.748726] device offline error, dev sdg, sector 0 op 0x0:(READ) flags 0x0 phys_seg 2 prio class 2 > [3633092.748744] device offline error, dev sdg, sector 4 op 0x0:(READ) flags 0x0 phys_seg 2 prio class 2 > [3633092.748754] sdg: unable to read partition table > [3633092.748825] sd 9:0:0:0: [sdg] Attached SCSI removable disk > > Hitting Ctrl-C in U-Boot then re-running the command gives this output: > > CTRL+C - Operation aborted > => ubi part ubi; ubifsmount ubi:root; ums 0 ubi 0; > UBI partition 'ubi' already selected > UMS: LUN 0, dev ubi -352321538, hwpart 234, sector 0x0, count 0xeafffffe > prefetch abort > pc : [<e8fd9ffa>] lr : [<45fb7665>] > reloc pc : [<e5e53ffa>] lr : [<42e31665>] > sp : 45d5f970 ip : 45dd66a8 fp : 00000000 > r10: 45ff88ec r9 : 45d65eb0 r8 : 45dd1fe8 > r7 : 45dd1fd8 r6 : 45ff5f18 r5 : 45dd5600 r4 : 45fff4f0 > r3 : e8fd9fff r2 : 45ff3260 r1 : 00000005 r0 : 45dd5594 > Flags: Nzcv IRQs off FIQs off Mode SVC_32 (T) > Code: ffff ffff fefd ffff (ffff) ffff > Resetting CPU ... > > Fastboot instantly downloads an image but produces this output: > > => fastboot 0 > musb-hdrc: peripheral reset irq lost! > Starting download of 7317504 bytes > ....................................................... > downloading of 7317504 bytes finished > Booting kernel at 42000000... > > > Wrong Image Type for bootm command > ERROR -91: can't get kernel image! > resetting ... > > > Running 'fastboot stage' to just upload an image then hitting Ctrl-C in U-Boot gives this error: > > undefined instruction > pc : [<45d69280>] lr : [<45fb8c0b>] > reloc pc : [<42be3280>] lr : [<42e32c0b>] > sp : 45d5fa28 ip : 45d6b59c fp : 00000000 > r10: 00000002 r9 : 45d65eb0 r8 : 00000000 > r7 : 00000002 r6 : 45d68c3c r5 : 00000000 r4 : 45d69288 > r3 : 45d69280 r2 : 00000001 r1 : 00001238 r0 : 45d69288 > Flags: nZCv IRQs off FIQs off Mode SVC_32 > Code: ffffffff ffffffff ffffffff ffffffff (ffffffff) > Resetting CPU ... > > Not too sure what's happening here. > > John. > > > > > > > > > John. > > > > > > On Thu, Jun 08, 2023 at 01:56:29PM -0600, Sam Edwards wrote: > > > > Happy Thursday, U-Boot list! > > > > > > > > Here is attempt 2 at making this USB controller driver compatible with > > > > DM's gadget model, following what most of the other musb variants do. > > > > > > > > v2 removes the unwanted printfs in the probe func, per feedback from Marek. > > > > I received no other feedback against v1 of this patch. > > > > > > > > Cheers, > > > > Sam > > > > > > > > Sam Edwards (2): > > > > usb: musb-new: sunxi: remove unwanted printfs > > > > usb: musb-new: sunxi: make compatible with UDC/DM gadget model > > > > > > > > drivers/usb/musb-new/sunxi.c | 52 +++++++++++++++++++++--------------- > > > > 1 file changed, 31 insertions(+), 21 deletions(-) > > > > > > > > -- > > > > 2.39.2 > > > >

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[PATCH 00/11] cadence-qspi: Add DTR support including PHY mode calibration
by Greg Malysa 12 Apr '24

12 Apr '24

This series introduces support for DTR mode for the Cadence QSPI/OSPI IP. We have been developing it against the SC594/SC598 from ADI, so there are some limitations specific to our hardware's capabilities. Ideally this series could be enhanced with features introduced in a patch series submitted by AMD, but currently no work has been done to reconcile the two. So this is somewhere between an RFC patch and a patch series we wish to submit as-is for inclusion. Beyond the specific support for the QSPI peripheral, this series also introduces a more general calibration framework as part of the spi system in order to facilitate integration of calibration support for other controllers within a consistent approach. Ian Roberts (11): mtd: spi-nor: Add calibration hook for high speed SPI mtd: spi-nor: Octal DTR support for IS25*x spi: cadence-quadspi: Enable DDR bit for DTR commands spi: cadence-quadspi: enable opcode extension based on command length spi: cadence-quadspi: disable automatic write enable spi: cadence-quadspi: unconditionally disable auto status register reads spi: cadence-quadspi: Remove redundant DTR state spi: cadence-quadspi: Direct mode does not support zero length addresses spi: cadence-quadspi: Add support for memory DMA channel transfers spi: cadence-quadspi: Add DT control of max Read Delay Capture value spi: cadence-quadspi: Implement high speed calibration doc/device-tree-bindings/spi/spi-bus.txt | 4 + doc/device-tree-bindings/spi/spi-cadence.txt | 11 + drivers/mtd/spi/Kconfig | 12 + drivers/mtd/spi/spi-nor-core.c | 246 ++++++++ drivers/mtd/spi/spi-nor-ids.c | 6 +- drivers/spi/cadence_qspi.c | 444 ++++++++++---- drivers/spi/cadence_qspi.h | 105 +++- drivers/spi/cadence_qspi_apb.c | 572 +++++++++++++++---- drivers/spi/spi-mem.c | 24 + include/linux/mtd/spi-nor.h | 13 + include/spi-mem.h | 19 + 11 files changed, 1226 insertions(+), 230 deletions(-) -- 2.43.2

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[PATCH v2] board: rockchip: Add the Turing RK1 SoM
by Joshua Riek 12 Apr '24

12 Apr '24

The Turing RK1 is a Rockchip RK3588 based SoM from Turing Machines. Specifications: Rockchip RK3588 SoC 4x ARM Cortex-A76, 4x ARM Cortex-A55 8/16/32GB memory LPDDR4x Mali G610MC4 GPU 32GB eMMC HS400 2x USB 2.0, 2x USB 3.0 2x MIPI CSI 4x lanes 1x MIPI-DSI DPHY 2x lanes PCIe 2.0 x1, PCIe 3.0 x4 1x HDMI 2.1 output, 1x DP 1.4 output Gigabit Ethernet Size: 69.6mm x 45mm (260-pin SO-DIMM connector) Kernel commit: 2806a69f3fef ("arm64: dts: rockchip: Add Turing RK1 SoM support") Signed-off-by: Joshua Riek <jjriek(a)verizon.net> Cc: Sam Edwards <CFSworks(a)gmail.com> --- Changes in v2: - removed BOOT_TARGET #ifdef ... #endif in the RK1 header file --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi | 25 + arch/arm/dts/rk3588-turing-rk1.dts | 21 + arch/arm/dts/rk3588-turing-rk1.dtsi | 614 ++++++++++++++++++ arch/arm/mach-rockchip/rk3588/Kconfig | 24 + board/turing/turing-rk1-rk3588/Kconfig | 15 + board/turing/turing-rk1-rk3588/MAINTAINERS | 9 + board/turing/turing-rk1-rk3588/Makefile | 6 + .../turing-rk1-rk3588/turing-rk1-rk3588.c | 39 ++ configs/turing-rk1-rk3588_defconfig | 133 ++++ doc/board/rockchip/rockchip.rst | 1 + include/configs/turing-rk1-rk3588.h | 15 + 12 files changed, 903 insertions(+) create mode 100644 arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588-turing-rk1.dts create mode 100644 arch/arm/dts/rk3588-turing-rk1.dtsi create mode 100644 board/turing/turing-rk1-rk3588/Kconfig create mode 100644 board/turing/turing-rk1-rk3588/MAINTAINERS create mode 100644 board/turing/turing-rk1-rk3588/Makefile create mode 100644 board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c create mode 100644 configs/turing-rk1-rk3588_defconfig create mode 100644 include/configs/turing-rk1-rk3588.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1be08c5fdc..97355d84de 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -195,6 +195,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \ rk3588s-orangepi-5.dtb \ rk3588-orangepi-5-plus.dtb \ rk3588-quartzpro64.dtb \ + rk3588-turing-rk1.dtb \ rk3588s-rock-5a.dtb \ rk3588-rock-5b.dtb diff --git a/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi b/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi new file mode 100644 index 0000000000..06c6f327c1 --- /dev/null +++ b/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Joshua Riek <jjriek(a)verizon.net> + * + */ + +#include "rk3588-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; + }; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; +}; + +&uart9 { + bootph-pre-ram; + clock-frequency = <24000000>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-turing-rk1.dts b/arch/arm/dts/rk3588-turing-rk1.dts new file mode 100644 index 0000000000..7bcad28d73 --- /dev/null +++ b/arch/arm/dts/rk3588-turing-rk1.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * This device tree covers the common case where the RK1 is used as a + * "compute node" system, where the carrier board is functioning more like a + * generic backplane (with no non-autoenumerable peripherals of its own) than + * like a device that the SoM is meant to enable. + * + * Copyright (c) 2023 Sam Edwards <CFSworks(a)gmail.com> + */ + +/dts-v1/; +#include "rk3588-turing-rk1.dtsi" + +/ { + model = "Turing Machines RK1"; + compatible = "turing,rk1", "rockchip,rk3588"; + + chosen { + stdout-path = "serial9:115200n8"; + }; +}; diff --git a/arch/arm/dts/rk3588-turing-rk1.dtsi b/arch/arm/dts/rk3588-turing-rk1.dtsi new file mode 100644 index 0000000000..9570b34aca --- /dev/null +++ b/arch/arm/dts/rk3588-turing-rk1.dtsi @@ -0,0 +1,614 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device tree definitions for the Turing RK1 SoM. + * + * Copyright (c) 2023 Sam Edwards <CFSworks(a)gmail.com> + * + * Based on RK3588-EVB1 devicetree + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3588.dtsi" + +/ { + compatible = "turing,rk1", "rockchip,rk3588"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + serial2 = &uart2; + serial9 = &uart9; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 25 95 145 195 255>; + fan-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0m2_pins &fan_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>; + pwms = <&pwm0 0 50000 0>; + #cooling-cells = <2>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie30_en>; + startup-delay-us = <5000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-rxid"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + pinctrl-names = "default"; + rx_delay = <0x00>; + tx_delay = <0x43>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <15000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1l1 { + linux,pci-domain = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_reset>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + linux,pci-domain = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_reset>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + fan { + fan_int: fan-int { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie2 { + pcie2_reset: pcie2-reset { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_reset: pcie3-reset { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc3v3_pcie30_en: pcie3-reg { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&spi2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&uart9 { + pinctrl-0 = <&uart9m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index e5282dd112..a2193fbd41 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -132,6 +132,29 @@ config TARGET_QUARTZPRO64_RK3588 Pine64 QuartzPro64 is a Rockchip RK3588 based SBC (Single Board Computer) by Pine64. +config TARGET_TURINGRK1_RK3588 + bool "Turing Machines RK1 RK3588 board" + select BOARD_LATE_INIT + help + The Turing RK1 is a Rockchip RK3588 based SoM from Turing Machines. + + There are three variants depending on the DRAM size : 8G, 16G and 32G. + + Specifications: + + Rockchip RK3588 SoC + 4x ARM Cortex-A76, 4x ARM Cortex-A55 + 8/16/32GB memory LPDDR4x + Mali G610MC4 GPU + 32GB eMMC HS400 + 2x USB 2.0, 2x USB 3.0 + 2x MIPI CSI 4x lanes + 1x MIPI-DSI DPHY 2x lanes + PCIe 2.0 x1, PCIe 3.0 x4 + 1x HDMI 2.1 output, 1x DP 1.4 output + Gigabit Ethernet + Size: 69.6mm x 45mm (260-pin SO-DIMM connector) + config ROCKCHIP_BOOT_MODE_REG default 0xfd588080 @@ -147,6 +170,7 @@ config SYS_MALLOC_F_LEN source board/edgeble/neural-compute-module-6/Kconfig source board/friendlyelec/nanopc-t6-rk3588/Kconfig source board/pine64/quartzpro64-rk3588/Kconfig +source board/turing/turing-rk1-rk3588/Kconfig source board/rockchip/evb_rk3588/Kconfig source board/radxa/rock5a-rk3588s/Kconfig source board/radxa/rock5b-rk3588/Kconfig diff --git a/board/turing/turing-rk1-rk3588/Kconfig b/board/turing/turing-rk1-rk3588/Kconfig new file mode 100644 index 0000000000..4c6cd6af34 --- /dev/null +++ b/board/turing/turing-rk1-rk3588/Kconfig @@ -0,0 +1,15 @@ +if TARGET_TURINGRK1_RK3588 + +config SYS_BOARD + default "turing-rk1-rk3588" + +config SYS_VENDOR + default "turing" + +config SYS_CONFIG_NAME + default "turing-rk1-rk3588" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/turing/turing-rk1-rk3588/MAINTAINERS b/board/turing/turing-rk1-rk3588/MAINTAINERS new file mode 100644 index 0000000000..4f313732fa --- /dev/null +++ b/board/turing/turing-rk1-rk3588/MAINTAINERS @@ -0,0 +1,9 @@ +TURINGRK1-RK3588 +M: Joshua Riek <jjriek(a)verizon.net> +S: Maintained +F: board/turing/turing-rk1-rk3588 +F: include/configs/turing-rk1-rk3588.h +F: configs/turing-rk1-rk3588_defconfig +F: arch/arm/dts/rk3588-turing-rk1.dts +F: arch/arm/dts/rk3588-turing-rk1.dtsi +F: arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi diff --git a/board/turing/turing-rk1-rk3588/Makefile b/board/turing/turing-rk1-rk3588/Makefile new file mode 100644 index 0000000000..a979d8023a --- /dev/null +++ b/board/turing/turing-rk1-rk3588/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2023 Rockchip Electronics Co,. Ltd. +# + +obj-y += turing-rk1-rk3588.o diff --git a/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c b/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c new file mode 100644 index 0000000000..e2338a2a35 --- /dev/null +++ b/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023 Rockchip Electronics Co,. Ltd. + */ + +#include <fdtdec.h> +#include <fdt_support.h> + +#ifdef CONFIG_OF_BOARD_SETUP +int turing_rk1_add_reserved_memory_fdt_nodes(void *new_blob) +{ + struct fdt_memory gap1 = { + .start = 0x3fc000000, + .end = 0x3fc4fffff, + }; + struct fdt_memory gap2 = { + .start = 0x3fff00000, + .end = 0x3ffffffff, + }; + unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; + unsigned int ret; + + /* + * Inject the reserved-memory nodes into the DTS + */ + ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0, + NULL, flags); + if (ret) + return ret; + + return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0, + NULL, flags); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return turing_rk1_add_reserved_memory_fdt_nodes(blob); +} +#endif diff --git a/configs/turing-rk1-rk3588_defconfig b/configs/turing-rk1-rk3588_defconfig new file mode 100644 index 0000000000..289f2da775 --- /dev/null +++ b/configs/turing-rk1-rk3588_defconfig @@ -0,0 +1,133 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588-turing-rk1" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_TURINGRK1_RK3588=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFEBC0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-turing-rk1.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_SCSI=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TFTPSRV=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SATA=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_PHYLIB=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=115200 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_XHCI_PCI=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_LAN75XX=y +CONFIG_USB_ETHER_LAN78XX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_PRODUCT_NUM=0x350b +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 18d0b6f089..9fe69fc942 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -117,6 +117,7 @@ List of mainline supported Rockchip boards: - Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588) - FriendlyElec NanoPC-T6 (nanopc-t6-rk3588) - Pine64 QuartzPro64 (quartzpro64-rk3588) + - Turing Machines RK1 (turing-rk1-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) - Radxa ROCK 5B (rock5b-rk3588) - Xunlong Orange Pi 5 (orangepi-5-rk3588s) diff --git a/include/configs/turing-rk1-rk3588.h b/include/configs/turing-rk1-rk3588.h new file mode 100644 index 0000000000..760f3c6ab3 --- /dev/null +++ b/include/configs/turing-rk1-rk3588.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#ifndef __TURINGRK1_RK3588_H +#define __TURINGRK1_RK3588_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3588_common.h> + +#endif /* __TURINGRK1_RK3588_H */ -- 2.25.1

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[PATCH] boot: Pass baud rate to stdout-path
by John Watts 11 Apr '24

11 Apr '24

Linux might use the wrong baud rate such as 9600 by default, make sure to specify it when passing the serial port over. Signed-off-by: John Watts <contact(a)jookia.org> --- On my board at least (a sunxi T113) the serial console will initialize as 9600 baud instead of the set baud. Pass the baud with the serial device to Linux to solve this issue. --- boot/fdt_support.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boot/fdt_support.c b/boot/fdt_support.c index 090d82ee80..83e62f47b5 100644 --- a/boot/fdt_support.c +++ b/boot/fdt_support.c @@ -153,9 +153,9 @@ static int fdt_fixup_stdout(void *fdt, int chosenoff) } /* fdt_setprop may break "path" so we copy it to tmp buffer */ - memcpy(tmp, path, len); + len = sprintf(tmp, "%.*s:%d", len, (char *)path, CONFIG_BAUDRATE); - err = fdt_setprop(fdt, chosenoff, "linux,stdout-path", tmp, len); + err = fdt_setprop(fdt, chosenoff, "linux,stdout-path", tmp, len + 1); if (err < 0) printf("WARNING: could not set linux,stdout-path %s.\n", fdt_strerror(err)); --- base-commit: 777c28460947371ada40868dc994dfe8537d7115 change-id: 20240411-stdout-4f91b566a0f2 Best regards, -- John Watts <contact(a)jookia.org>

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[PATCH 0/2] sunxi: Support UART1 and UART2 on the T113
by John Watts 11 Apr '24

11 Apr '24

The T113 supports UART1 and UART2 on PG and PD pins respectively. Add support for these in U-Boot so we can use them. Note: I'm not entirely sure if the PD pins should be default, they overlap with the LCD pins. I am however using this on a real board. Signed-off-by: John Watts <contact(a)jookia.org> --- John Watts (2): sunxi: Support UART1 on the T113 sunxi: Support UART2 on the T113 arch/arm/mach-sunxi/board.c | 9 +++++++-- include/sunxi_gpio.h | 1 + 2 files changed, 8 insertions(+), 2 deletions(-) --- base-commit: 777c28460947371ada40868dc994dfe8537d7115 change-id: 20240411-t113serial-a6e9ca8d8848 Best regards, -- John Watts <contact(a)jookia.org>

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[PATCH v4 1/6] boot: fdt: Change type of env_get_bootm_low() to phys_addr_t
by Marek Vasut 11 Apr '24

11 Apr '24

Change type of ulong env_get_bootm_low() to phys_addr_t env_get_bootm_low(). The PPC/LS systems already treat env_get_bootm_low() result as phys_addr_t, while the function itself still returns ulong. This is potentially dangerous on 64bit systems, where ulong might not be large enough to hold the content of "bootm_low" environment variable. Fix it by using phys_addr_t, similar to what env_get_bootm_size() does, which returns phys_size_t . Reviewed-by: Laurent Pinchart <laurent.pinchart(a)ideasonboard.com> Reported-by: Laurent Pinchart <laurent.pinchart(a)ideasonboard.com> Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- Cc: Heinrich Schuchardt <xypron.glpk(a)gmx.de> Cc: Kuninori Morimoto <kuninori.morimoto.gx(a)renesas.com> Cc: Laurent Pinchart <laurent.pinchart(a)ideasonboard.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> --- V2: - Drop now unnecessary conversion in boot_start_lmb() lmb_init_and_reserve_range() - Drop tmp variable in env_get_bootm_low() - Print initrd_high as u64/%llx - Add RB from Laurent V3: No change V4: No change --- boot/bootm.c | 4 ++-- boot/image-board.c | 14 ++++++-------- boot/image-fdt.c | 9 +++++---- include/image.h | 2 +- 4 files changed, 14 insertions(+), 15 deletions(-) diff --git a/boot/bootm.c b/boot/bootm.c index d071537d692..032f5a4a160 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -242,13 +242,13 @@ static int boot_get_kernel(const char *addr_fit, struct bootm_headers *images, #ifdef CONFIG_LMB static void boot_start_lmb(struct bootm_headers *images) { - ulong mem_start; + phys_addr_t mem_start; phys_size_t mem_size; mem_start = env_get_bootm_low(); mem_size = env_get_bootm_size(); - lmb_init_and_reserve_range(&images->lmb, (phys_addr_t)mem_start, + lmb_init_and_reserve_range(&images->lmb, mem_start, mem_size, NULL); } #else diff --git a/boot/image-board.c b/boot/image-board.c index 75f6906cd56..3263497a1d5 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -107,14 +107,12 @@ static int on_loadaddr(const char *name, const char *value, enum env_op op, } U_BOOT_ENV_CALLBACK(loadaddr, on_loadaddr); -ulong env_get_bootm_low(void) +phys_addr_t env_get_bootm_low(void) { char *s = env_get("bootm_low"); - if (s) { - ulong tmp = hextoul(s, NULL); - return tmp; - } + if (s) + return simple_strtoull(s, NULL, 16); #if defined(CFG_SYS_SDRAM_BASE) return CFG_SYS_SDRAM_BASE; @@ -538,7 +536,7 @@ int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, ulong *initrd_start, ulong *initrd_end) { char *s; - ulong initrd_high; + phys_addr_t initrd_high; int initrd_copy_to_ram = 1; s = env_get("initrd_high"); @@ -553,8 +551,8 @@ int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, initrd_high = env_get_bootm_mapsize() + env_get_bootm_low(); } - debug("## initrd_high = 0x%08lx, copy_to_ram = %d\n", - initrd_high, initrd_copy_to_ram); + debug("## initrd_high = 0x%llx, copy_to_ram = %d\n", + (u64)initrd_high, initrd_copy_to_ram); if (rd_data) { if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */ diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 5e4aa9de0d2..c2571b22244 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -160,9 +160,10 @@ int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size) { void *fdt_blob = *of_flat_tree; void *of_start = NULL; - u64 start, size, usable; + phys_addr_t start, size, usable; char *fdt_high; - ulong mapsize, low; + phys_addr_t low; + phys_size_t mapsize; ulong of_len = 0; int bank; int err; @@ -217,7 +218,7 @@ int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size) if (start + size < low) continue; - usable = min(start + size, (u64)(low + mapsize)); + usable = min(start + size, low + mapsize); /* * At least part of this DRAM bank is usable, try @@ -233,7 +234,7 @@ int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size) * Reduce the mapping size in the next bank * by the size of attempt in current bank. */ - mapsize -= usable - max(start, (u64)low); + mapsize -= usable - max(start, low); if (!mapsize) break; } diff --git a/include/image.h b/include/image.h index 21de70f0c9e..acffd17e0df 100644 --- a/include/image.h +++ b/include/image.h @@ -946,7 +946,7 @@ static inline void image_set_name(struct legacy_img_hdr *hdr, const char *name) int image_check_hcrc(const struct legacy_img_hdr *hdr); int image_check_dcrc(const struct legacy_img_hdr *hdr); #ifndef USE_HOSTCC -ulong env_get_bootm_low(void); +phys_addr_t env_get_bootm_low(void); phys_size_t env_get_bootm_size(void); phys_size_t env_get_bootm_mapsize(void); #endif -- 2.43.0

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[PATCH v2 00/19] x86: expo: Add support for editing coreboot CMOS RAM settings
by Simon Glass 11 Apr '24

11 Apr '24

U-Boot provides support for editing settings with an 'expo', as well as reading and writing settings to CMOS RAM. This series integrates expo functionality with coreboot, using the sysinfo table to get a list of settings, creating an expo with them and allowing them to be edited. A new CI test provides coverage for some coreboot-related commands. For this to work, a number of minor tweaks are made to existing tests, so that they pass on coreboot (x86) or at least are skipped when they cannot pass. Likely most of these fixes will apply to other boards too. It includes several other fixes and improvements: - new -m flag for 'bootflow scan' so it can display a menu automatically - Fix for video-scrolling crash with Truetype - menu items can now have individual integer values - menu items are lined up according to the width of all menu labels Changes in v2: - Avoid using common.h - Avoid using common.h - Rebase to -next Simon Glass (19): video: Add a dark-grey console colour video: Avoid starting a new line to close to the bottom expo: Place menu items to the right of all labels expo: Set the initial next_id to 1 expo: Use standard numbering for save and discard expo: Allow menu items to have values expo: Add a little more cedit CMOS logging expo: Support menu-item values in cedit expo: Drop unneceesary calls to expo_str() expo: Drop scene_title_set() expo: Add forward declaration for udevice to cedit x86: coreboot: Enable unit tests x86: CI: Update coreboot x86: coreboot: Add a test for cbsysinfo command x86: coreboot: Show the option table x86: coreboot: Enable support for the configuration editor x86: coreboot: Add a command to check and update CMOS RAM x86: coreboot: Allow building an expo for editing CMOS config x86: Enable RTC command by default .azure-pipelines.yml | 2 +- .gitlab-ci.yml | 2 +- arch/sandbox/dts/cedit.dtsi | 3 + arch/x86/dts/coreboot.dts | 7 + boot/Makefile | 4 + boot/cedit.c | 191 +++++++++++++++-------- boot/expo.c | 3 + boot/expo_build.c | 36 ++--- boot/expo_build_cb.c | 245 ++++++++++++++++++++++++++++++ boot/scene.c | 61 ++++++-- boot/scene_internal.h | 30 +++- boot/scene_menu.c | 26 +++- boot/scene_textline.c | 3 +- cmd/Kconfig | 12 ++ cmd/cedit.c | 28 ++++ cmd/x86/Makefile | 1 + cmd/x86/cbcmos.c | 139 +++++++++++++++++ cmd/x86/cbsysinfo.c | 73 ++++++++- configs/coreboot64_defconfig | 2 + configs/coreboot_defconfig | 6 + doc/board/coreboot/coreboot.rst | 6 + doc/develop/cedit.rst | 9 +- doc/develop/expo.rst | 26 +++- doc/usage/cmd/cbcmos.rst | 45 ++++++ doc/usage/cmd/cbsysinfo.rst | 99 ++++++++++++ doc/usage/cmd/cedit.rst | 91 ++++++++++- doc/usage/index.rst | 1 + drivers/video/vidconsole-uclass.c | 4 +- drivers/video/video-uclass.c | 3 + include/cedit.h | 2 + include/expo.h | 51 +++++-- include/test/cedit-test.h | 30 ++-- include/video.h | 4 +- include/video_console.h | 8 + test/boot/cedit.c | 22 ++- test/boot/expo.c | 26 +++- test/boot/files/expo_ids.h | 3 +- test/boot/files/expo_layout.dts | 5 +- test/cmd/Makefile | 1 + test/cmd/coreboot.c | 119 +++++++++++++++ tools/expo.py | 33 +++- 41 files changed, 1309 insertions(+), 153 deletions(-) create mode 100644 boot/expo_build_cb.c create mode 100644 cmd/x86/cbcmos.c create mode 100644 doc/usage/cmd/cbcmos.rst create mode 100644 test/cmd/coreboot.c -- 2.34.1

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