April 2024 - U-Boot

[PATCH] sysreset: add Qualcomm PSHOLD reset driver
by Robert Marko 23 Apr '24

23 Apr '24

Number of Qualcomm ARMv7 SoC-s did not use PSCI but rather used PSHOLD (Qualcomm Power Supply Hold Reset) bit to trigger reset or poweroff. Qualcomm IPQ40XX is one of them, so provide a simple sysreset driver based on the upstream Linux one, it is DT compatible as well. Signed-off-by: Robert Marko <robert.marko(a)sartura.hr> --- drivers/sysreset/Kconfig | 6 +++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_msm-pshold.c | 56 ++++++++++++++++++++++++++ 3 files changed, 63 insertions(+) create mode 100644 drivers/sysreset/sysreset_msm-pshold.c diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 49c0787b26..30ff9e576d 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -235,6 +235,12 @@ config SYSRESET_RAA215300 help Add support for the system reboot via the Renesas RAA215300 PMIC. +config SYSRESET_MSM_PSHOLD + bool "Support sysreset for Qualcomm SoCs via PSHOLD" + depends on ARCH_IPQ40XX + help + Add support for the system reboot on Qualcomm SoCs via PSHOLD. + endif endmenu diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index e0e732205d..da61dca8e2 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -28,4 +28,5 @@ obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o obj-$(CONFIG_$(SPL_TPL_)SYSRESET_AT91) += sysreset_at91.o obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o obj-$(CONFIG_SYSRESET_RAA215300) += sysreset_raa215300.o +obj-$(CONFIG_SYSRESET_MSM_PSHOLD) += sysreset_msm-pshold.o obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o diff --git a/drivers/sysreset/sysreset_msm-pshold.c b/drivers/sysreset/sysreset_msm-pshold.c new file mode 100644 index 0000000000..d25a412954 --- /dev/null +++ b/drivers/sysreset/sysreset_msm-pshold.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm PSHOLD reset driver + * + * Copyright (c) 2024 Sartura Ltd. + * + * Author: Robert Marko <robert.marko(a)sartura.hr> + * Based on the Linux msm-poweroff driver. + * + */ + +#include <common.h> +#include <dm.h> +#include <sysreset.h> +#include <asm/io.h> +#include <linux/delay.h> + +struct msm_pshold_priv { + phys_addr_t base; +}; + +static int msm_pshold_request(struct udevice *dev, enum sysreset_t type) +{ + struct msm_pshold_priv *priv = dev_get_priv(dev); + + writel(0, priv->base); + mdelay(10000); + + return 0; +} + +static struct sysreset_ops msm_pshold_ops = { + .request = msm_pshold_request, +}; + +static int msm_pshold_probe(struct udevice *dev) +{ + struct msm_pshold_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0; +} + +static const struct udevice_id msm_pshold_ids[] = { + { .compatible = "qcom,pshold", }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(msm_pshold) = { + .name = "msm_pshold", + .id = UCLASS_SYSRESET, + .of_match = msm_pshold_ids, + .probe = msm_pshold_probe, + .priv_auto = sizeof(struct msm_pshold_priv), + .ops = &msm_pshold_ops, +}; -- 2.44.0

2 1

[PATCH v2 0/3] Introduce NET_PREFER_ROM_MAC_ADDR config
by Detlev Casanova 23 Apr '24

23 Apr '24

When there is a MAC address mismatch between ROM and environment, u-boot chooses the one from the environment. This config allows to prefer the MAC address from the ROM instead of the environment. See the first commit message for details. Changes since v1: - Simplify implementation with a NET_PREFER_ROM_MAC_ADDR config Detlev Casanova (3): net: eth-uclass: Introduce NET_PREFER_ROM_MAC_ADDR configs/rock5b: Set NET_PREFER_ROM_MAC_ADDR to y net: eth-uclass: Add driver source possibility configs/rock5b-rk3588_defconfig | 1 + net/Kconfig | 7 +++++++ net/eth-uclass.c | 17 +++++++++++++---- 3 files changed, 21 insertions(+), 4 deletions(-) -- 2.43.2

2 7

[PATCH v2] usb: cdns3: gadget.c: Set fast access bit
by Ravi Gunasekaran 23 Apr '24

23 Apr '24

From: Aswath Govindraju <a-govindraju(a)ti.com> When the device port is in a low power state [U3/L2/Not Connected], accesses to usb device registers may take a long time. This could lead to potential core hang when the controller registers are accessed after the port is disabled by setting DEVDS field. Setting the fast register access bit ensures that the PHY clock is keeping up in active state. Therefore, set fast access bit to ensure the accesses to device registers are quick even in low power states. Signed-off-by: Aswath Govindraju <a-govindraju(a)ti.com> Signed-off-by: Ravi Gunasekaran <r-gunasekaran(a)ti.com> Reviewed-by: Roger Quadros <rogerq(a)kernel.org> --- v1 was posted and was reviewed as well. But it did not get merged. This change is present in upstream linux kernel as well. Upstream Linux kernel commit: b5148d946f45 ("usb: cdns3: gadget: set fast access bit") Changes since v1: ---------------- * Rebased to tip of -next * Added Reviewed-by tag v1: https://lore.kernel.org/u-boot/20230505121353.23486-1-r-gunasekaran@ti.com/ drivers/usb/cdns3/gadget.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c index 7aa0c6b2be..d11175dc5b 100644 --- a/drivers/usb/cdns3/gadget.c +++ b/drivers/usb/cdns3/gadget.c @@ -2325,6 +2325,9 @@ static void cdns3_gadget_config(struct cdns3_device *priv_dev) writel(USB_IEN_INIT, &regs->usb_ien); writel(USB_CONF_CLK2OFFDS | USB_CONF_L1DS, &regs->usb_conf); + /* Set the Fast access bit */ + writel(PUSB_PWR_FST_REG_ACCESS, &priv_dev->regs->usb_pwr); + cdns3_configure_dmult(priv_dev, NULL); cdns3_gadget_pullup(&priv_dev->gadget, 1); @@ -2383,6 +2386,7 @@ static int cdns3_gadget_udc_stop(struct usb_gadget *gadget) /* disable interrupt for device */ writel(0, &priv_dev->regs->usb_ien); + writel(0, &priv_dev->regs->usb_pwr); writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf); return ret; base-commit: bc39e06778168a34bb4e0a34fbee4edbde4414d8 -- 2.17.1

2 1

[RFC PATCH 1/1] net: dwc_eth_qos: mdio: Implement clause 45
by Philip Oberfichtner 23 Apr '24

23 Apr '24

Bevor this commit, only clause 22 access was possible. After this commit, clause 45 direct access will available as well. Note that there is a slight change of behavior: Before this commit, the C45E bit was set to whatever value was left in the register from the previous access. After this commit, we adopt the common practice of discerning C45 from C22 using the devad argument. Signed-off-by: Philip Oberfichtner <pro(a)denx.de> --- Notes: This patch is labeled RFC as there is a slight change of behavior (see commit message). I'm not sure in fact if this solution works for everybody - this is up for discussion! My implementation is tested on an Intel Elkhart lake SOC. Driver code for dwc_eth_qos_intel coming soon in a separate patch series. drivers/net/dwc_eth_qos.c | 66 ++++++++++++++++++++++++++------------- drivers/net/dwc_eth_qos.h | 1 + 2 files changed, 45 insertions(+), 22 deletions(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 86d989e244..64a9bff6bb 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -162,6 +162,25 @@ static int eqos_mdio_wait_idle(struct eqos_priv *eqos) 1000000, true); } +/* Bitmask common for mdio_read and mdio_write */ +#define EQOS_MDIO_BITFIELD(pa, rda, cr) \ + (pa << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) | \ + (rda << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) | \ + (cr << EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) | \ + EQOS_MAC_MDIO_ADDRESS_GB + +static u32 eqos_mdio_bitfield(struct eqos_priv *eqos, int addr, int devad, int reg) +{ + int cr = eqos->config->config_mac_mdio; + bool c22 = devad == MDIO_DEVAD_NONE ? true : false; + + if (c22) + return EQOS_MDIO_BITFIELD(addr, reg, cr); + else + return EQOS_MDIO_BITFIELD(addr, devad, cr) | + EQOS_MAC_MDIO_ADDRESS_C45E; +} + static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, int mdio_reg) { @@ -179,15 +198,17 @@ static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, } val = readl(&eqos->mac_regs->mdio_address); - val &= EQOS_MAC_MDIO_ADDRESS_SKAP | - EQOS_MAC_MDIO_ADDRESS_C45E; - val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) | - (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) | - (eqos->config->config_mac_mdio << - EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) | - (EQOS_MAC_MDIO_ADDRESS_GOC_READ << - EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) | - EQOS_MAC_MDIO_ADDRESS_GB; + val &= EQOS_MAC_MDIO_ADDRESS_SKAP; + + val |= eqos_mdio_bitfield(eqos, mdio_addr, mdio_devad, mdio_reg) | + EQOS_MAC_MDIO_ADDRESS_GOC_READ << + EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT; + + if (val & EQOS_MAC_MDIO_ADDRESS_C45E) { + writel(mdio_reg << EQOS_MAC_MDIO_DATA_RA_SHIFT, + &eqos->mac_regs->mdio_data); + } + writel(val, &eqos->mac_regs->mdio_address); udelay(eqos->config->mdio_wait); @@ -210,7 +231,8 @@ static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, int mdio_reg, u16 mdio_val) { struct eqos_priv *eqos = bus->priv; - u32 val; + u32 v_addr; + u32 v_data; int ret; debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev, @@ -222,20 +244,20 @@ static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, return ret; } - writel(mdio_val, &eqos->mac_regs->mdio_data); + v_addr = readl(&eqos->mac_regs->mdio_address); + v_addr &= EQOS_MAC_MDIO_ADDRESS_SKAP; + + v_addr |= eqos_mdio_bitfield(eqos, mdio_addr, mdio_devad, mdio_reg) | + EQOS_MAC_MDIO_ADDRESS_GOC_WRITE << + EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT; + + v_data = mdio_val; + if (v_addr & EQOS_MAC_MDIO_ADDRESS_C45E) + v_data |= mdio_reg << EQOS_MAC_MDIO_DATA_RA_SHIFT; - val = readl(&eqos->mac_regs->mdio_address); - val &= EQOS_MAC_MDIO_ADDRESS_SKAP | - EQOS_MAC_MDIO_ADDRESS_C45E; - val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) | - (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) | - (eqos->config->config_mac_mdio << - EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) | - (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE << - EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) | - EQOS_MAC_MDIO_ADDRESS_GB; - writel(val, &eqos->mac_regs->mdio_address); + writel(v_data, &eqos->mac_regs->mdio_data); + writel(v_addr, &eqos->mac_regs->mdio_address); udelay(eqos->config->mdio_wait); ret = eqos_mdio_wait_idle(eqos); diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index 8b3d0d464d..d6ed3830be 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -92,6 +92,7 @@ struct eqos_mac_regs { #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1) #define EQOS_MAC_MDIO_ADDRESS_GB BIT(0) +#define EQOS_MAC_MDIO_DATA_RA_SHIFT 16 #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff #define EQOS_MTL_REGS_BASE 0xd00 -- 2.39.2

2 1

[PATCH v2] rockchip: rv1108: Convert to OF_UPSTREAM
by Fabio Estevam 23 Apr '24

23 Apr '24

Instead of using the local rv1108 devicetree copies from U-Boot, let's convert the rv1108 boards to OF_UPSTREAM so that the upstream kernel devicetrees can be used instead. Tested on a rv1108-elgin-r1 board. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- Changes since v1: - Fixed typo in commit log. arch/arm/dts/rv1108-elgin-r1.dts | 59 ---- arch/arm/dts/rv1108-evb.dts | 79 ----- arch/arm/dts/rv1108.dtsi | 581 ------------------------------- arch/arm/mach-rockchip/Kconfig | 1 + configs/elgin-rv1108_defconfig | 2 +- configs/evb-rv1108_defconfig | 2 +- 6 files changed, 3 insertions(+), 721 deletions(-) delete mode 100644 arch/arm/dts/rv1108-elgin-r1.dts delete mode 100644 arch/arm/dts/rv1108-evb.dts delete mode 100644 arch/arm/dts/rv1108.dtsi diff --git a/arch/arm/dts/rv1108-elgin-r1.dts b/arch/arm/dts/rv1108-elgin-r1.dts deleted file mode 100644 index 83e8b3183847..000000000000 --- a/arch/arm/dts/rv1108-elgin-r1.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; - -#include "rv1108.dtsi" - -/ { - model = "Elgin RV1108 R1 board"; - compatible = "elgin,rv1108-elgin", "rockchip,rv1108"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x08000000>; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; -}; - -&emmc { - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_otg: otg-port { - status = "okay"; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer_pullup>; - status = "okay"; -}; - -&usb20_otg { - status = "okay"; -}; - -&pinctrl { - uart2m0 { - uart2m0_xfer_pullup: uart2m0-xfer-pullup { - rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <2 RK_PD1 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; - }; - }; -}; diff --git a/arch/arm/dts/rv1108-evb.dts b/arch/arm/dts/rv1108-evb.dts deleted file mode 100644 index c91776bc106e..000000000000 --- a/arch/arm/dts/rv1108-evb.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; - -#include "rv1108.dtsi" - -/ { - model = "Rockchip RV1108 Evaluation board"; - compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x08000000>; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - vcc5v0_otg: vcc5v0-otg-drv { - compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc5v0_otg"; - gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&gmac { - status = "okay"; - clock_in_out = <0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; -}; - -&saradc { - status = "okay"; -}; - -&sfc { - status = "okay"; - flash@0 { - compatible = "gd25q256","jedec,spi-nor"; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - spi-max-frequency = <96000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb20_otg { - vbus-supply = <&vcc5v0_otg>; - status = "okay"; -}; - -&usb_host_ehci { - status = "okay"; -}; - -&usb_host_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi deleted file mode 100644 index 215d88522587..000000000000 --- a/arch/arm/dts/rv1108.dtsi +++ /dev/null @@ -1,581 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/rv1108-cru.h> -#include <dt-bindings/pinctrl/rockchip.h> -/ { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "rockchip,rv1108"; - - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - spi0 = &sfc; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@102a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x102a0000 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - }; - - bus_intmem@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x2000>; - }; - - uart2: serial@10210000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10210000 0x100>; - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "disabled"; - }; - - uart1: serial@10220000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10220000 0x100>; - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart0: serial@10230000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10230000 0x100>; - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - grf: syscon@10300000 { - compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd"; - reg = <0x10300000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy: usb2-phy@100 { - compatible = "rockchip,rv1108-usb2phy"; - reg = <0x100 0x0c>; - clocks = <&cru SCLK_USBPHY>; - clock-names = "phyclk"; - #clock-cells = <0>; - clock-output-names = "usbphy"; - rockchip,usbgrf = <&usbgrf>; - status = "disabled"; - - u2phy_otg: otg-port { - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "otg-mux"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy_host: host-port { - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - saradc: saradc@1038c000 { - compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; - reg = <0x1038c000 0x100>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - #io-channel-cells = <1>; - clock-frequency = <1000000>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - status = "disabled"; - }; - - pmugrf: syscon@20060000 { - compatible = "rockchip,rv1108-pmugrf", "syscon"; - reg = <0x20060000 0x1000>; - }; - - usbgrf: syscon@202a0000 { - compatible = "rockchip,rv1108-usbgrf", "syscon"; - reg = <0x202a0000 0x1000>; - }; - - cru: clock-controller@20200000 { - compatible = "rockchip,rv1108-cru"; - reg = <0x20200000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - emmc: dwmmc@30110000 { - compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x30110000 0x4000>; - status = "disabled"; - }; - - sdio: dwmmc@30120000 { - compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x30120000 0x4000>; - status = "disabled"; - }; - - sdmmc: dwmmc@30130000 { - compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 100000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x30130000 0x4000>; - status = "disabled"; - }; - - usb_host_ehci: usb@30140000 { - compatible = "generic-ehci"; - reg = <0x30140000 0x20000>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - usb_host_ohci: usb@30160000 { - compatible = "generic-ohci"; - reg = <0x30160000 0x20000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - usb20_otg: usb@30180000 { - compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x30180000 0x40000>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - g-use-dma; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - sfc: sfc@301c0000 { - compatible = "rockchip,sfc"; - reg = <0x301c0000 0x200>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - pinctrl-0 = <&sfc_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - gmac: ethernet@30200000 { - compatible = "rockchip,rv1108-gmac"; - reg = <0x30200000 0x10000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_MAC>, - <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, - <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, - <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; - clock-names = "stmmaceth", - "mac_clk_rx", "mac_clk_tx", - "clk_mac_ref", "clk_mac_refout", - "aclk_mac", "pclk_mac"; - pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins>; - phy-mode = "rmii"; - max-speed = <100>; - status = "disabled"; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x1000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rv1108-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@20030000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20030000 0x100>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@10310000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10310000 0x100>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@10320000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10320000 0x100>; - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@10330000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10330000 0x100>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { - drive-strength = <12>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { - drive-strength = <4>; - }; - - pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - gmac { - rmii_pins: rmii-pins { - rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>, - <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>, - <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>, - <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; - }; - }; - - i2c2m1 { - i2c2m1_xfer: i2c2m1-xfer { - rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>; - }; - - i2c2m1_gpio: i2c2m1-gpio { - rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c2m05v { - i2c2m05v_xfer: i2c2m05v-xfer { - rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>; - }; - - i2c2m05v_gpio: i2c2m05v-gpio { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - sfc { - sfc_pins: sfc-pins { - rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>, - <2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>, - <2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>, - <2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>, - <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, - <2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; - }; - - emmc_pwren: emmc-pwren { - rockchip,pins = <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, - <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts_gpio: uart0-rts-gpio { - rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, - <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart01rts: uart1-rts { - rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2m0 { - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2m1 { - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>, - <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - uart2_5v { - uart2_5v_cts: uart2_5v-cts { - rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart2_5v_rts: uart2_5v-rts { - rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 4f22d9bde9f9..b4a10be00249 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -343,6 +343,7 @@ config ROCKCHIP_RV1108 bool "Support Rockchip RV1108" select CPU_V7A imply ROCKCHIP_COMMON_BOARD + imply OF_UPSTREAM help The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 and a DSP. diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig index 446c9c9b7aca..140429f84d29 100644 --- a/configs/elgin-rv1108_defconfig +++ b/configs/elgin-rv1108_defconfig @@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rv1108-elgin-r1" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1108-elgin-r1" CONFIG_ROCKCHIP_RV1108=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 CONFIG_TARGET_ELGIN_RV1108=y diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index 1c62149a9b57..afc0ce4a0929 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -5,7 +5,7 @@ CONFIG_TEXT_BASE=0x60000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 -CONFIG_DEFAULT_DEVICE_TREE="rv1108-evb" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1108-evb" CONFIG_ROCKCHIP_RV1108=y CONFIG_DEBUG_UART_BASE=0x10210000 CONFIG_DEBUG_UART_CLOCK=24000000 -- 2.34.1

1 0

[PATCH] rockchip: rv1108: Convert to OF_UPSTREAM
by Fabio Estevam 23 Apr '24

23 Apr '24

Instead of using the local rv1108 devicetree copies from U-Boot, let's convert the rv11008 board to OF_UPSTREAM so that the upstream kernel devicetrees can be used instead. Tested on a rv1108-elgin-r1 board. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- arch/arm/dts/rv1108-elgin-r1.dts | 59 ---- arch/arm/dts/rv1108-evb.dts | 79 ----- arch/arm/dts/rv1108.dtsi | 581 ------------------------------- arch/arm/mach-rockchip/Kconfig | 1 + configs/elgin-rv1108_defconfig | 2 +- configs/evb-rv1108_defconfig | 2 +- 6 files changed, 3 insertions(+), 721 deletions(-) delete mode 100644 arch/arm/dts/rv1108-elgin-r1.dts delete mode 100644 arch/arm/dts/rv1108-evb.dts delete mode 100644 arch/arm/dts/rv1108.dtsi diff --git a/arch/arm/dts/rv1108-elgin-r1.dts b/arch/arm/dts/rv1108-elgin-r1.dts deleted file mode 100644 index 83e8b3183847..000000000000 --- a/arch/arm/dts/rv1108-elgin-r1.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; - -#include "rv1108.dtsi" - -/ { - model = "Elgin RV1108 R1 board"; - compatible = "elgin,rv1108-elgin", "rockchip,rv1108"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x08000000>; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; -}; - -&emmc { - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_otg: otg-port { - status = "okay"; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer_pullup>; - status = "okay"; -}; - -&usb20_otg { - status = "okay"; -}; - -&pinctrl { - uart2m0 { - uart2m0_xfer_pullup: uart2m0-xfer-pullup { - rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <2 RK_PD1 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; - }; - }; -}; diff --git a/arch/arm/dts/rv1108-evb.dts b/arch/arm/dts/rv1108-evb.dts deleted file mode 100644 index c91776bc106e..000000000000 --- a/arch/arm/dts/rv1108-evb.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; - -#include "rv1108.dtsi" - -/ { - model = "Rockchip RV1108 Evaluation board"; - compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x08000000>; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - vcc5v0_otg: vcc5v0-otg-drv { - compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc5v0_otg"; - gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&gmac { - status = "okay"; - clock_in_out = <0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; -}; - -&saradc { - status = "okay"; -}; - -&sfc { - status = "okay"; - flash@0 { - compatible = "gd25q256","jedec,spi-nor"; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - spi-max-frequency = <96000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb20_otg { - vbus-supply = <&vcc5v0_otg>; - status = "okay"; -}; - -&usb_host_ehci { - status = "okay"; -}; - -&usb_host_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi deleted file mode 100644 index 215d88522587..000000000000 --- a/arch/arm/dts/rv1108.dtsi +++ /dev/null @@ -1,581 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/rv1108-cru.h> -#include <dt-bindings/pinctrl/rockchip.h> -/ { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "rockchip,rv1108"; - - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - spi0 = &sfc; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@102a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x102a0000 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - }; - - bus_intmem@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x2000>; - }; - - uart2: serial@10210000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10210000 0x100>; - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "disabled"; - }; - - uart1: serial@10220000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10220000 0x100>; - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart0: serial@10230000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10230000 0x100>; - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - grf: syscon@10300000 { - compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd"; - reg = <0x10300000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy: usb2-phy@100 { - compatible = "rockchip,rv1108-usb2phy"; - reg = <0x100 0x0c>; - clocks = <&cru SCLK_USBPHY>; - clock-names = "phyclk"; - #clock-cells = <0>; - clock-output-names = "usbphy"; - rockchip,usbgrf = <&usbgrf>; - status = "disabled"; - - u2phy_otg: otg-port { - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "otg-mux"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy_host: host-port { - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - saradc: saradc@1038c000 { - compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; - reg = <0x1038c000 0x100>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - #io-channel-cells = <1>; - clock-frequency = <1000000>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - status = "disabled"; - }; - - pmugrf: syscon@20060000 { - compatible = "rockchip,rv1108-pmugrf", "syscon"; - reg = <0x20060000 0x1000>; - }; - - usbgrf: syscon@202a0000 { - compatible = "rockchip,rv1108-usbgrf", "syscon"; - reg = <0x202a0000 0x1000>; - }; - - cru: clock-controller@20200000 { - compatible = "rockchip,rv1108-cru"; - reg = <0x20200000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - emmc: dwmmc@30110000 { - compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x30110000 0x4000>; - status = "disabled"; - }; - - sdio: dwmmc@30120000 { - compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x30120000 0x4000>; - status = "disabled"; - }; - - sdmmc: dwmmc@30130000 { - compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 100000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x30130000 0x4000>; - status = "disabled"; - }; - - usb_host_ehci: usb@30140000 { - compatible = "generic-ehci"; - reg = <0x30140000 0x20000>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - usb_host_ohci: usb@30160000 { - compatible = "generic-ohci"; - reg = <0x30160000 0x20000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - usb20_otg: usb@30180000 { - compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x30180000 0x40000>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - g-use-dma; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - sfc: sfc@301c0000 { - compatible = "rockchip,sfc"; - reg = <0x301c0000 0x200>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - pinctrl-0 = <&sfc_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - gmac: ethernet@30200000 { - compatible = "rockchip,rv1108-gmac"; - reg = <0x30200000 0x10000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_MAC>, - <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, - <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, - <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; - clock-names = "stmmaceth", - "mac_clk_rx", "mac_clk_tx", - "clk_mac_ref", "clk_mac_refout", - "aclk_mac", "pclk_mac"; - pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins>; - phy-mode = "rmii"; - max-speed = <100>; - status = "disabled"; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x1000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rv1108-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@20030000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20030000 0x100>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@10310000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10310000 0x100>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@10320000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10320000 0x100>; - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@10330000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10330000 0x100>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { - drive-strength = <12>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { - drive-strength = <4>; - }; - - pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - gmac { - rmii_pins: rmii-pins { - rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>, - <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>, - <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>, - <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; - }; - }; - - i2c2m1 { - i2c2m1_xfer: i2c2m1-xfer { - rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>; - }; - - i2c2m1_gpio: i2c2m1-gpio { - rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c2m05v { - i2c2m05v_xfer: i2c2m05v-xfer { - rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>; - }; - - i2c2m05v_gpio: i2c2m05v-gpio { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - sfc { - sfc_pins: sfc-pins { - rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>, - <2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>, - <2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>, - <2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>, - <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, - <2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; - }; - - emmc_pwren: emmc-pwren { - rockchip,pins = <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, - <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts_gpio: uart0-rts-gpio { - rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, - <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart01rts: uart1-rts { - rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2m0 { - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2m1 { - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>, - <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - uart2_5v { - uart2_5v_cts: uart2_5v-cts { - rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart2_5v_rts: uart2_5v-rts { - rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 4f22d9bde9f9..b4a10be00249 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -343,6 +343,7 @@ config ROCKCHIP_RV1108 bool "Support Rockchip RV1108" select CPU_V7A imply ROCKCHIP_COMMON_BOARD + imply OF_UPSTREAM help The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 and a DSP. diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig index 446c9c9b7aca..140429f84d29 100644 --- a/configs/elgin-rv1108_defconfig +++ b/configs/elgin-rv1108_defconfig @@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rv1108-elgin-r1" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1108-elgin-r1" CONFIG_ROCKCHIP_RV1108=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 CONFIG_TARGET_ELGIN_RV1108=y diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index 1c62149a9b57..afc0ce4a0929 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -5,7 +5,7 @@ CONFIG_TEXT_BASE=0x60000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 -CONFIG_DEFAULT_DEVICE_TREE="rv1108-evb" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1108-evb" CONFIG_ROCKCHIP_RV1108=y CONFIG_DEBUG_UART_BASE=0x10210000 CONFIG_DEBUG_UART_CLOCK=24000000 -- 2.34.1

1 0

[PATCH v4 0/7] Add SE HMBSC board support
by Sumit Garg 23 Apr '24

23 Apr '24

SE HMIBSC board is based on Qcom APQ8016 SoC. One of the major difference from db410c is serial port where HMIBSC board uses UART1 as the debug console with an RS232 port, patch #2 - #5 adds corresponding driver support. Patch #6 adds main HMIBSC board specific bits, features: - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306) - 2GiB RAM - 64GiB eMMC, SD slot - WiFi and Bluetooth - 2x Host, 1x Device USB port - HDMI - Discrete TPM2 chip over SPI Features enabled in U-Boot: - RAUC updates (refer [2] for more details) - Environment protection - USB based ethernet adaptors Feedback is very much welcome. Changes in v4: - Rebased on top of qcom-main [4]. - Split out board DTS patch as #6. - Convert to text based environment as hmibsc.env. - MMC regression has been reported for qcom-main branch here [5]. - Collected further review tag. Changes in v3: - Rebased on top of qcom-next [1]. - Collected some review tags. - Incorporated misc. comments from Caleb and Stephen. - Split patch#4 as requested. - Linux HMIBSC board DTS has already been reviewed here [3], I have incorporated that for U-Boot too. Changes in v2: - Rebased on top on qcom-next [1]. - Added patch#1 as a fix for generic qcom board support. - Added patch#4 to enable driving GPIO pins based on pinctrl configuration. This replaces the custom GPIO configuration. - Added proper DTS file for HMIBSC board based on Linux DT pattern. - Merged board support patches into a single patch#5. [1] https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-n… [2] https://rauc.readthedocs.io/en/latest/ [3] https://lore.kernel.org/linux-kernel/20240403043416.3800259-4-sumit.garg@li… [4] https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-m… [5] https://lore.kernel.org/all/CAFA6WYO+3VroUdFUVH390taViQX8pMQrOQDTSn0yU6BD5Y… Sumit Garg (7): qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default apq8016: Add support for UART1 clocks and pinmux serial_msm: Enable RS232 flow control pinctrl: qcom: Add support for driving GPIO pins output pinctrl: qcom: apq8016: Add GPIO pinctrl function arm: dts: qcom: Add Schneider HMIBSC board dts board: add support for Schneider HMIBSC board arch/arm/Kconfig | 2 +- arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++++++++++++++++++++++ board/schneider/hmibsc/MAINTAINERS | 6 + board/schneider/hmibsc/hmibsc.env | 40 ++ configs/hmibsc_defconfig | 87 ++++ doc/board/index.rst | 1 + doc/board/schneider/hmibsc.rst | 45 ++ doc/board/schneider/index.rst | 9 + drivers/clk/qcom/clock-apq8016.c | 38 +- drivers/pinctrl/qcom/pinctrl-apq8016.c | 2 + drivers/pinctrl/qcom/pinctrl-qcom.c | 25 +- drivers/serial/serial_msm.c | 24 +- include/configs/hmibsc.h | 16 + 13 files changed, 760 insertions(+), 26 deletions(-) create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts create mode 100644 board/schneider/hmibsc/MAINTAINERS create mode 100644 board/schneider/hmibsc/hmibsc.env create mode 100644 configs/hmibsc_defconfig create mode 100644 doc/board/schneider/hmibsc.rst create mode 100644 doc/board/schneider/index.rst create mode 100644 include/configs/hmibsc.h -- 2.34.1

3 11

[PATCH v2 0/3] riscv: Rename spl_soc_init() to spl_dram_init()
by lukas.funke-oss＠weidmueller.com 23 Apr '24

23 Apr '24

From: Lukas Funke <lukas.funke(a)weidmueller.com> This patch series renames spl_soc_init() to spl_dram_init() since the purpose of the function is to initialization the DRAM on sifive/starfive boards. spl_dram_init() is a commonly used function for this purpose. Changes in v2: - capitalized acronym DRAM Lukas Funke (3): arch: riscv: Rename spl_soc_init() to spl_dram_init() board: sifive: Call spl_dram_init() for DRAM initialization board: starfive: Call spl_dram_init() for DRAM initialization arch/riscv/cpu/fu540/spl.c | 2 +- arch/riscv/cpu/fu740/spl.c | 2 +- arch/riscv/cpu/jh7110/spl.c | 2 +- arch/riscv/include/asm/arch-fu540/spl.h | 2 +- arch/riscv/include/asm/arch-fu740/spl.h | 2 +- arch/riscv/include/asm/arch-jh7110/spl.h | 2 +- board/sifive/unleashed/spl.c | 4 ++-- board/sifive/unmatched/spl.c | 4 ++-- board/starfive/visionfive2/spl.c | 4 ++-- 9 files changed, 12 insertions(+), 12 deletions(-) -- 2.30.2

2 4

[PATCH] board: sl28: move to OF_UPSTREAM
by Michael Walle 23 Apr '24

23 Apr '24

Use the new device devicetree files in dts/upstream/ and delete the old ones. Still keep the -u-boot.dtsi with all u-boot specifics around. There is one catch and that is fsl-ls1028a-kontron-sl28-var3.dts which is not available upstream (yet!). For now, the base dts is used for this variant as this only differ in the compatible and the (human readable) model name. Signed-off-by: Michael Walle <michael(a)walle.cc> --- I'll send a patch to linux to add the var3.dts, then I'll add the correct var3 dts again. --- .../arm/dts/fsl-ls1028a-kontron-sl28-var1.dts | 59 ---- .../arm/dts/fsl-ls1028a-kontron-sl28-var2.dts | 65 ---- .../arm/dts/fsl-ls1028a-kontron-sl28-var3.dts | 15 - .../arm/dts/fsl-ls1028a-kontron-sl28-var4.dts | 47 --- arch/arm/dts/fsl-ls1028a-kontron-sl28.dts | 308 ------------------ board/kontron/sl28/spl.c | 11 +- configs/kontron_sl28_defconfig | 5 +- 7 files changed, 8 insertions(+), 502 deletions(-) delete mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts delete mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts delete mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts delete mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts delete mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28.dts diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts deleted file mode 100644 index 7cd29ab970..0000000000 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for the Kontron SMARC-sAL28 board. - * - * This is for the network variant 1 which has one ethernet port. It is - * different than the base variant, which also has one port, but here the - * port is connected via RGMII. This port is not TSN aware. - * None of the four SerDes lanes are used by the module, instead they are - * all led out to the carrier for customer use. - * - * Copyright (C) 2021 Michael Walle <michael(a)walle.cc> - * - */ - -/dts-v1/; -#include "fsl-ls1028a-kontron-sl28.dts" -#include <dt-bindings/net/qca-ar803x.h> - -/ { - model = "Kontron SMARC-sAL28 (4 Lanes)"; - compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a"; -}; - -&enetc_mdio_pf3 { - /* Delete unused phy node */ - /delete-node/ ethernet-phy@5; - - phy0: ethernet-phy@4 { - reg = <0x4>; - eee-broken-1000t; - eee-broken-100tx; - qca,clk-out-frequency = <125000000>; - qca,clk-out-strength = <AR803X_STRENGTH_FULL>; - qca,keep-pll-enabled; - vddio-supply = <&vddio>; - - vddio: vddio-regulator { - regulator-name = "VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddh: vddh-regulator { - regulator-name = "VDDH"; - }; - }; -}; - -&enetc_port0 { - status = "disabled"; - /* Delete the phy-handle to the old phy0 label */ - /delete-property/ phy-handle; -}; - -&enetc_port1 { - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts deleted file mode 100644 index 330e34f933..0000000000 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for the Kontron SMARC-sAL28 board. - * - * This is for the network variant 2 which has two ethernet ports. These - * ports are connected to the internal switch. - * - * Copyright (C) 2021 Michael Walle <michael(a)walle.cc> - * - */ - -/dts-v1/; -#include "fsl-ls1028a-kontron-sl28.dts" - -/ { - model = "Kontron SMARC-sAL28 (TSN-on-module)"; - compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a"; -}; - -&enetc_mdio_pf3 { - phy1: ethernet-phy@4 { - reg = <0x4>; - eee-broken-1000t; - eee-broken-100tx; - }; -}; - -&enetc_port0 { - status = "disabled"; - /* - * In the base device tree the PHY at address 5 was assigned for - * this port. On this module this PHY is connected to a switch - * port instead. Therefore, delete the phy-handle property here. - */ - /delete-property/ phy-handle; -}; - -&enetc_port2 { - status = "okay"; -}; - -&mscc_felix { - status = "okay"; -}; - -&mscc_felix_port0 { - label = "swp0"; - managed = "in-band-status"; - phy-handle = <&phy0>; - phy-mode = "sgmii"; - status = "okay"; -}; - -&mscc_felix_port1 { - label = "swp1"; - managed = "in-band-status"; - phy-handle = <&phy1>; - phy-mode = "sgmii"; - status = "okay"; -}; - -&mscc_felix_port4 { - ethernet = <&enetc_port2>; - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts deleted file mode 100644 index 0c8b2af41a..0000000000 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for the Kontron SMARC-sAL28 board. - * - * Copyright (C) 2019 Michael Walle <michael(a)walle.cc> - * - */ - -/dts-v1/; -#include "fsl-ls1028a-kontron-sl28.dts" - -/ { - model = "Kontron SMARC-sAL28 (Single PHY)"; - compatible = "kontron,sl28-var3", "kontron,sl28", "fsl,ls1028a"; -}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts deleted file mode 100644 index 9b5e92fb75..0000000000 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for the Kontron SMARC-sAL28 board. - * - * This is for the network variant 4 which has two ethernet ports. It - * extends the base and provides one more port connected via RGMII. - * - * Copyright (C) 2021 Michael Walle <michael(a)walle.cc> - * - */ - -/dts-v1/; -#include "fsl-ls1028a-kontron-sl28.dts" -#include <dt-bindings/net/qca-ar803x.h> - -/ { - model = "Kontron SMARC-sAL28 (Dual PHY)"; - compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a"; -}; - -&enetc_mdio_pf3 { - phy1: ethernet-phy@4 { - reg = <0x4>; - eee-broken-1000t; - eee-broken-100tx; - qca,clk-out-frequency = <125000000>; - qca,clk-out-strength = <AR803X_STRENGTH_FULL>; - qca,keep-pll-enabled; - vddio-supply = <&vddio>; - - vddio: vddio-regulator { - regulator-name = "VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddh: vddh-regulator { - regulator-name = "VDDH"; - }; - }; -}; - -&enetc_port1 { - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts deleted file mode 100644 index ab713b4949..0000000000 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts +++ /dev/null @@ -1,308 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for the Kontron SMARC-sAL28 board. - * - * Copyright (C) 2021 Michael Walle <michael(a)walle.cc> - * - */ - -/dts-v1/; -#include "fsl-ls1028a.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> - -/ { - model = "Kontron SMARC-sAL28"; - compatible = "kontron,sl28", "fsl,ls1028a"; - - aliases { - crypto = &crypto; - serial0 = &duart0; - serial1 = &duart1; - serial2 = &lpuart1; - spi0 = &fspi; - spi1 = &dspi2; - mmc0 = &esdhc1; - mmc1 = &esdhc; - rtc0 = &rtc; - rtc1 = &ftm_alarm0; - }; - - buttons0 { - compatible = "gpio-keys"; - - power-button { - interrupts-extended = <&sl28cpld_intc - 4 IRQ_TYPE_EDGE_BOTH>; - linux,code = <KEY_POWER>; - label = "Power"; - }; - - sleep-button { - interrupts-extended = <&sl28cpld_intc - 5 IRQ_TYPE_EDGE_BOTH>; - linux,code = <KEY_SLEEP>; - label = "Sleep"; - }; - }; - - buttons1 { - compatible = "gpio-keys-polled"; - poll-interval = <200>; - - lid-switch { - linux,input-type = <EV_SW>; - linux,code = <SW_LID>; - gpios = <&sl28cpld_gpio3 4 GPIO_ACTIVE_LOW>; - label = "Lid"; - }; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&can0 { - status = "okay"; -}; - -&dspi2 { - status = "okay"; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&enetc_mdio_pf3 { - phy0: ethernet-phy@5 { - reg = <0x5>; - eee-broken-1000t; - eee-broken-100tx; - }; -}; - -&enetc_port0 { - phy-handle = <&phy0>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "okay"; -}; - -&esdhc { - sd-uhs-sdr104; - sd-uhs-sdr50; - sd-uhs-sdr25; - sd-uhs-sdr12; - status = "okay"; -}; - -&esdhc1 { - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - status = "okay"; -}; - -&fspi { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - m25p,fast-read; - spi-max-frequency = <133000000>; - reg = <0>; - /* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */ - spi-rx-bus-width = <2>; /* 2 SPI Rx lines */ - spi-tx-bus-width = <1>; /* 1 SPI Tx line */ - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x000000 0x010000>; - label = "rcw"; - read-only; - }; - - partition@10000 { - reg = <0x010000 0x1d0000>; - label = "failsafe bootloader"; - read-only; - }; - - partition@200000 { - reg = <0x200000 0x010000>; - label = "configuration store"; - }; - - partition@210000 { - reg = <0x210000 0x1d0000>; - label = "bootloader"; - }; - - partition@3e0000 { - reg = <0x3e0000 0x020000>; - label = "bootloader environment"; - }; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "TDO", "TCK", - "", "", "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - "", "", "", "", "", "", "TMS", "TDI", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c0 { - status = "okay"; - - rtc: rtc@32 { - compatible = "microcrystal,rv8803"; - reg = <0x32>; - }; - - sl28cpld@4a { - compatible = "kontron,sl28cpld"; - reg = <0x4a>; - #address-cells = <1>; - #size-cells = <0>; - - watchdog@4 { - compatible = "kontron,sl28cpld-wdt"; - reg = <0x4>; - kontron,assert-wdt-timeout-pin; - }; - - hwmon@b { - compatible = "kontron,sl28cpld-fan"; - reg = <0xb>; - }; - - sl28cpld_pwm0: pwm@c { - compatible = "kontron,sl28cpld-pwm"; - reg = <0xc>; - #pwm-cells = <2>; - }; - - sl28cpld_pwm1: pwm@e { - compatible = "kontron,sl28cpld-pwm"; - reg = <0xe>; - #pwm-cells = <2>; - }; - - sl28cpld_gpio0: gpio@10 { - compatible = "kontron,sl28cpld-gpio"; - reg = <0x10>; - interrupts-extended = <&gpio2 6 - IRQ_TYPE_EDGE_FALLING>; - - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "GPIO0_CAM0_PWR_N", "GPIO1_CAM1_PWR_N", - "GPIO2_CAM0_RST_N", "GPIO3_CAM1_RST_N", - "GPIO4_HDA_RST_N", "GPIO5_PWM_OUT", - "GPIO6_TACHIN", "GPIO7"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sl28cpld_gpio1: gpio@15 { - compatible = "kontron,sl28cpld-gpio"; - reg = <0x15>; - interrupts-extended = <&gpio2 6 - IRQ_TYPE_EDGE_FALLING>; - - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "GPIO8", "GPIO9", "GPIO10", "GPIO11", - "", "", "", ""; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sl28cpld_gpio2: gpio@1a { - compatible = "kontron,sl28cpld-gpo"; - reg = <0x1a>; - - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "LCD0 voltage enable", - "LCD0 backlight enable", - "eMMC reset", "LVDS bridge reset", - "LVDS bridge power-down", - "SDIO power enable", - "", ""; - }; - - sl28cpld_gpio3: gpio@1b { - compatible = "kontron,sl28cpld-gpi"; - reg = <0x1b>; - - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "Power button", "Force recovery", "Sleep", - "Battery low", "Lid state", "Charging", - "Charger present", ""; - }; - - sl28cpld_intc: interrupt-controller@1c { - compatible = "kontron,sl28cpld-intc"; - reg = <0x1c>; - interrupts-extended = <&gpio2 6 - IRQ_TYPE_EDGE_FALLING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&lpuart1 { - status = "okay"; -}; diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c index ffaf517a8b..80acde7495 100644 --- a/board/kontron/sl28/spl.c +++ b/board/kontron/sl28/spl.c @@ -47,15 +47,14 @@ int board_fit_config_name_match(const char *name) switch (variant) { case 1: - return strcmp(name, "fsl-ls1028a-kontron-sl28-var1"); + return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28-var1"); case 2: - return strcmp(name, "fsl-ls1028a-kontron-sl28-var2"); - case 3: - return strcmp(name, "fsl-ls1028a-kontron-sl28-var3"); + return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28-var2"); case 4: - return strcmp(name, "fsl-ls1028a-kontron-sl28-var4"); + return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28-var4"); + case 3: default: - return strcmp(name, "fsl-ls1028a-kontron-sl28"); + return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28"); } } diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 639c5c6ce1..adc1d501ba 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -11,7 +11,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800eff0 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x3e0000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-kontron-sl28" +CONFIG_DEFAULT_DEVICE_TREE="freescale/fsl-ls1028a-kontron-sl28" CONFIG_SPL_TEXT_BASE=0x18010000 CONFIG_SYS_FSL_SDHC_CLK_DIV=1 CONFIG_OF_LIBFDT_OVERLAY=y @@ -73,7 +73,8 @@ CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_RNG=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="fsl-ls1028a-kontron-sl28 fsl-ls1028a-kontron-sl28-var1 fsl-ls1028a-kontron-sl28-var2 fsl-ls1028a-kontron-sl28-var3 fsl-ls1028a-kontron-sl28-var4" +CONFIG_OF_UPSTREAM=y +CONFIG_OF_LIST="freescale/fsl-ls1028a-kontron-sl28 freescale/fsl-ls1028a-kontron-sl28-var1 freescale/fsl-ls1028a-kontron-sl28-var2 freescale/fsl-ls1028a-kontron-sl28-var4" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -- 2.39.2

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[PATCH 0/9] qcom: RBx fixes and USB support
by Caleb Connolly 23 Apr '24

23 Apr '24

This series is a few loosely connected patches to get the RB1 and 2 boards booting from USB with upstream U-Boot, and a few preperatory patches for rb5. Unfortunately the RB5 board requires a regulator on the RPMh peripheral to be turned on for the USB VBUS rail. Support for this will be added in future patches. * Add a few missing compatible strings for sm6115/sm8250 * Fix the femto-v2 HS USB phy used on sm8250 * Fix USB role selection on RB2 (without breaking Linux!) * Pick a value for CONFIG_SYS_LOAD_ADDR that won't cause a null pointer on most boards * Fix EFI booting by generating SMBIOS tables --- Caleb Connolly (9): gpio: qcom_pmic: add pm6125 gpio: qcom_pmic: add pm8150l iommu: qcom-smmu: add qcom generic compatible phy: qcom: snps-femto-v2: drop clocks arm: dts: qrb4210-rb2-u-boot: add u-boot fixups mach-snapdragon: implement ft_board_setup() for USB role selection qcom_defconfig: enable OF_BOARD_SETUP qcom_defconfig: define safe default SYS_LOAD_ADDR qcom_defconfig: generate SMBIOS tables arch/arm/dts/qrb4210-rb2-u-boot.dtsi | 6 ++++++ arch/arm/mach-snapdragon/of_fixup.c | 20 ++++++++++++++++++++ configs/qcom_defconfig | 5 +++-- drivers/gpio/qcom_pmic_gpio.c | 2 ++ drivers/iommu/qcom-hyp-smmu.c | 1 + drivers/phy/qcom/phy-qcom-snps-femto-v2.c | 14 -------------- 6 files changed, 32 insertions(+), 16 deletions(-) --- base-commit: d5460b082cd6afd0e07c0ec0e5a82d1af8dc09f7 // Caleb (they/them)

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