April 2024 - U-Boot

Re: [PATCH v2 11/11] net: dwc_eth_qos: Add support for st, ext-phyclk property
by Christophe ROULLIER 19 Apr '24

19 Apr '24

> -----Original Message----- > From: Marek Vasut<marex(a)denx.de> > Sent: Tuesday, March 26, 2024 1:08 PM > To:u-boot@lists.denx.de > Cc: Marek Vasut<marex(a)denx.de>; Christophe ROULLIER<christophe.roullier(a)st.com>; Joe Hershberger<joe.hershberger(a)ni.com>; Patrice CHOTARD - foss<patrice.chotard(a)foss.st.com>; Patrick DELAUNAY - foss<patrick.delaunay(a)foss.st.com>; Ramon Fried<rfried.dev(a)gmail.com>;u-boot@dh-electronics.com;uboot-stm32@st-md-mailman.stormreply.com > Subject: [PATCH v2 11/11] net: dwc_eth_qos: Add support for st,ext-phyclk property > > The "st,ext-phyclk" property is a unification of "st,eth-clk-sel" > and "st,eth-ref-clk-sel" properties. All three properties define ETH CK clock direction, however: > - "st,eth-clk-sel" selects clock direction for GMII/RGMII mode > - "st,eth-ref-clk-sel" selects clock direction for RMII mode > - "st,ext-phyclk" selects clock direction for all RMII/GMII/RGMII modes The "st,ext-phyclk" is the preferrable property to use. > > Signed-off-by: Marek Vasut<marex(a)denx.de> > --- > Cc: Christophe Roullier<christophe.roullier(a)st.com> > Cc: Joe Hershberger<joe.hershberger(a)ni.com> > Cc: Patrice Chotard<patrice.chotard(a)foss.st.com> > Cc: Patrick Delaunay<patrick.delaunay(a)foss.st.com> > Cc: Ramon Fried<rfried.dev(a)gmail.com> > Cc:u-boot@dh-electronics.com > Cc:uboot-stm32@st-md-mailman.stormreply.com > --- > V2: New patch > --- > drivers/net/dwc_eth_qos_stm32.c | 30 +++++++++++++++++++++++++++--- > 1 file changed, 27 insertions(+), 3 deletions(-) > > diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index 435473f99a6..9ee82b54c62 100644 > --- a/drivers/net/dwc_eth_qos_stm32.c > +++ b/drivers/net/dwc_eth_qos_stm32.c > @@ -140,6 +140,8 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev, > const bool is_mp13 = device_is_compatible(dev, "st,stm32mp13-dwmac"); > /* Gigabit Ethernet 125MHz clock selection. */ > const bool eth_clk_sel = dev_read_bool(dev, "st,eth-clk-sel"); > + /* Ethernet clock source is RCC. */ > + const bool ext_phyclk = dev_read_bool(dev, "st,ext-phyclk"); > struct regmap *regmap; > u32 regmap_mask; > u32 value; > @@ -156,6 +158,12 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev, > dev_dbg(dev, "PHY_INTERFACE_MODE_MII\n"); > value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, > SYSCFG_PMCSETR_ETH_SEL_GMII_MII); > + /* > + * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only. > + * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and > + * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx > + * supports only MII, ETH_SELMII is not present. > + */ > if (!is_mp13) /* Select MII mode on STM32MP15xx */ > value |= SYSCFG_PMCSETR_ETH_SELMII; > break; > @@ -163,14 +171,25 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev, > dev_dbg(dev, "PHY_INTERFACE_MODE_GMII\n"); > value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, > SYSCFG_PMCSETR_ETH_SEL_GMII_MII); > - if (eth_clk_sel) > + /* > + * If eth_clk_sel is set, use internal ETH_CLKx clock from RCC, > + * otherwise use external clock from IO pin (requires matching > + * GPIO block AF setting of that pin). > + */ > + if (eth_clk_sel || ext_phyclk) > value |= SYSCFG_PMCSETR_ETH_CLK_SEL; > break; > case PHY_INTERFACE_MODE_RMII: > dev_dbg(dev, "PHY_INTERFACE_MODE_RMII\n"); > value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, > SYSCFG_PMCSETR_ETH_SEL_RMII); > - if (eth_ref_clk_sel) > + /* > + * If eth_ref_clk_sel is set, use internal clock from RCC, > + * otherwise use external clock from ETHn_RX_CLK/ETHn_REF_CLK > + * IO pin (requires matching GPIO block AF setting of that > + * pin). > + */ > + if (eth_ref_clk_sel || ext_phyclk) > value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL; > break; > case PHY_INTERFACE_MODE_RGMII: > @@ -180,7 +199,12 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev, > dev_dbg(dev, "PHY_INTERFACE_MODE_RGMII\n"); > value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, > SYSCFG_PMCSETR_ETH_SEL_RGMII); > - if (eth_clk_sel) > + /* > + * If eth_clk_sel is set, use internal ETH_CLKx clock from RCC, > + * otherwise use external clock from ETHx_CLK125 pin (requires > + * matching GPIO block AF setting of that pin). > + */ > + if (eth_clk_sel || ext_phyclk) > value |= SYSCFG_PMCSETR_ETH_CLK_SEL; > break; > default: > -- > 2.43.0 > Reviewed-by: Christophe ROULLIER <christophe.roullier(a)foss.st.com>

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Re: [PATCH v2 10/11] net: dwc_eth_qos: Add support of STM32MP13xx platform
by Christophe ROULLIER 19 Apr '24

19 Apr '24

> -----Original Message----- > From: Marek Vasut<marex(a)denx.de> > Sent: Tuesday, March 26, 2024 1:08 PM > To:u-boot@lists.denx.de > Cc: Christophe ROULLIER<christophe.roullier(a)st.com>; Patrice CHOTARD - foss<patrice.chotard(a)foss.st.com>; Marek Vasut<marex(a)denx.de>; Joe Hershberger<joe.hershberger(a)ni.com>; Patrick DELAUNAY - foss<patrick.delaunay(a)foss.st.com>; Ramon Fried<rfried.dev(a)gmail.com>;u-boot@dh-electronics.com;uboot-stm32@st-md-mailman.stormreply.com > Subject: [PATCH v2 10/11] net: dwc_eth_qos: Add support of STM32MP13xx platform > > From: Christophe Roullier<christophe.roullier(a)st.com> > > Add compatible "st,stm32mp13-dwmac" to manage STM32MP13 boards. > > Reviewed-by: Patrice Chotard<patrice.chotard(a)foss.st.com> > Signed-off-by: Christophe Roullier<christophe.roullier(a)st.com> > Signed-off-by: Marek Vasut<marex(a)denx.de> # Rebase, reshuffle, squash code > --- > Cc: Christophe Roullier<christophe.roullier(a)st.com> > Cc: Joe Hershberger<joe.hershberger(a)ni.com> > Cc: Patrice Chotard<patrice.chotard(a)foss.st.com> > Cc: Patrick Delaunay<patrick.delaunay(a)foss.st.com> > Cc: Ramon Fried<rfried.dev(a)gmail.com> > Cc:u-boot@dh-electronics.com > Cc:uboot-stm32@st-md-mailman.stormreply.com > --- > V2: Add RB from Patrice > --- > drivers/net/dwc_eth_qos.c | 4 ++++ > drivers/net/dwc_eth_qos.h | 1 + > drivers/net/dwc_eth_qos_stm32.c | 11 +++++++++++ > 3 files changed, 16 insertions(+) > > diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 203bfc0848c..e02317905e5 100644 > --- a/drivers/net/dwc_eth_qos.c > +++ b/drivers/net/dwc_eth_qos.c > @@ -1505,6 +1505,10 @@ static const struct udevice_id eqos_ids[] = { > }, > #endif > #if IS_ENABLED(CONFIG_DWC_ETH_QOS_STM32) > + { > + .compatible = "st,stm32mp13-dwmac", > + .data = (ulong)&eqos_stm32mp13_config > + }, > { > .compatible = "st,stm32mp1-dwmac", > .data = (ulong)&eqos_stm32mp15_config diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index bafd0d339fb..8b3d0d464d3 100644 > --- a/drivers/net/dwc_eth_qos.h > +++ b/drivers/net/dwc_eth_qos.h > @@ -290,5 +290,6 @@ int eqos_null_ops(struct udevice *dev); extern struct eqos_config eqos_imx_config; extern struct eqos_config eqos_rockchip_config; extern struct eqos_config eqos_qcom_config; > +extern struct eqos_config eqos_stm32mp13_config; > extern struct eqos_config eqos_stm32mp15_config; extern struct eqos_config eqos_jh7110_config; diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index 5a20fe5bea2..435473f99a6 100644 > --- a/drivers/net/dwc_eth_qos_stm32.c > +++ b/drivers/net/dwc_eth_qos_stm32.c > @@ -279,6 +279,17 @@ static struct eqos_ops eqos_stm32_ops = { > .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32 }; > > +struct eqos_config __maybe_unused eqos_stm32mp13_config = { > + .reg_access_always_ok = false, > + .mdio_wait = 10000, > + .swr_wait = 50, > + .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, > + .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, > + .axi_bus_width = EQOS_AXI_WIDTH_32, > + .interface = dev_read_phy_mode, > + .ops = &eqos_stm32_ops > +}; > + > struct eqos_config __maybe_unused eqos_stm32mp15_config = { > .reg_access_always_ok = false, > .mdio_wait = 10000, > -- > 2.43.0 > Reviewed-by: Christophe ROULLIER <christophe.roullier(a)foss.st.com>

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Re: [PATCH v2 09/11] net: dwc_eth_qos: Add DT parsing for STM32MP13xx platform
by Christophe ROULLIER 19 Apr '24

19 Apr '24

> -----Original Message----- > From: Marek Vasut<marex(a)denx.de> > Sent: Tuesday, March 26, 2024 1:08 PM > To:u-boot@lists.denx.de > Cc: Christophe ROULLIER<christophe.roullier(a)st.com>; Marek Vasut<marex(a)denx.de>; Joe Hershberger<joe.hershberger(a)ni.com>; Patrice CHOTARD - foss<patrice.chotard(a)foss.st.com>; Patrick DELAUNAY - foss<patrick.delaunay(a)foss.st.com>; Ramon Fried<rfried.dev(a)gmail.com>;u-boot@dh-electronics.com;uboot-stm32@st-md-mailman.stormreply.com > Subject: [PATCH v2 09/11] net: dwc_eth_qos: Add DT parsing for STM32MP13xx platform > > From: Christophe Roullier<christophe.roullier(a)st.com> > > Manage 2 ethernet instances, select which instance to configure with mask If mask is not present in DT, it is stm32mp15 platform. > > Signed-off-by: Christophe Roullier<christophe.roullier(a)st.com> > Signed-off-by: Marek Vasut<marex(a)denx.de> # Rework the code > --- > Cc: Christophe Roullier<christophe.roullier(a)st.com> > Cc: Joe Hershberger<joe.hershberger(a)ni.com> > Cc: Patrice Chotard<patrice.chotard(a)foss.st.com> > Cc: Patrick Delaunay<patrick.delaunay(a)foss.st.com> > Cc: Ramon Fried<rfried.dev(a)gmail.com> > Cc:u-boot@dh-electronics.com > Cc:uboot-stm32@st-md-mailman.stormreply.com > --- > V2: - Drop unrelated clock frequency validation > - Move "st,ext-phyclk" property support into separate patch > - This leaves only the regmap parts here > --- > drivers/net/dwc_eth_qos_stm32.c | 41 ++++++++++++++++++++++----------- > 1 file changed, 28 insertions(+), 13 deletions(-) > > diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index 0b13d01346b..5a20fe5bea2 100644 > --- a/drivers/net/dwc_eth_qos_stm32.c > +++ b/drivers/net/dwc_eth_qos_stm32.c > @@ -23,6 +23,7 @@ > #include <net.h> > #include <netdev.h> > #include <phy.h> > +#include <regmap.h> > #include <reset.h> > #include <syscon.h> > #include <wait_bit.h> > @@ -33,11 +34,16 @@ > > /* SYSCFG registers */ > #define SYSCFG_PMCSETR 0x04 > -#define SYSCFG_PMCCLRR 0x44 > +#define SYSCFG_PMCCLRR_MP13 0x08 > +#define SYSCFG_PMCCLRR_MP15 0x44 > + > +#define SYSCFG_PMCSETR_ETH1_MASK GENMASK(23, 16) > +#define SYSCFG_PMCSETR_ETH2_MASK GENMASK(31, 24) > > #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16) > #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17) > > +/* STM32MP15xx specific bit */ > #define SYSCFG_PMCSETR_ETH_SELMII BIT(20) > > #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) > @@ -130,23 +136,30 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev, { > /* Ethernet 50MHz RMII clock selection. */ > const bool eth_ref_clk_sel = dev_read_bool(dev, "st,eth-ref-clk-sel"); > + /* SoC is STM32MP13xx with two ethernet MACs */ > + const bool is_mp13 = device_is_compatible(dev, "st,stm32mp13-dwmac"); > /* Gigabit Ethernet 125MHz clock selection. */ > const bool eth_clk_sel = dev_read_bool(dev, "st,eth-clk-sel"); > - u8 *syscfg; > + struct regmap *regmap; > + u32 regmap_mask; > u32 value; > > - syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); > - if (!syscfg) > - return -ENODEV; > + regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscon"); > + if (IS_ERR(regmap)) > + return PTR_ERR(regmap); > + > + regmap_mask = dev_read_u32_index_default(dev, "st,syscon", 2, > + SYSCFG_PMCSETR_ETH1_MASK); > > switch (interface_type) { > case PHY_INTERFACE_MODE_MII: > dev_dbg(dev, "PHY_INTERFACE_MODE_MII\n"); > value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, > SYSCFG_PMCSETR_ETH_SEL_GMII_MII); > - value |= SYSCFG_PMCSETR_ETH_REF_CLK_SEL; > + if (!is_mp13) /* Select MII mode on STM32MP15xx */ > + value |= SYSCFG_PMCSETR_ETH_SELMII; > break; > - case PHY_INTERFACE_MODE_GMII: > + case PHY_INTERFACE_MODE_GMII: /* STM32MP15xx only */ > dev_dbg(dev, "PHY_INTERFACE_MODE_GMII\n"); > value = FIELD_PREP(SYSCFG_PMCSETR_ETH_SEL_MASK, > SYSCFG_PMCSETR_ETH_SEL_GMII_MII); @@ -177,13 +190,15 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev, > return -EINVAL; > } > > - /* clear and set ETH configuration bits */ > - writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII | > - SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL, > - syscfg + SYSCFG_PMCCLRR); > - writel(value, syscfg + SYSCFG_PMCSETR); > + /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */ > + value <<= ffs(regmap_mask) - ffs(SYSCFG_PMCSETR_ETH1_MASK); > > - return 0; > + /* Update PMCCLRR (clear register) */ > + regmap_write(regmap, is_mp13 ? > + SYSCFG_PMCCLRR_MP13 : SYSCFG_PMCCLRR_MP15, > + regmap_mask); > + > + return regmap_update_bits(regmap, SYSCFG_PMCSETR, regmap_mask, value); > } > > static int eqos_probe_resources_stm32(struct udevice *dev) > -- > 2.43.0 Reviewed-by: Christophe ROULLIER <christophe.roullier(a)foss.st.com>

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[PATCH v2 00/11] net: dwc_eth_qos: Clean up STM32 glue code and add STM32MP13xx support
by Marek Vasut 19 Apr '24

19 Apr '24

Split off STM32 glue code from the DWMAC driver into separate file, similar to what other SoCs already do, to avoid mixing the ST specifics with generic DWMAC core code. Clean the STM32 DWMAC board code which is currently duplicated in multiple board files, move it into the newly separated glue code, since the code is not board specific, it is only generic DT parsing and generic register programming. Add STM32MP13xx support based on ST downstream patches on top, although that part is mostly rewritten from scratch. Christophe Roullier (2): net: dwc_eth_qos: Add DT parsing for STM32MP13xx platform net: dwc_eth_qos: Add support of STM32MP13xx platform Marek Vasut (9): net: dwc_eth_qos: Split STM32 glue into separate file net: dwc_eth_qos: Rename eqos_stm32_config to eqos_stm32mp15_config net: dwc_eth_qos: Fold board_interface_eth_init into STM32 glue code net: dwc_eth_qos: Scrub ifdeffery net: dwc_eth_qos: Use FIELD_PREP for ETH_SEL bitfield net: dwc_eth_qos: Move log_debug statements on top of case block net: dwc_eth_qos: Use consistent logging prints net: dwc_eth_qos: Constify st,eth-* values parsed out of DT net: dwc_eth_qos: Add support for st,ext-phyclk property board/dhelectronics/dh_stm32mp1/board.c | 82 ------ board/st/stm32mp1/stm32mp1.c | 82 ------ drivers/net/Makefile | 1 + drivers/net/dwc_eth_qos.c | 171 +------------ drivers/net/dwc_eth_qos.h | 2 + drivers/net/dwc_eth_qos_stm32.c | 326 ++++++++++++++++++++++++ 6 files changed, 334 insertions(+), 330 deletions(-) create mode 100644 drivers/net/dwc_eth_qos_stm32.c Cc: Christophe Roullier <christophe.roullier(a)st.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Ramon Fried <rfried.dev(a)gmail.com> Cc: u-boot(a)dh-electronics.com Cc: uboot-stm32(a)st-md-mailman.stormreply.com -- 2.43.0

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Re: [PATCH v2 04/11] net: dwc_eth_qos: Scrub ifdeffery
by Christophe ROULLIER 19 Apr '24

19 Apr '24

> -----Original Message----- > From: Marek Vasut <marex(a)denx.de> > Sent: Tuesday, March 26, 2024 1:07 PM > To: u-boot(a)lists.denx.de > Cc: Marek Vasut <marex(a)denx.de>; Patrice CHOTARD - foss <patrice.chotard(a)foss.st.com>; Christophe ROULLIER <christophe.roullier(a)st.com>; Joe Hershberger <joe.hershberger(a)ni.com>; Patrick DELAUNAY - foss <patrick.delaunay(a)foss.st.com>; Ramon Fried <rfried.dev(a)gmail.com>; u-boot(a)dh-electronics.com; uboot-stm32(a)st-md-mailman.stormreply.com > Subject: [PATCH v2 04/11] net: dwc_eth_qos: Scrub ifdeffery > > Replace ifdef CONFIG_CLK with if (CONFIG_IS_ENABLED(CLK)) to improve code build coverage. Some of the functions printed debug("%s: OK\n", __func__); on exit with and without CLK enabled, some did not, make it consistent and print nothing if CLK is disabled. > > Reviewed-by: Patrice Chotard <patrice.chotard(a)foss.st.com> > Signed-off-by: Marek Vasut <marex(a)denx.de> > --- > Cc: Christophe Roullier <christophe.roullier(a)st.com> > Cc: Joe Hershberger <joe.hershberger(a)ni.com> > Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> > Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> > Cc: Ramon Fried <rfried.dev(a)gmail.com> > Cc: u-boot(a)dh-electronics.com > Cc: uboot-stm32(a)st-md-mailman.stormreply.com > --- > V2: Add RB from Patrice > --- > drivers/net/dwc_eth_qos_stm32.c | 25 ++++++++++++------------- > 1 file changed, 12 insertions(+), 13 deletions(-) > > diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index 7520a136ed0..d7ec0c9be36 100644 > --- a/drivers/net/dwc_eth_qos_stm32.c > +++ b/drivers/net/dwc_eth_qos_stm32.c > @@ -46,21 +46,22 @@ > > static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev) { -#ifdef CONFIG_CLK > - struct eqos_priv *eqos = dev_get_priv(dev); > + struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev); > + > + if (!CONFIG_IS_ENABLED(CLK)) > + return 0; > > return clk_get_rate(&eqos->clk_master_bus); > -#else > - return 0; > -#endif > } > > static int eqos_start_clks_stm32(struct udevice *dev) { -#ifdef CONFIG_CLK > - struct eqos_priv *eqos = dev_get_priv(dev); > + struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev); > int ret; > > + if (!CONFIG_IS_ENABLED(CLK)) > + return 0; > + > debug("%s(dev=%p):\n", __func__, dev); > > ret = clk_enable(&eqos->clk_master_bus); > @@ -89,12 +90,10 @@ static int eqos_start_clks_stm32(struct udevice *dev) > } > eqos->clk_ck_enabled = true; > } > -#endif > > debug("%s: OK\n", __func__); > return 0; > > -#ifdef CONFIG_CLK > err_disable_clk_tx: > clk_disable(&eqos->clk_tx); > err_disable_clk_rx: > @@ -104,20 +103,20 @@ err_disable_clk_master_bus: > err: > debug("%s: FAILED: %d\n", __func__, ret); > return ret; > -#endif > } > > static int eqos_stop_clks_stm32(struct udevice *dev) { -#ifdef CONFIG_CLK > - struct eqos_priv *eqos = dev_get_priv(dev); > + struct eqos_priv __maybe_unused *eqos = dev_get_priv(dev); > + > + if (!CONFIG_IS_ENABLED(CLK)) > + return 0; > > debug("%s(dev=%p):\n", __func__, dev); > > clk_disable(&eqos->clk_tx); > clk_disable(&eqos->clk_rx); > clk_disable(&eqos->clk_master_bus); > -#endif > > debug("%s: OK\n", __func__); > return 0; > -- > 2.43.0 > Reviewed-by: Christophe ROULLIER <christophe.roullier(a)foss.st.com>

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Re: [PATCH v2 02/11] net: dwc_eth_qos: Rename eqos_stm32_config to eqos_stm32mp15_config
by Christophe ROULLIER 19 Apr '24

19 Apr '24

> -----Original Message----- > From: Marek Vasut<marex(a)denx.de> > Sent: Tuesday, March 26, 2024 1:07 PM > To:u-boot@lists.denx.de > Cc: Marek Vasut<marex(a)denx.de>; Patrice CHOTARD - foss<patrice.chotard(a)foss.st.com>; Christophe ROULLIER<christophe.roullier(a)st.com>; Joe Hershberger<joe.hershberger(a)ni.com>; Patrick DELAUNAY - foss<patrick.delaunay(a)foss.st.com>; Ramon Fried<rfried.dev(a)gmail.com>;u-boot@dh-electronics.com;uboot-stm32@st-md-mailman.stormreply.com > Subject: [PATCH v2 02/11] net: dwc_eth_qos: Rename eqos_stm32_config to eqos_stm32mp15_config > > The current glue code is specific to STM32MP15xx, the upcoming STM32MP13xx will introduce another entry specific to the STM32MP13xx. Rename the current entry to eqos_stm32mp15_config in preparation for STM32MP13xx addition. No functional change. > > Reviewed-by: Patrice Chotard<patrice.chotard(a)foss.st.com> > Signed-off-by: Marek Vasut<marex(a)denx.de> > --- > Cc: Christophe Roullier<christophe.roullier(a)st.com> > Cc: Joe Hershberger<joe.hershberger(a)ni.com> > Cc: Patrice Chotard<patrice.chotard(a)foss.st.com> > Cc: Patrick Delaunay<patrick.delaunay(a)foss.st.com> > Cc: Ramon Fried<rfried.dev(a)gmail.com> > Cc:u-boot@dh-electronics.com > Cc:uboot-stm32@st-md-mailman.stormreply.com > --- > V2: Add RB from Patrice > --- > drivers/net/dwc_eth_qos.c | 2 +- > drivers/net/dwc_eth_qos.h | 2 +- > drivers/net/dwc_eth_qos_stm32.c | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 533c2bf070b..203bfc0848c 100644 > --- a/drivers/net/dwc_eth_qos.c > +++ b/drivers/net/dwc_eth_qos.c > @@ -1507,7 +1507,7 @@ static const struct udevice_id eqos_ids[] = { #if IS_ENABLED(CONFIG_DWC_ETH_QOS_STM32) > { > .compatible = "st,stm32mp1-dwmac", > - .data = (ulong)&eqos_stm32_config > + .data = (ulong)&eqos_stm32mp15_config > }, > #endif > #if IS_ENABLED(CONFIG_DWC_ETH_QOS_IMX) > diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index a6087f191ab..bafd0d339fb 100644 > --- a/drivers/net/dwc_eth_qos.h > +++ b/drivers/net/dwc_eth_qos.h > @@ -290,5 +290,5 @@ int eqos_null_ops(struct udevice *dev); extern struct eqos_config eqos_imx_config; extern struct eqos_config eqos_rockchip_config; extern struct eqos_config eqos_qcom_config; -extern struct eqos_config eqos_stm32_config; > +extern struct eqos_config eqos_stm32mp15_config; > extern struct eqos_config eqos_jh7110_config; diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index cfda757133e..fd29a604987 100644 > --- a/drivers/net/dwc_eth_qos_stm32.c > +++ b/drivers/net/dwc_eth_qos_stm32.c > @@ -184,7 +184,7 @@ static struct eqos_ops eqos_stm32_ops = { > .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32 }; > > -struct eqos_config __maybe_unused eqos_stm32_config = { > +struct eqos_config __maybe_unused eqos_stm32mp15_config = { > .reg_access_always_ok = false, > .mdio_wait = 10000, > .swr_wait = 50, > -- > 2.43.0 > Reviewed-by: Christophe ROULLIER <christophe.roullier(a)foss.st.com>

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Re: [PATCH v2 01/11] net: dwc_eth_qos: Split STM32 glue into separate file
by Christophe ROULLIER 19 Apr '24

19 Apr '24

> -----Original Message----- > From: Marek Vasut<marex(a)denx.de> > Sent: Tuesday, March 26, 2024 1:07 PM > To:u-boot@lists.denx.de > Cc: Marek Vasut<marex(a)denx.de>; Patrice CHOTARD - foss<patrice.chotard(a)foss.st.com>; Christophe ROULLIER<christophe.roullier(a)st.com>; Joe Hershberger<joe.hershberger(a)ni.com>; Patrick DELAUNAY - foss<patrick.delaunay(a)foss.st.com>; Ramon Fried<rfried.dev(a)gmail.com>;u-boot@dh-electronics.com;uboot-stm32@st-md-mailman.stormreply.com > Subject: [PATCH v2 01/11] net: dwc_eth_qos: Split STM32 glue into separate file > > Move STM32 glue code into separate file to contain the STM32 specific code outside of the DWMAC core code. No functional change. > > Reviewed-by: Patrice Chotard<patrice.chotard(a)foss.st.com> > Signed-off-by: Marek Vasut<marex(a)denx.de> > --- > Cc: Christophe Roullier<christophe.roullier(a)st.com> > Cc: Joe Hershberger<joe.hershberger(a)ni.com> > Cc: Patrice Chotard<patrice.chotard(a)foss.st.com> > Cc: Patrick Delaunay<patrick.delaunay(a)foss.st.com> > Cc: Ramon Fried<rfried.dev(a)gmail.com> > Cc:u-boot@dh-electronics.com > Cc:uboot-stm32@st-md-mailman.stormreply.com > --- > V2: Add RB from Patrice > --- > drivers/net/Makefile | 1 + > drivers/net/dwc_eth_qos.c | 165 --------------------------- > drivers/net/dwc_eth_qos.h | 1 + > drivers/net/dwc_eth_qos_stm32.c | 196 ++++++++++++++++++++++++++++++++ > 4 files changed, 198 insertions(+), 165 deletions(-) create mode 100644 drivers/net/dwc_eth_qos_stm32.c > > diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 6677366ebd6..dc3404519d6 100644 > --- a/drivers/net/Makefile > +++ b/drivers/net/Makefile > @@ -23,6 +23,7 @@ obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o > obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o > obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o > obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o > +obj-$(CONFIG_DWC_ETH_QOS_STM32) += dwc_eth_qos_stm32.o > obj-$(CONFIG_E1000) += e1000.o > obj-$(CONFIG_E1000_SPI) += e1000_spi.o > obj-$(CONFIG_EEPRO100) += eepro100.o > diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 9b3bce1dc87..533c2bf070b 100644 > --- a/drivers/net/dwc_eth_qos.c > +++ b/drivers/net/dwc_eth_qos.c > @@ -295,58 +295,6 @@ err: > #endif > } > > -static int eqos_start_clks_stm32(struct udevice *dev) -{ -#ifdef CONFIG_CLK > - struct eqos_priv *eqos = dev_get_priv(dev); > - int ret; > - > - debug("%s(dev=%p):\n", __func__, dev); > - > - ret = clk_enable(&eqos->clk_master_bus); > - if (ret < 0) { > - pr_err("clk_enable(clk_master_bus) failed: %d", ret); > - goto err; > - } > - > - ret = clk_enable(&eqos->clk_rx); > - if (ret < 0) { > - pr_err("clk_enable(clk_rx) failed: %d", ret); > - goto err_disable_clk_master_bus; > - } > - > - ret = clk_enable(&eqos->clk_tx); > - if (ret < 0) { > - pr_err("clk_enable(clk_tx) failed: %d", ret); > - goto err_disable_clk_rx; > - } > - > - if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) { > - ret = clk_enable(&eqos->clk_ck); > - if (ret < 0) { > - pr_err("clk_enable(clk_ck) failed: %d", ret); > - goto err_disable_clk_tx; > - } > - eqos->clk_ck_enabled = true; > - } > -#endif > - > - debug("%s: OK\n", __func__); > - return 0; > - > -#ifdef CONFIG_CLK > -err_disable_clk_tx: > - clk_disable(&eqos->clk_tx); > -err_disable_clk_rx: > - clk_disable(&eqos->clk_rx); > -err_disable_clk_master_bus: > - clk_disable(&eqos->clk_master_bus); > -err: > - debug("%s: FAILED: %d\n", __func__, ret); > - return ret; > -#endif > -} > - > static int eqos_stop_clks_tegra186(struct udevice *dev) { #ifdef CONFIG_CLK @@ -365,22 +313,6 @@ static int eqos_stop_clks_tegra186(struct udevice *dev) > return 0; > } > > -static int eqos_stop_clks_stm32(struct udevice *dev) -{ -#ifdef CONFIG_CLK > - struct eqos_priv *eqos = dev_get_priv(dev); > - > - debug("%s(dev=%p):\n", __func__, dev); > - > - clk_disable(&eqos->clk_tx); > - clk_disable(&eqos->clk_rx); > - clk_disable(&eqos->clk_master_bus); > -#endif > - > - debug("%s: OK\n", __func__); > - return 0; > -} > - > static int eqos_start_resets_tegra186(struct udevice *dev) { > struct eqos_priv *eqos = dev_get_priv(dev); @@ -493,17 +425,6 @@ static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev) #endif } > > -static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev) -{ -#ifdef CONFIG_CLK > - struct eqos_priv *eqos = dev_get_priv(dev); > - > - return clk_get_rate(&eqos->clk_master_bus); > -#else > - return 0; > -#endif > -} > - > static int eqos_set_full_duplex(struct udevice *dev) { > struct eqos_priv *eqos = dev_get_priv(dev); @@ -1415,57 +1336,6 @@ err_free_reset_eqos: > return ret; > } > > -static int eqos_probe_resources_stm32(struct udevice *dev) -{ > - struct eqos_priv *eqos = dev_get_priv(dev); > - int ret; > - phy_interface_t interface; > - > - debug("%s(dev=%p):\n", __func__, dev); > - > - interface = eqos->config->interface(dev); > - > - if (interface == PHY_INTERFACE_MODE_NA) { > - pr_err("Invalid PHY interface\n"); > - return -EINVAL; > - } > - > - ret = board_interface_eth_init(dev, interface); > - if (ret) > - return -EINVAL; > - > - ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus); > - if (ret) { > - pr_err("clk_get_by_name(master_bus) failed: %d", ret); > - goto err_probe; > - } > - > - ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx); > - if (ret) { > - pr_err("clk_get_by_name(rx) failed: %d", ret); > - goto err_probe; > - } > - > - ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx); > - if (ret) { > - pr_err("clk_get_by_name(tx) failed: %d", ret); > - goto err_probe; > - } > - > - /* Get ETH_CLK clocks (optional) */ > - ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck); > - if (ret) > - pr_warn("No phy clock provided %d", ret); > - > - debug("%s: OK\n", __func__); > - return 0; > - > -err_probe: > - > - debug("%s: returns %d\n", __func__, ret); > - return ret; > -} > - > static phy_interface_t eqos_get_interface_tegra186(const struct udevice *dev) { > return PHY_INTERFACE_MODE_MII; > @@ -1484,12 +1354,6 @@ static int eqos_remove_resources_tegra186(struct udevice *dev) > return 0; > } > > -static int eqos_remove_resources_stm32(struct udevice *dev) -{ > - debug("%s(dev=%p):\n", __func__, dev); > - return 0; > -} > - > static int eqos_probe(struct udevice *dev) { > struct eqos_priv *eqos = dev_get_priv(dev); @@ -1633,35 +1497,6 @@ static const struct eqos_config __maybe_unused eqos_tegra186_config = { > .ops = &eqos_tegra186_ops > }; > > -static struct eqos_ops eqos_stm32_ops = { > - .eqos_inval_desc = eqos_inval_desc_generic, > - .eqos_flush_desc = eqos_flush_desc_generic, > - .eqos_inval_buffer = eqos_inval_buffer_generic, > - .eqos_flush_buffer = eqos_flush_buffer_generic, > - .eqos_probe_resources = eqos_probe_resources_stm32, > - .eqos_remove_resources = eqos_remove_resources_stm32, > - .eqos_stop_resets = eqos_null_ops, > - .eqos_start_resets = eqos_null_ops, > - .eqos_stop_clks = eqos_stop_clks_stm32, > - .eqos_start_clks = eqos_start_clks_stm32, > - .eqos_calibrate_pads = eqos_null_ops, > - .eqos_disable_calibration = eqos_null_ops, > - .eqos_set_tx_clk_speed = eqos_null_ops, > - .eqos_get_enetaddr = eqos_null_ops, > - .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32 > -}; > - > -static const struct eqos_config __maybe_unused eqos_stm32_config = { > - .reg_access_always_ok = false, > - .mdio_wait = 10000, > - .swr_wait = 50, > - .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV, > - .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, > - .axi_bus_width = EQOS_AXI_WIDTH_64, > - .interface = dev_read_phy_mode, > - .ops = &eqos_stm32_ops > -}; > - > static const struct udevice_id eqos_ids[] = { #if IS_ENABLED(CONFIG_DWC_ETH_QOS_TEGRA186) > { > diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index e3222e1e17e..a6087f191ab 100644 > --- a/drivers/net/dwc_eth_qos.h > +++ b/drivers/net/dwc_eth_qos.h > @@ -290,4 +290,5 @@ int eqos_null_ops(struct udevice *dev); extern struct eqos_config eqos_imx_config; extern struct eqos_config eqos_rockchip_config; extern struct eqos_config eqos_qcom_config; > +extern struct eqos_config eqos_stm32_config; > extern struct eqos_config eqos_jh7110_config; diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c new file mode 100644 index 00000000000..cfda757133e > --- /dev/null > +++ b/drivers/net/dwc_eth_qos_stm32.c > @@ -0,0 +1,196 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2024, Marek Vasut<marex(a)denx.de> > + * > + * This is code moved from drivers/net/dwc_eth_qos.c , which is: > + * Copyright (c) 2016, NVIDIA CORPORATION. > + */ > + > +#include <common.h> > +#include <asm/cache.h> > +#include <asm/gpio.h> > +#include <asm/io.h> > +#include <clk.h> > +#include <cpu_func.h> > +#include <dm.h> > +#include <dm/device_compat.h> > +#include <errno.h> > +#include <eth_phy.h> > +#include <log.h> > +#include <malloc.h> > +#include <memalign.h> > +#include <miiphy.h> > +#include <net.h> > +#include <netdev.h> > +#include <phy.h> > +#include <reset.h> > +#include <wait_bit.h> > +#include <linux/delay.h> > + > +#include "dwc_eth_qos.h" > + > +static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev) { #ifdef > +CONFIG_CLK > + struct eqos_priv *eqos = dev_get_priv(dev); > + > + return clk_get_rate(&eqos->clk_master_bus); > +#else > + return 0; > +#endif > +} > + > +static int eqos_start_clks_stm32(struct udevice *dev) { #ifdef > +CONFIG_CLK > + struct eqos_priv *eqos = dev_get_priv(dev); > + int ret; > + > + debug("%s(dev=%p):\n", __func__, dev); > + > + ret = clk_enable(&eqos->clk_master_bus); > + if (ret < 0) { > + pr_err("clk_enable(clk_master_bus) failed: %d", ret); > + goto err; > + } > + > + ret = clk_enable(&eqos->clk_rx); > + if (ret < 0) { > + pr_err("clk_enable(clk_rx) failed: %d", ret); > + goto err_disable_clk_master_bus; > + } > + > + ret = clk_enable(&eqos->clk_tx); > + if (ret < 0) { > + pr_err("clk_enable(clk_tx) failed: %d", ret); > + goto err_disable_clk_rx; > + } > + > + if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) { > + ret = clk_enable(&eqos->clk_ck); > + if (ret < 0) { > + pr_err("clk_enable(clk_ck) failed: %d", ret); > + goto err_disable_clk_tx; > + } > + eqos->clk_ck_enabled = true; > + } > +#endif > + > + debug("%s: OK\n", __func__); > + return 0; > + > +#ifdef CONFIG_CLK > +err_disable_clk_tx: > + clk_disable(&eqos->clk_tx); > +err_disable_clk_rx: > + clk_disable(&eqos->clk_rx); > +err_disable_clk_master_bus: > + clk_disable(&eqos->clk_master_bus); > +err: > + debug("%s: FAILED: %d\n", __func__, ret); > + return ret; > +#endif > +} > + > +static int eqos_stop_clks_stm32(struct udevice *dev) { #ifdef > +CONFIG_CLK > + struct eqos_priv *eqos = dev_get_priv(dev); > + > + debug("%s(dev=%p):\n", __func__, dev); > + > + clk_disable(&eqos->clk_tx); > + clk_disable(&eqos->clk_rx); > + clk_disable(&eqos->clk_master_bus); > +#endif > + > + debug("%s: OK\n", __func__); > + return 0; > +} > + > +static int eqos_probe_resources_stm32(struct udevice *dev) { > + struct eqos_priv *eqos = dev_get_priv(dev); > + int ret; > + phy_interface_t interface; > + > + debug("%s(dev=%p):\n", __func__, dev); > + > + interface = eqos->config->interface(dev); > + > + if (interface == PHY_INTERFACE_MODE_NA) { > + pr_err("Invalid PHY interface\n"); > + return -EINVAL; > + } > + > + ret = board_interface_eth_init(dev, interface); > + if (ret) > + return -EINVAL; > + > + ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus); > + if (ret) { > + pr_err("clk_get_by_name(master_bus) failed: %d", ret); > + goto err_probe; > + } > + > + ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx); > + if (ret) { > + pr_err("clk_get_by_name(rx) failed: %d", ret); > + goto err_probe; > + } > + > + ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx); > + if (ret) { > + pr_err("clk_get_by_name(tx) failed: %d", ret); > + goto err_probe; > + } > + > + /* Get ETH_CLK clocks (optional) */ > + ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck); > + if (ret) > + pr_warn("No phy clock provided %d", ret); > + > + debug("%s: OK\n", __func__); > + return 0; > + > +err_probe: > + > + debug("%s: returns %d\n", __func__, ret); > + return ret; > +} > + > +static int eqos_remove_resources_stm32(struct udevice *dev) { > + debug("%s(dev=%p):\n", __func__, dev); > + > + return 0; > +} > + > +static struct eqos_ops eqos_stm32_ops = { > + .eqos_inval_desc = eqos_inval_desc_generic, > + .eqos_flush_desc = eqos_flush_desc_generic, > + .eqos_inval_buffer = eqos_inval_buffer_generic, > + .eqos_flush_buffer = eqos_flush_buffer_generic, > + .eqos_probe_resources = eqos_probe_resources_stm32, > + .eqos_remove_resources = eqos_remove_resources_stm32, > + .eqos_stop_resets = eqos_null_ops, > + .eqos_start_resets = eqos_null_ops, > + .eqos_stop_clks = eqos_stop_clks_stm32, > + .eqos_start_clks = eqos_start_clks_stm32, > + .eqos_calibrate_pads = eqos_null_ops, > + .eqos_disable_calibration = eqos_null_ops, > + .eqos_set_tx_clk_speed = eqos_null_ops, > + .eqos_get_enetaddr = eqos_null_ops, > + .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32 }; > + > +struct eqos_config __maybe_unused eqos_stm32_config = { > + .reg_access_always_ok = false, > + .mdio_wait = 10000, > + .swr_wait = 50, > + .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV, > + .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, > + .axi_bus_width = EQOS_AXI_WIDTH_64, > + .interface = dev_read_phy_mode, > + .ops = &eqos_stm32_ops > +}; > -- > 2.43.0 > Reviewed-by: Christophe ROULLIER<christophe.roullier(a)foss.st.com>

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[PATCH v3] ARM: stm32: Initialize TAMP_SMCR BKP..PROT fields on STM32MP15xx
by Marek Vasut 19 Apr '24

19 Apr '24

In case of an OTP-CLOSED STM32MP15xx system, the CPU core 1 cannot be released from endless loop in BootROM only by populating TAMP BKPxR 4 and 5 with magic and branch address and sending SGI0 interrupt from core 0 to core 1 twice. TAMP_SMCR BKP..PROT fields must be initialized as well to release the core 1 from endless loop during the second SGI0 handling on core 1. Initialize TAMP_SMCR to protect the first 32 backup registers, the ones which contain the core 1 magic, branch address and boot information. This requirement seems to be undocumented, therefore it was necessary to trace and analyze the STM32MP15xx BootROM using OpenOCD and objdump. Ultimately, it turns out that a certain BootROM function reads out the TAMP_SMCR register and tests whether the BKP..PROT fields are non-zero. If they are zero, the BootROM code again waits for SGI0 using WFI, else the execution moves forward until it reaches handoff to the TAMP BKPxR 5 branch address. This fixes CPU core 1 release using U-Boot PSCI implementation on an OTP-CLOSED system, i.e. system with fuse 0 bit 6 set. Reviewed-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Igor Opaniuk <igor.opaniuk(a)foundries.io> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Simon Glass <sjg(a)chromium.org Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> Cc: u-boot(a)dh-electronics.com Cc: uboot-stm32(a)st-md-mailman.stormreply.com --- V2: Fix up the BKPRWD/BKPWD mask typo V3: - Update the allocation to 0x20/0x20 - Update commit message - Add RB from Patrick --- arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index dd99150fbc2..d75ec99d6a1 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -14,6 +14,7 @@ #include <asm/arch/sys_proto.h> #include <dm/device.h> #include <dm/uclass.h> +#include <linux/bitfield.h> /* RCC register */ #define RCC_TZCR (STM32_RCC_BASE + 0x00) @@ -41,6 +42,9 @@ #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) +#define TAMP_SMCR (STM32_TAMP_BASE + 0x20) +#define TAMP_SMCR_BKPRWDPROT GENMASK(7, 0) +#define TAMP_SMCR_BKPWDPROT GENMASK(23, 16) #define PWR_CR1 (STM32_PWR_BASE + 0x00) #define PWR_MCUCR (STM32_PWR_BASE + 0x14) @@ -136,6 +140,18 @@ static void security_init(void) */ writel(0x0, TAMP_CR1); + /* + * TAMP: Configure non-zero secure protection settings. This is + * checked by BootROM function 35ac on OTP-CLOSED device during + * CPU core 1 release from endless loop. If secure protection + * fields are zero, the core 1 is not released from endless + * loop on second SGI0. + */ + clrsetbits_le32(TAMP_SMCR, + TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT, + FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x20) | + FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x20)); + /* GPIOZ: deactivate the security */ writel(BIT(0), RCC_MP_AHB5ENSETR); writel(0x0, GPIOZ_SECCFGR); -- 2.43.0

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[PATCH] efi_loader: use event callback for initrd deregistration
by Masahisa Kojima 19 Apr '24

19 Apr '24

Currently efi_initrd_deregister() is called in bootefi.c when the image started from bootefi command returns. Since efi_guid_event_group_return_to_efibootmgr event is implemented, so let's use this event for invoking initrd deregistration. Signed-off-by: Masahisa Kojima <masahisa.kojima(a)linaro.org> --- Note that this patch can be applied to u-boot/next. This patch requires the patch e0d1a1ea68("efi_loader: add return to efibootmgr event group") cmd/bootefi.c | 5 -- lib/efi_loader/efi_load_initrd.c | 82 +++++++++++++++++++++----------- 2 files changed, 55 insertions(+), 32 deletions(-) diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 4d74969ad6..e52bd3f743 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -390,11 +390,6 @@ static efi_status_t do_bootefi_exec(efi_handle_t handle, void *load_options) out: free(load_options); - if (IS_ENABLED(CONFIG_EFI_LOAD_FILE2_INITRD)) { - if (efi_initrd_deregister() != EFI_SUCCESS) - log_err("Failed to remove loadfile2 for initrd\n"); - } - /* Notify EFI_EVENT_GROUP_RETURN_TO_EFIBOOTMGR event group. */ list_for_each_entry(evt, &efi_events, link) { if (evt->group && diff --git a/lib/efi_loader/efi_load_initrd.c b/lib/efi_loader/efi_load_initrd.c index 193433782c..7ca7785c04 100644 --- a/lib/efi_loader/efi_load_initrd.c +++ b/lib/efi_loader/efi_load_initrd.c @@ -184,6 +184,50 @@ out: return ret; } +/** + * efi_initrd_deregister() - delete the handle for loading initial RAM disk + * + * This will delete the handle containing the Linux specific vendor device + * path and EFI_LOAD_FILE2_PROTOCOL for loading an initrd + * + * Return: status code + */ +efi_status_t efi_initrd_deregister(void) +{ + efi_status_t ret; + + if (!efi_initrd_handle) + return EFI_SUCCESS; + + ret = efi_uninstall_multiple_protocol_interfaces(efi_initrd_handle, + /* initramfs */ + &efi_guid_device_path, + &dp_lf2_handle, + /* LOAD_FILE2 */ + &efi_guid_load_file2_protocol, + &efi_lf2_protocol, + NULL); + efi_initrd_handle = NULL; + + return ret; +} + +/** + * efi_initrd_return_notify() - return to efibootmgr callback + * + * @event: the event for which this notification function is registered + * @context: event context + */ +static void EFIAPI efi_initrd_return_notify(struct efi_event *event, + void *context) +{ + efi_status_t ret; + + EFI_ENTRY("%p, %p", event, context); + ret = efi_initrd_deregister(); + EFI_EXIT(ret); +} + /** * efi_initrd_register() - create handle for loading initial RAM disk * @@ -197,6 +241,7 @@ out: efi_status_t efi_initrd_register(void) { efi_status_t ret; + struct efi_event *event; /* * Allow the user to continue if Boot#### file path is not set for @@ -215,34 +260,17 @@ efi_status_t efi_initrd_register(void) &efi_guid_load_file2_protocol, &efi_lf2_protocol, NULL); + if (ret != EFI_SUCCESS) { + log_err("installing EFI_LOAD_FILE2_PROTOCOL failed\n"); + return ret; + } - return ret; -} - -/** - * efi_initrd_deregister() - delete the handle for loading initial RAM disk - * - * This will delete the handle containing the Linux specific vendor device - * path and EFI_LOAD_FILE2_PROTOCOL for loading an initrd - * - * Return: status code - */ -efi_status_t efi_initrd_deregister(void) -{ - efi_status_t ret; - - if (!efi_initrd_handle) - return EFI_SUCCESS; - - ret = efi_uninstall_multiple_protocol_interfaces(efi_initrd_handle, - /* initramfs */ - &efi_guid_device_path, - &dp_lf2_handle, - /* LOAD_FILE2 */ - &efi_guid_load_file2_protocol, - &efi_lf2_protocol, - NULL); - efi_initrd_handle = NULL; + ret = efi_create_event(EVT_NOTIFY_SIGNAL, TPL_CALLBACK, + efi_initrd_return_notify, NULL, + &efi_guid_event_group_return_to_efibootmgr, + &event); + if (ret != EFI_SUCCESS) + log_err("Creating event failed\n"); return ret; } base-commit: 4a363dd516856344558034027e40d903868f67b4 -- 2.34.1

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[PATCH v2] efi_loader: change the error message when storing EFI variables
by Ilias Apalodimas 19 Apr '24

19 Apr '24

When we try to store EFI variables on a file, we need to use an ESP. if an ESP is not found, variables will change in memory, but U-Boot won't be able to restore them across reboots. Adjust the error message so users can understand what's going on Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- Changes since v1: - print different messages if ESP is missing or write to file failed lib/efi_loader/efi_var_file.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/lib/efi_loader/efi_var_file.c b/lib/efi_loader/efi_var_file.c index 413e1794e88c..d5d347d50f8d 100644 --- a/lib/efi_loader/efi_var_file.c +++ b/lib/efi_loader/efi_var_file.c @@ -73,16 +73,20 @@ efi_status_t efi_var_to_file(void) goto error; ret = efi_set_blk_dev_to_system_partition(); - if (ret != EFI_SUCCESS) + if (ret != EFI_SUCCESS) { + log_err("ESP not found."); goto error; + } r = fs_write(EFI_VAR_FILE_NAME, map_to_sysmem(buf), 0, len, &actlen); - if (r || len != actlen) + if (r || len != actlen) { + log_err("Failed to store variables."); ret = EFI_DEVICE_ERROR; + } error: if (ret != EFI_SUCCESS) - log_err("Failed to persist EFI variables\n"); + log_err(" UEFI variables won't persist reboot\n"); free(buf); return ret; #else -- 2.43.0

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