April 2024 - U-Boot

[PATCH 1/3] ARM: dts: stm32: Fix partition node name for stm32mp157c-ev1-u-boot
by Patrice Chotard 19 Apr '24

19 Apr '24

Fix flash@0 and nand@0 partition node name with correct offset. Fixes: e91d3c61767b ("arm: dts: stm32: Add partitions in flash0 and nand node for stm32mp15xx-ev1") Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> --- arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi index 139940bd5d4..3515347e91d 100644 --- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi @@ -33,11 +33,11 @@ label = "fsbl1"; reg = <0x00000000 0x00040000>; }; - partition@80000 { + partition@40000 { label = "fsbl2"; reg = <0x00040000 0x00040000>; }; - partition@100000 { + partition@80000 { label = "ssbl"; reg = <0x00080000 0x00200000>; }; @@ -58,7 +58,7 @@ label = "fsbl2"; reg = <0x00040000 0x00040000>; }; - partition@100000 { + partition@80000 { label = "fip"; reg = <0x00080000 0x00400000>; }; @@ -112,7 +112,7 @@ label = "fip2"; reg = <0x00600000 0x00400000>; }; - partition@1200000 { + partition@a00000 { label = "UBI"; reg = <0x00a00000 0x3f600000>; }; -- 2.25.1

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[PATCH 1/2] mmc: stm32_sdmmc2: Add "st,stm32mp25-sdmmc2" compatible
by Patrice Chotard 19 Apr '24

19 Apr '24

From: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Add compatible used for STM32MP25 family. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> --- drivers/mmc/stm32_sdmmc2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index a2b111a8435..d4982a14281 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -789,6 +789,7 @@ static int stm32_sdmmc2_bind(struct udevice *dev) static const struct udevice_id stm32_sdmmc2_ids[] = { { .compatible = "st,stm32-sdmmc2" }, + { .compatible = "st,stm32mp25-sdmmc2" }, { } }; -- 2.25.1

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[PATCH v1 00/25] stm32mp: Fix keys & leds management
by Patrice Chotard 19 Apr '24

19 Apr '24

Adding FASTBOOT support for stm32mp13 shows issues when entering in fastboot mode using a dedicated key. On several STM32MP boards, same gpio is shared between key and led. Restore the fastboot/stm32prog activation using a dedicated key. Restore the led-blue which indicates U-Boot entering / exit. Make usage of BUTTON-UCLASS for key management on STM32MP1. Patrice Chotard (25): configs: stm32mp13: Enable FASTBOOT configs: stm32mp1: Enable BUTTON_GPIO flag for stm32mp15_defconfig configs: stm32mp1: Enable BUTTON_GPIO flag for stm32mp15_basic_defconfig configs: stm32mp1: Enable BUTTON_GPIO flag for stm32mp15_trusted_defconfig configs: stm32mp1: Enable BUTTON_GPIO flag for stm32mp13_defconfig board: st: stmp32mp1: Use BUTTON UCLASS in board_key_check() ARM: dts: stm32: Add gpio-keys for stm32mp135f-dk-u-boot ARM: dts: stm32: Don't probe led-red/led-blue at boot for stm32mp135f-dk-u-boot ARM: dts: stm32: Clean led-red node for stm32mp135f-dk-u-boot ARM: dts: stm32: Add gpio-keys for stm32mp157a-dk1-scmi-u-boot ARM: dts: stm32: Don't probe red led at boot for stm32mp157a-dk1-scmi-u-boot ARM: dts: stm32: Update red led node for stm32mp157a-dk1-scmi-u-boot ARM: dts: stm32: Add led-blue for stm32mp157a-dk1-scmi-u-boot ARM: dts: stm32: Add gpio-keys for stm32mp157a-dk1-u-boot ARM: dts: stm32: Don't probe red led at boot for stm32mp157a-dk1-u-boot ARM: dts: stm32: Update red led node for stm32mp157a-dk1-u-boot ARM: dts: stm32: Update u-boot,boot-led for stm32mp157a-dk1-u-boot ARM: dts: stm32: Add gpio-keys for stm32mp157c-ed1-u-boot ARM: dts: stm32: Don't probe red led at boot for stm32mp157c-ed1-u-boot ARM: dts: stm32: Update red led node for stm32mp157c-ed1-u-boot ARM: dts: stm32: Add led-blue for stm32mp157c-ed1-u-boot ARM: dts: stm32: Add gpio-keys for stm32mp157c-ed1-scmi-u-boot ARM: dts: stm32: Don't probe red led at boot for stm32mp157c-ed1-scmi-u-boot ARM: dts: stm32: Update red led node for stm32mp157c-ed1-scmi-u-boot ARM: dts: stm32: Add led-blue for stm32mp157c-ed1-scmi-u-boot arch/arm/dts/stm32mp135f-dk-u-boot.dtsi | 19 +++++- arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi | 32 ++++++--- arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 32 ++++++--- arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi | 34 +++++++--- arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 34 +++++++--- board/st/stm32mp1/stm32mp1.c | 68 +++++++++++-------- configs/stm32mp13_defconfig | 11 ++- configs/stm32mp15_basic_defconfig | 2 + configs/stm32mp15_defconfig | 2 + configs/stm32mp15_trusted_defconfig | 2 + 10 files changed, 173 insertions(+), 63 deletions(-) -- 2.25.1

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[PATCH] stm32mp: cmd_stm32prog: add dependencies with USB_GADGET_DOWNLOAD
by Patrick Delaunay 19 Apr '24

19 Apr '24

This patch avoids compilation issue when CONFIG_USB_GADGET is deactivated in defconfig, with undefined reference to run_usb_dnl_gadget and to g_dnl_set_product. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig index 8f91db4b46b9..589276282e44 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig @@ -17,6 +17,7 @@ config CMD_STM32PROG config CMD_STM32PROG_USB bool "support stm32prog over USB" depends on CMD_STM32PROG + depends on USB_GADGET_DOWNLOAD default y help activate the command "stm32prog usb" for STM32MP soc family -- 2.25.1

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[PATCH] arm: stm32: Enable OHCI HCD support on STM32MP15xx DHSOM
by Marek Vasut 19 Apr '24

19 Apr '24

The OHCI HCD is mandatory for USB 1.1 FS/LS device support, enable it. This used to be enabled implicitly before, now that implicit dependency disappeared and this got disabled. Enable it manually. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: u-boot(a)dh-electronics.com Cc: uboot-stm32(a)st-md-mailman.stormreply.com --- configs/stm32mp15_dhcom_basic_defconfig | 2 ++ configs/stm32mp15_dhcor_basic_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index 1d241529be7..0bfd3b76d6a 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -164,6 +164,8 @@ CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 6e0c4a8cf9f..1c1fbc5c7db 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -164,6 +164,8 @@ CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC2=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y -- 2.43.0

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[PATCH] mtd: rawnand: stm32_fmc2: add MP25 support
by Christophe Kerello 19 Apr '24

19 Apr '24

FMC2 IP supports up to 4 chip select. On MP1 SoC, only 2 of them are available when on MP25 SoC, the 4 chip select are available. Let's use a platform data structure for parameters that will differ. Signed-off-by: Christophe Kerello <christophe.kerello(a)foss.st.com> --- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 47 ++++++++++++++++++++++---- 1 file changed, 40 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index 3528824575b..d284b8cbb12 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -34,7 +34,7 @@ #define FMC2_RB_DELAY_US 30 /* Max chip enable */ -#define FMC2_MAX_CE 2 +#define FMC2_MAX_CE 4 /* Timings */ #define FMC2_THIZ 1 @@ -160,6 +160,11 @@ static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip) return container_of(chip, struct stm32_fmc2_nand, chip); } +struct stm32_fmc2_nfc_data { + int max_ncs; + struct udevice *(*get_cdev)(struct udevice *dev); +}; + struct stm32_fmc2_nfc { struct nand_hw_control base; struct stm32_fmc2_nand nand; @@ -169,6 +174,7 @@ struct stm32_fmc2_nfc { fdt_addr_t cmd_base[FMC2_MAX_CE]; fdt_addr_t addr_base[FMC2_MAX_CE]; struct clk clk; + const struct stm32_fmc2_nfc_data *data; u8 cs_assigned; int cs_sel; @@ -815,7 +821,7 @@ static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, ofnode node) } for (i = 0; i < nand->ncs; i++) { - if (cs[i] >= FMC2_MAX_CE) { + if (cs[i] >= nfc->data->max_ncs) { log_err("Invalid reg value: %d\n", nand->cs_used[i]); return -EINVAL; } @@ -906,10 +912,18 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev) spin_lock_init(&nfc->controller.lock); init_waitqueue_head(&nfc->controller.wq); - cdev = stm32_fmc2_nfc_get_cdev(dev); - if (!cdev) + nfc->data = (void *)dev_get_driver_data(dev); + if (!nfc->data) return -EINVAL; + if (nfc->data->get_cdev) { + cdev = nfc->data->get_cdev(dev); + if (!cdev) + return -EINVAL; + } else { + cdev = dev->parent; + } + ret = stm32_fmc2_nfc_parse_dt(dev, nfc); if (ret) return ret; @@ -921,7 +935,7 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev) if (dev == cdev) start_region = 1; - for (chip_cs = 0, mem_region = start_region; chip_cs < FMC2_MAX_CE; + for (chip_cs = 0, mem_region = start_region; chip_cs < nfc->data->max_ncs; chip_cs++, mem_region += 3) { if (!(nfc->cs_assigned & BIT(chip_cs))) continue; @@ -1033,9 +1047,28 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev) return nand_register(0, mtd); } +static const struct stm32_fmc2_nfc_data stm32_fmc2_nfc_mp1_data = { + .max_ncs = 2, + .get_cdev = stm32_fmc2_nfc_get_cdev, +}; + +static const struct stm32_fmc2_nfc_data stm32_fmc2_nfc_mp25_data = { + .max_ncs = 4, +}; + static const struct udevice_id stm32_fmc2_nfc_match[] = { - { .compatible = "st,stm32mp15-fmc2" }, - { .compatible = "st,stm32mp1-fmc2-nfc" }, + { + .compatible = "st,stm32mp15-fmc2", + .data = (ulong)&stm32_fmc2_nfc_mp1_data, + }, + { + .compatible = "st,stm32mp1-fmc2-nfc", + .data = (ulong)&stm32_fmc2_nfc_mp1_data, + }, + { + .compatible = "st,stm32mp25-fmc2-nfc", + .data = (ulong)&stm32_fmc2_nfc_mp25_data, + }, { /* Sentinel */ } }; -- 2.25.1

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[PATCH v1 0/2] memory: stm32-fmc2-ebi: Add MP25 FMC2 support
by Christophe Kerello 19 Apr '24

19 Apr '24

On MP1 SoC, RNB signal (NAND controller signal) and NWAIT signal (PSRAM controller signal) have been integrated together in the SoC. That means that the NAND controller and the PSRAM controller (if the signal is used) can not be used at the same time. On MP25 SoC, the 2 signals can be used outside the SoC, so there is no more restrictions. MP1 SoC also embeds revision 1.1 of the FMC2 IP when MP25 SoC embeds revision 2.0 of the FMC2 IP. Christophe Kerello (2): memory: stm32-fmc2-ebi: add MP25 support memory: stm32-fmc2-ebi: add MP25 RIF support drivers/memory/stm32-fmc2-ebi.c | 449 +++++++++++++++++++++++++++++++- 1 file changed, 437 insertions(+), 12 deletions(-) -- 2.25.1

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[PATCH v2] ARM: stm32: Jump to ep on successful resume in PSCI suspend code
by Marek Vasut 19 Apr '24

19 Apr '24

In case the system has resumed successfully, the PSCI suspend resume code has to jump to the 'ep' successful resume entry point code path, otherwise the code has to jump to content of the LR register, which points to failed resume code path. To implement this distinction, rewrite LR register stored on stack with 'ep' value in case of a successful resume, which is really in every case unless some catastrophic failure occurred during suspend. Without this change, Linux counts every resume as failed in /sys/power/suspend_stats/fail Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: u-boot(a)dh-electronics.com Cc: u-boot(a)lists.denx.de Cc: uboot-stm32(a)st-md-mailman.stormreply.com --- V2: Rebase on u-boot/master --- arch/arm/mach-stm32mp/stm32mp1/psci.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c index 8cdeb0ab3f2..4f2379df45f 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c @@ -703,6 +703,8 @@ void __secure psci_system_suspend(u32 __always_unused function_id, { u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr; u32 gicd_addr = stm32mp_get_gicd_base_address(); + u32 cpu = psci_get_cpu_id(); + u32 sp = (u32)__secure_stack_end - (cpu << ARM_PSCI_STACK_SHIFT); bool iwdg1_wake = false; bool iwdg2_wake = false; bool other_wake = false; @@ -805,4 +807,16 @@ void __secure psci_system_suspend(u32 __always_unused function_id, writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR); clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); + + /* + * The system has resumed successfully. Rewrite LR register stored + * on stack with 'ep' value, so that on return from this PSCI call, + * the code would jump to that 'ep' resume entry point code path + * instead of the previous 'lr' register content which (e.g. with + * Linux) points to resume failure code path. + * + * See arch/arm/cpu/armv7/psci.S _smc_psci: for the stack layout + * used here, SP-4 is PC, SP-8 is LR, SP-12 is R7, and so on. + */ + writel(ep, sp - 8); } -- 2.43.0

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[PATCH] ARM: stm32: Drop superfluous Makefile entry for ecdsa_romapi.o
by Marek Vasut 19 Apr '24

19 Apr '24

The source file is in arch/arm/mach-stm32mp/ecdsa_romapi.c and not in arch/arm/mach-stm32mp/stm32mp1/ecdsa_romapi.c . There are two Makefile entries in each subdirectory. Drop the bogus one and keep only the correct one, the one in arch/arm/mach-stm32mp/Makefile . Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Igor Opaniuk <igor.opaniuk(a)foundries.io> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Simon Glass <sjg(a)chromium.org Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> Cc: u-boot(a)dh-electronics.com Cc: uboot-stm32(a)st-md-mailman.stormreply.com --- arch/arm/mach-stm32mp/stm32mp1/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile index 857148747ef..ebae50f66c9 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/Makefile +++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile @@ -8,7 +8,6 @@ obj-y += cpu.o obj-$(CONFIG_STM32MP13X) += stm32mp13x.o obj-$(CONFIG_STM32MP15X) += stm32mp15x.o -obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o ifdef CONFIG_SPL_BUILD obj-y += spl.o obj-y += tzc400.o -- 2.43.0

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[PATCH] ARM: stm32: Report OTP-CLOSED instead of rev.? on closed STM32MP15xx
by Marek Vasut 19 Apr '24

19 Apr '24

SoC revision is only accessible via DBUMCU IDC register, which requires BSEC.DENABLE DBGSWENABLE bit to be set to make the register accessible, otherwise an access to the register triggers bus fault. As BSEC.DBGSWENABLE is zero in case of an OTP-CLOSED system, do NOT set DBGSWENABLE bit as this might open a brief window for timing attacks. Instead, report that this system is OTP-CLOSED and do not report any SoC revision to avoid confusing users. Use an SEC/C abbreviation to avoid growing SOC_NAME_SIZE . Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Igor Opaniuk <igor.opaniuk(a)foundries.io> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Simon Glass <sjg(a)chromium.org Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> Cc: u-boot(a)dh-electronics.com Cc: uboot-stm32(a)st-md-mailman.stormreply.com --- arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index afc56b02eea..dd99150fbc2 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -322,8 +322,23 @@ void get_soc_name(char name[SOC_NAME_SIZE]) get_cpu_string_offsets(&type, &pkg, &rev); - snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", - soc_type[type], soc_pkg[pkg], soc_rev[rev]); + if (bsec_dbgswenable()) { + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", + soc_type[type], soc_pkg[pkg], soc_rev[rev]); + } else { + /* + * SoC revision is only accessible via DBUMCU IDC register, + * which requires BSEC.DENABLE DBGSWENABLE bit to be set to + * make the register accessible, otherwise an access to the + * register triggers bus fault. As BSEC.DBGSWENABLE is zero + * in case of an OTP-CLOSED system, do NOT set DBGSWENABLE + * bit as this might open a brief window for timing attacks. + * Instead, report that this system is OTP-CLOSED and do not + * report any SoC revision to avoid confusing users. + */ + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s SEC/C", + soc_type[type], soc_pkg[pkg]); + } } static void setup_soc_type_pkg_rev(void) -- 2.43.0

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