April 2024 - U-Boot

[PATCH v2 1/3] efi_loader: enable QueryVariableInfo at runtime for file backed variables
by Ilias Apalodimas 25 Apr '24

25 Apr '24

Since commit c28d32f946f0 ("efi_loader: conditionally enable SetvariableRT") we are enabling the last bits of missing runtime services. Add support for QueryVariableInfo which we already support at boottime and we just need to mark some fucntions available at runtime and move some checks around. It's worth noting that pointer checks for maxmimum and remaining variable storage aren't when we store variables on the RPMB, since the Secure World backend is already performing them. Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- Changes since v1: - require EFI_VARIABLE_RUNTIME_ACCESS to be set at runtime - return EFI_UNSUPPORTED for auth variables lib/efi_loader/efi_runtime.c | 4 +++ lib/efi_loader/efi_var_common.c | 6 ----- lib/efi_loader/efi_variable.c | 25 ++++++++++++++----- lib/efi_loader/efi_variable_tee.c | 5 ++++ .../efi_selftest_variables_runtime.c | 14 ++++++++--- 5 files changed, 39 insertions(+), 15 deletions(-) diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c index 73831c527e00..011bcd04836d 100644 --- a/lib/efi_loader/efi_runtime.c +++ b/lib/efi_loader/efi_runtime.c @@ -129,6 +129,10 @@ efi_status_t efi_init_runtime_supported(void) EFI_RT_SUPPORTED_SET_VIRTUAL_ADDRESS_MAP | EFI_RT_SUPPORTED_CONVERT_POINTER; + if (IS_ENABLED(CONFIG_EFI_VARIABLE_FILE_STORE)) + rt_table->runtime_services_supported |= + EFI_RT_SUPPORTED_QUERY_VARIABLE_INFO; + if (IS_ENABLED(CONFIG_EFI_RT_VOLATILE_STORE)) { u8 s = 0; diff --git a/lib/efi_loader/efi_var_common.c b/lib/efi_loader/efi_var_common.c index 961139f005af..ea8d2a4cf98c 100644 --- a/lib/efi_loader/efi_var_common.c +++ b/lib/efi_loader/efi_var_common.c @@ -1,4 +1,3 @@ -// SPDX-License-Identifier: GPL-2.0+ /* * UEFI runtime variable services * @@ -163,11 +162,6 @@ efi_status_t EFIAPI efi_query_variable_info( EFI_ENTRY("%x %p %p %p", attributes, maximum_variable_storage_size, remaining_variable_storage_size, maximum_variable_size); - if (!maximum_variable_storage_size || - !remaining_variable_storage_size || - !maximum_variable_size) - return EFI_EXIT(EFI_INVALID_PARAMETER); - ret = efi_query_variable_info_int(attributes, maximum_variable_storage_size, remaining_variable_storage_size, diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index 0cbed53d1dbf..1cc02acb3b26 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -406,12 +406,15 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, return EFI_SUCCESS; } -efi_status_t efi_query_variable_info_int(u32 attributes, - u64 *maximum_variable_storage_size, - u64 *remaining_variable_storage_size, - u64 *maximum_variable_size) +efi_status_t __efi_runtime +efi_query_variable_info_int(u32 attributes, + u64 *maximum_variable_storage_size, + u64 *remaining_variable_storage_size, + u64 *maximum_variable_size) { - if (attributes == 0) + if (!maximum_variable_storage_size || + !remaining_variable_storage_size || + !maximum_variable_size || !attributes) return EFI_INVALID_PARAMETER; /* EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS is deprecated */ @@ -460,7 +463,17 @@ static efi_status_t __efi_runtime EFIAPI efi_query_variable_info_runtime( u64 *remaining_variable_storage_size, u64 *maximum_variable_size) { - return EFI_UNSUPPORTED; + if (!(attributes & EFI_VARIABLE_RUNTIME_ACCESS)) + return EFI_INVALID_PARAMETER; + if ((attributes & (EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS | + EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS | + EFI_VARIABLE_ENHANCED_AUTHENTICATED_ACCESS))) + return EFI_UNSUPPORTED; + + return efi_query_variable_info_int(attributes, + maximum_variable_storage_size, + remaining_variable_storage_size, + maximum_variable_size); } /** diff --git a/lib/efi_loader/efi_variable_tee.c b/lib/efi_loader/efi_variable_tee.c index 4f1aa298da13..8b6b0a390869 100644 --- a/lib/efi_loader/efi_variable_tee.c +++ b/lib/efi_loader/efi_variable_tee.c @@ -873,6 +873,11 @@ efi_status_t efi_query_variable_info_int(u32 attributes, efi_status_t ret; u8 *comm_buf; + if (!max_variable_storage_size || + !remain_variable_storage_size || + !max_variable_size || !attributes) + return EFI_INVALID_PARAMETER; + payload_size = sizeof(*mm_query_info); comm_buf = setup_mm_hdr((void **)&mm_query_info, payload_size, SMM_VARIABLE_FUNCTION_QUERY_VARIABLE_INFO, diff --git a/lib/efi_selftest/efi_selftest_variables_runtime.c b/lib/efi_selftest/efi_selftest_variables_runtime.c index afa91be62c85..5794a7b2d405 100644 --- a/lib/efi_selftest/efi_selftest_variables_runtime.c +++ b/lib/efi_selftest/efi_selftest_variables_runtime.c @@ -60,9 +60,17 @@ static int execute(void) ret = runtime->query_variable_info(EFI_VARIABLE_BOOTSERVICE_ACCESS, &max_storage, &rem_storage, &max_size); - if (ret != EFI_UNSUPPORTED) { - efi_st_error("QueryVariableInfo failed\n"); - return EFI_ST_FAILURE; + + if (IS_ENABLED(CONFIG_EFI_VARIABLE_FILE_STORE)) { + if (ret != EFI_SUCCESS) { + efi_st_error("QueryVariableInfo failed\n"); + return EFI_ST_FAILURE; + } + } else { + if (ret != EFI_UNSUPPORTED) { + efi_st_error("QueryVariableInfo failed\n"); + return EFI_ST_FAILURE; + } } ret = runtime->set_variable(u"efi_st_var0", &guid_vendor0, -- 2.40.1

2 4

[PATCH v2] efi_loader: do not install dtb if bootmgr fails
by Heinrich Schuchardt 25 Apr '24

25 Apr '24

If the UEFI boot manager fails there is no point in installing the device-tree as a configuration table. Unload image if device-tree cannot be installed. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- v2: Unload image if device-tree cannot be installed. --- lib/efi_loader/efi_bootmgr.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c index ca2ebdaa32f..aa2cc0eb52f 100644 --- a/lib/efi_loader/efi_bootmgr.c +++ b/lib/efi_loader/efi_bootmgr.c @@ -1209,15 +1209,21 @@ efi_status_t efi_bootmgr_run(void *fdt) return CMD_RET_FAILURE; } - ret = efi_install_fdt(fdt); - if (ret != EFI_SUCCESS) - return ret; - ret = efi_bootmgr_load(&handle, &load_options); if (ret != EFI_SUCCESS) { log_notice("EFI boot manager: Cannot load any image\n"); return ret; } + ret = efi_install_fdt(fdt); + if (ret != EFI_SUCCESS) { + if (EFI_CALL(efi_unload_image(*handle)) == EFI_SUCCESS) + free(load_options); + else + log_err("Unloading image failed\n"); + + return ret; + } + return do_bootefi_exec(handle, load_options); } -- 2.43.0

2 1

[PATCH v3] usb: cdns3: gadget.c: Set fast access bit
by Ravi Gunasekaran 25 Apr '24

25 Apr '24

From: Aswath Govindraju <a-govindraju(a)ti.com> When the device port is in a low power state [U3/L2/Not Connected], accesses to usb device registers may take a long time. This could lead to potential core hang when the controller registers are accessed after the port is disabled by setting DEVDS field. Setting the fast register access bit ensures that the PHY clock is keeping up in active state. Therefore, set fast access bit to ensure the accesses to device registers are quick even in low power states. commit b5148d946f45 ("usb: cdns3: gadget: set fast access bit") in the upstream kernel is taken as reference. Signed-off-by: Aswath Govindraju <a-govindraju(a)ti.com> Signed-off-by: Ravi Gunasekaran <r-gunasekaran(a)ti.com> Reviewed-by: Roger Quadros <rogerq(a)kernel.org> Reviewed-by: Marek Vasut <marex(a)denx.de> --- Changes since v2: ---------------- * Updated the commit description with reference to upstream kernel commit * Picked up Marek's Reviewed-by tag from v2 Changes since v1: ----------------- * Rebased to tip of -next * Added Reviewed-by tag v2: https://lore.kernel.org/all/20240423082420.32336-1-r-gunasekaran@ti.com/ v1: https://lore.kernel.org/u-boot/20230505121353.23486-1-r-gunasekaran@ti.com/ drivers/usb/cdns3/gadget.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c index 7aa0c6b2be..d11175dc5b 100644 --- a/drivers/usb/cdns3/gadget.c +++ b/drivers/usb/cdns3/gadget.c @@ -2325,6 +2325,9 @@ static void cdns3_gadget_config(struct cdns3_device *priv_dev) writel(USB_IEN_INIT, &regs->usb_ien); writel(USB_CONF_CLK2OFFDS | USB_CONF_L1DS, &regs->usb_conf); + /* Set the Fast access bit */ + writel(PUSB_PWR_FST_REG_ACCESS, &priv_dev->regs->usb_pwr); + cdns3_configure_dmult(priv_dev, NULL); cdns3_gadget_pullup(&priv_dev->gadget, 1); @@ -2383,6 +2386,7 @@ static int cdns3_gadget_udc_stop(struct usb_gadget *gadget) /* disable interrupt for device */ writel(0, &priv_dev->regs->usb_ien); + writel(0, &priv_dev->regs->usb_pwr); writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf); return ret; base-commit: bc39e06778168a34bb4e0a34fbee4edbde4414d8 -- 2.17.1

3 3

[PATCH v3 00/11] rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588
by Quentin Schulz 25 Apr '24

25 Apr '24

This is a new version of the patch series started by Chris Morgan here: https://lore.kernel.org/u-boot/20240401181435.553351-1-macroalpha82@gmail.c… Thanks Chris for starting this effort and allowing me to take over the development. Allow RK3568 and RK3588 based boards to get the RAM bank configuration from the ROCKCHIP_TPL stage instead of the current logic. This fixes both an issue where 256MB of RAM is blocked for devices with >= 4GB of RAM and where memory holes need to be defined for devices with more than 16GB of RAM. In the event that neither SoC is used or the ROCKCHIP_TPL stage is not used, fall back to existing logic. The logic handles creating memory holes from reserved memory areas defined in mem_map data struct in SoC C files, but only if the DRAM area overlaps with one reserved memory area. Since mem_map data struct is used, it should be rather straightforward to add support for other SoCs if needed. The logic is taken from Rockchip's U-Boot tag linux-5.10-gen-rkr4.1 (e08e32143dd). Note that Rockchip's U-Boot/TF-A/OP-TEE modify the ATAGS at runtime as well, but the DDR_MEM tag seems to be pretty much stable (though BL31 seems to be reserving only 1MB for itself at the moment). u32 for ATAGS is used because it simplifies the pointer arithmetic and it's expected that ATAGS are always below the 4GB limit allowed by u32. The default number of DRAM banks is increased to 10 if ROCKCHIP_EXTERNAL_TPL is used, making it almost guaranteed that the new logic will be used for new devices, provided the ATAGS are valid. This was tested on Rock5B 16GB, Rock5B 8G and Jaguar 4G. U-Boot reports the appropriate DRAM size and the kernel passes the memtest. Boot the kernel with the following params: setenv bootargs 'memtest=1 console=uart,mmio32,0xfeb50000 earlyprintk' Jaguar 4GB: """ [ 0.000000] early_memtest: # of tests: 1 [ 0.000000] 0x0000000000200000 - 0x0000000002010000 pattern 0000000000000000 [ 0.000000] 0x0000000003b80000 - 0x00000000eced1000 pattern 0000000000000000 [ 0.000000] 0x00000000ecee4000 - 0x00000000f0000000 pattern 0000000000000000 [ 0.000000] 0x00000001f0000000 - 0x00000001ff790d38 pattern 0000000000000000 [ 0.000000] 0x00000001ff790d64 - 0x00000001ff790d68 pattern 0000000000000000 [ 0.000000] 0x00000001ff790d94 - 0x00000001ff790d98 pattern 0000000000000000 [ 0.000000] 0x00000001ff790dc4 - 0x00000001ff790dc8 pattern 0000000000000000 [ 0.000000] 0x00000001ff790df9 - 0x00000001ff790e00 pattern 0000000000000000 [ 0.000000] 0x00000001ff790e2c - 0x00000001ff790e30 pattern 0000000000000000 [ 0.000000] 0x00000001ff790e5c - 0x00000001ff790e60 pattern 0000000000000000 [ 0.000000] 0x00000001ff790e8c - 0x00000001ff790e90 pattern 0000000000000000 [ 0.000000] 0x00000001ff790ebc - 0x00000001ff790ec0 pattern 0000000000000000 [ 0.000000] 0x00000001ff790eec - 0x00000001ff790ef0 pattern 0000000000000000 [ 0.000000] 0x00000001ff790f1f - 0x00000001ff790f20 pattern 0000000000000000 [ 0.000000] 0x00000001ff790f4f - 0x00000001ff790f50 pattern 0000000000000000 [ 0.000000] 0x00000001ff790f7f - 0x00000001ff790f80 pattern 0000000000000000 [ 0.000000] 0x00000001ff790faf - 0x00000001ff790fb0 pattern 0000000000000000 [ 0.000000] 0x00000001ff790fdf - 0x00000001ff790fe0 pattern 0000000000000000 [ 0.000000] 0x00000001ff79100f - 0x00000001ff791010 pattern 0000000000000000 [ 0.000000] 0x00000001ff79103f - 0x00000001ff791040 pattern 0000000000000000 [ 0.000000] 0x00000001ff79106f - 0x00000001ff791070 pattern 0000000000000000 [ 0.000000] 0x00000001ff79109f - 0x00000001ff7910a0 pattern 0000000000000000 [ 0.000000] 0x00000001ff7910cf - 0x00000001ff7910d0 pattern 0000000000000000 [ 0.000000] 0x00000001ff7910fc - 0x00000001ff791100 pattern 0000000000000000 [ 0.000000] 0x00000001ff79112c - 0x00000001ff791130 pattern 0000000000000000 [ 0.000000] 0x00000001ff79115c - 0x00000001ff791160 pattern 0000000000000000 [ 0.000000] 0x00000001ff79118c - 0x00000001ff791190 pattern 0000000000000000 [ 0.000000] 0x00000001ff7911bc - 0x00000001ff7911c0 pattern 0000000000000000 [ 0.000000] 0x00000001ff7911ec - 0x00000001ff7911f0 pattern 0000000000000000 [ 0.000000] 0x00000001ff79121c - 0x00000001ff791220 pattern 0000000000000000 [ 0.000000] 0x00000001ff79124c - 0x00000001ff791250 pattern 0000000000000000 [ 0.000000] 0x00000001ff79127c - 0x00000001ff791280 pattern 0000000000000000 [ 0.000000] 0x00000001ff7912ad - 0x00000001ff7912b0 pattern 0000000000000000 [ 0.000000] 0x00000001ff7912dd - 0x00000001ff7912e0 pattern 0000000000000000 [ 0.000000] 0x00000001ff79130d - 0x00000001ff791310 pattern 0000000000000000 [ 0.000000] 0x00000001ff79133d - 0x00000001ff791340 pattern 0000000000000000 [ 0.000000] 0x00000001ff79136d - 0x00000001ff791370 pattern 0000000000000000 [ 0.000000] 0x00000001ff803ffc - 0x00000001ff804000 pattern 0000000000000000 $ lsmem --output SIZE --bytes --json | jq '[.memory[].size] | add / 1024 / 1024 / 1024' 4 """ Rock5B 8G: """ [ 0.000000] early_memtest: # of tests: 1 [ 0.000000] 0x0000000000200000 - 0x0000000002010000 pattern 0000000000000000 [ 0.000000] 0x0000000003b80000 - 0x00000000ecbc6000 pattern 0000000000000000 [ 0.000000] 0x00000000ecbd8000 - 0x00000000f0000000 pattern 0000000000000000 [ 0.000000] 0x0000000100000000 - 0x0000000200000000 pattern 0000000000000000 [ 0.000000] 0x00000002f0000000 - 0x00000002fef8e090 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e0bc - 0x00000002fef8e0c0 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e0ec - 0x00000002fef8e0f0 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e11c - 0x00000002fef8e120 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e14c - 0x00000002fef8e150 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e17c - 0x00000002fef8e180 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e1ac - 0x00000002fef8e1b0 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e1dc - 0x00000002fef8e1e0 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e20c - 0x00000002fef8e210 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e23f - 0x00000002fef8e240 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e26f - 0x00000002fef8e270 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e29f - 0x00000002fef8e2a0 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e2cf - 0x00000002fef8e2d0 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e2ff - 0x00000002fef8e300 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e32f - 0x00000002fef8e330 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e35f - 0x00000002fef8e360 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e38f - 0x00000002fef8e390 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e3bf - 0x00000002fef8e3c0 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e3ef - 0x00000002fef8e3f0 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e41c - 0x00000002fef8e420 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e44c - 0x00000002fef8e450 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e47c - 0x00000002fef8e480 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e4ac - 0x00000002fef8e4b0 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e4dc - 0x00000002fef8e4e0 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e50c - 0x00000002fef8e510 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e53c - 0x00000002fef8e540 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e56c - 0x00000002fef8e570 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e59c - 0x00000002fef8e5a0 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e5cd - 0x00000002fef8e5d0 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e5fd - 0x00000002fef8e600 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e62d - 0x00000002fef8e630 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e65d - 0x00000002fef8e660 pattern 0000000000000000 [ 0.000000] 0x00000002fef8e68d - 0x00000002fef8e690 pattern 0000000000000000 $ lsmem --output SIZE --bytes --json | jq '[.memory[].size] | add / 1024 / 1024 / 1024' 8 """ Rock5B 16GB: """ [ 0.000000] early_memtest: # of tests: 1 [ 0.000000] 0x0000000000200000 - 0x0000000002010000 pattern 0000000000000000 [ 0.000000] 0x0000000003b80000 - 0x00000000ecbc6000 pattern 0000000000000000 [ 0.000000] 0x00000000ecbd8000 - 0x00000000f0000000 pattern 0000000000000000 [ 0.000000] 0x0000000100000000 - 0x00000003fc000000 pattern 0000000000000000 [ 0.000000] 0x00000003fc500000 - 0x00000003fff00000 pattern 0000000000000000 [ 0.000000] 0x00000004f0000000 - 0x00000004fdf88090 pattern 0000000000000000 [ 0.000000] 0x00000004fdf880bc - 0x00000004fdf880c0 pattern 0000000000000000 [ 0.000000] 0x00000004fdf880ec - 0x00000004fdf880f0 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8811c - 0x00000004fdf88120 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8814c - 0x00000004fdf88150 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8817c - 0x00000004fdf88180 pattern 0000000000000000 [ 0.000000] 0x00000004fdf881ac - 0x00000004fdf881b0 pattern 0000000000000000 [ 0.000000] 0x00000004fdf881dc - 0x00000004fdf881e0 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8820c - 0x00000004fdf88210 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8823f - 0x00000004fdf88240 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8826f - 0x00000004fdf88270 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8829f - 0x00000004fdf882a0 pattern 0000000000000000 [ 0.000000] 0x00000004fdf882cf - 0x00000004fdf882d0 pattern 0000000000000000 [ 0.000000] 0x00000004fdf882ff - 0x00000004fdf88300 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8832f - 0x00000004fdf88330 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8835f - 0x00000004fdf88360 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8838f - 0x00000004fdf88390 pattern 0000000000000000 [ 0.000000] 0x00000004fdf883bf - 0x00000004fdf883c0 pattern 0000000000000000 [ 0.000000] 0x00000004fdf883ef - 0x00000004fdf883f0 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8841c - 0x00000004fdf88420 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8844c - 0x00000004fdf88450 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8847c - 0x00000004fdf88480 pattern 0000000000000000 [ 0.000000] 0x00000004fdf884ac - 0x00000004fdf884b0 pattern 0000000000000000 [ 0.000000] 0x00000004fdf884dc - 0x00000004fdf884e0 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8850c - 0x00000004fdf88510 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8853c - 0x00000004fdf88540 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8856c - 0x00000004fdf88570 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8859c - 0x00000004fdf885a0 pattern 0000000000000000 [ 0.000000] 0x00000004fdf885cd - 0x00000004fdf885d0 pattern 0000000000000000 [ 0.000000] 0x00000004fdf885fd - 0x00000004fdf88600 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8862d - 0x00000004fdf88630 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8865d - 0x00000004fdf88660 pattern 0000000000000000 [ 0.000000] 0x00000004fdf8868d - 0x00000004fdf88690 pattern 0000000000000000 $ lsmem --output SIZE --bytes --json | jq '[.memory[].size] | add / 1024 / 1024 / 1024' 16 """ I tested on Rock5B 16GB that without the memory holes and without using this new logic, the kernel fails this memtest, so this test seems valid. This has NOT been tested on RK356x as I don't own any. Changes in v3: - Split board migration to new DRAM ATAGS mechanism into separate commits, - Use mem_map instead of hardcoded values for reserved memory area for MMIO, - Add tag hash check to match Rockchip's downstream implementation, - Bail from while loop as soon as a tag with no size is encountered to match Rockchip's downstream implementation, - Use enum instead of constants for ATAG magic, - Add debug messages and comments, - Fix atags traversal by using tag size instead of checking every 16B, - Migrate Jaguar to new mechanism, - Default NR_DRAM_BANKS to 10 when ROCKCHIP_EXTERNAL_TPL is used so the default allows to use this new logic, - Define tag_header data struct to parse the first two bytes of a tag more easily, - Do not stop at CORE magic, directly look for DDR_MEM, - Bail from while loop as soon as an unknown tag is used to match Rockchip's downstream implementation, - Use phys_size_t and phys_addr_t wherever possible, Link to v2: https://lore.kernel.org/u-boot/20240401181435.553351-1-macroalpha82@gmail.c… Link to v1: https://lore.kernel.org/u-boot/20240330050515.470025-1-macroalpha82@gmail.c… Co-Developed-by: Chris Morgan <macromorgan(a)hotmail.com> Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- Quentin Schulz (11): rockchip: sdram: Support getting banks from TPL for rk3568 and rk3588 rockchip: NR_DRAM_BANKS now defaults to 10 when Rockchip TPL blob is used rockchip: nanopc-t6-rk3588: use DRAM banks from ATAGS rockchip: quartzpro64-rk3588: use DRAM banks from ATAGS rockchip: rock5a-rk3588s: use DRAM banks from ATAGS rockchip: rock5b-rk3588: use DRAM banks from ATAGS rockchip: evb_rk3588 et al.: use DRAM banks from ATAGS rockchip: toybrick_rk3588: use DRAM banks from ATAGS rockchip: turing-rk1-rk3588: use DRAM banks from ATAGS rockchip: rk3588: use DRAM banks from ATAGS rockchip: rk356x: use DRAM banks from ATAGS arch/arm/mach-rockchip/Kconfig | 3 + arch/arm/mach-rockchip/sdram.c | 240 +++++++++++++++++++++ board/friendlyelec/nanopc-t6-rk3588/Makefile | 6 - .../nanopc-t6-rk3588/nanopc-t6-rk3588.c | 39 ---- board/pine64/quartzpro64-rk3588/Makefile | 3 - .../pine64/quartzpro64-rk3588/quartzpro64-rk3588.c | 39 ---- board/radxa/rock5a-rk3588s/Makefile | 6 - board/radxa/rock5a-rk3588s/rock5a-rk3588s.c | 39 ---- board/radxa/rock5b-rk3588/Makefile | 6 - board/radxa/rock5b-rk3588/rock5b-rk3588.c | 39 ---- board/rockchip/evb_rk3588/Makefile | 6 - board/rockchip/evb_rk3588/evb-rk3588.c | 39 ---- board/rockchip/toybrick_rk3588/Makefile | 6 - board/rockchip/toybrick_rk3588/toybrick-rk3588.c | 39 ---- board/turing/turing-rk1-rk3588/Makefile | 6 - board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c | 39 ---- configs/anbernic-rgxx3-rk3566_defconfig | 1 - configs/bpi-r2-pro-rk3568_defconfig | 1 - configs/coolpi-4b-rk3588s_defconfig | 2 - configs/coolpi-cm5-evb-rk3588_defconfig | 2 - configs/evb-rk3568_defconfig | 1 - configs/evb-rk3588_defconfig | 2 - configs/generic-rk3568_defconfig | 1 - configs/generic-rk3588_defconfig | 2 - configs/jaguar-rk3588_defconfig | 1 - configs/lubancat-2-rk3568_defconfig | 1 - configs/nanopc-t6-rk3588_defconfig | 2 - configs/nanopi-r5c-rk3568_defconfig | 1 - configs/nanopi-r5s-rk3568_defconfig | 1 - configs/neu6a-io-rk3588_defconfig | 1 - configs/neu6b-io-rk3588_defconfig | 1 - configs/odroid-m1-rk3568_defconfig | 1 - configs/orangepi-5-plus-rk3588_defconfig | 2 - configs/orangepi-5-rk3588s_defconfig | 2 - configs/pinetab2-rk3566_defconfig | 1 - configs/quartz64-a-rk3566_defconfig | 1 - configs/quartz64-b-rk3566_defconfig | 1 - configs/quartzpro64-rk3588_defconfig | 2 - configs/radxa-cm3-io-rk3566_defconfig | 1 - configs/radxa-e25-rk3568_defconfig | 1 - configs/rock-3a-rk3568_defconfig | 1 - configs/rock5a-rk3588s_defconfig | 2 - configs/rock5b-rk3588_defconfig | 2 - configs/soquartz-blade-rk3566_defconfig | 1 - configs/soquartz-cm4-rk3566_defconfig | 1 - configs/soquartz-model-a-rk3566_defconfig | 1 - configs/toybrick-rk3588_defconfig | 2 - configs/turing-rk1-rk3588_defconfig | 2 - 48 files changed, 243 insertions(+), 356 deletions(-) --- base-commit: b03b49046af5dfca599d2ce8f0aafed89b97aa91 change-id: 20240415-rk35xx-dram-atags-35c9f19f4c38 Best regards, -- Quentin Schulz <quentin.schulz(a)theobroma-systems.com>

4 26

[PATCH] sysreset: psci: drop reliance on SPL support
by Andre Przywara 24 Apr '24

24 Apr '24

At the moment enabling CONFIG_SYSRESET_PSCI *selects* SPL_ARM_PSCI_FW, even though this is a platform design property, so nothing any driver should enforce. Some platforms load the PSCI runtime (TF-A) only in the SPL, so PSCI is naturally not available during SPL runtime. Spit CONFIG_SYSRESET_PSCI up into an SPL and a U-Boot proper version, and let the former *depend* on SPL_ARM_PSCI_FW. This allows to enable CONFIG_SYSRESET_PSCI on platforms without SPL PSCI support. Signed-off-by: Andre Przywara <andre.przywara(a)arm.com> --- drivers/sysreset/Kconfig | 8 +++++++- drivers/sysreset/Makefile | 2 +- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 49c0787b26d..62fe9eb6220 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -119,11 +119,17 @@ config SYSRESET_PALMAS config SYSRESET_PSCI bool "Enable support for PSCI System Reset" depends on ARM_PSCI_FW - select SPL_ARM_PSCI_FW if SPL help Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware must be running on your system. +config SYSRESET_SPL_PSCI + bool "Enable support for PSCI System Reset in SPL" + depends on SPL_ARM_PSCI_FW + help + Enable PSCI SYSTEM_RESET function call in the SPL. To use this, PSCI + firmware must be running on your system before the SPL. + config SYSRESET_SBI bool "Enable support for SBI System Reset" depends on RISCV_SMODE && SBI_V02 diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index e0e732205df..8d992ae0930 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o obj-$(CONFIG_$(SPL_TPL_)SYSRESET_PALMAS) += sysreset_palmas.o -obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o +obj-$(CONFIG_$(SPL_TPL_)SYSRESET_PSCI) += sysreset_psci.o obj-$(CONFIG_SYSRESET_SBI) += sysreset_sbi.o obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o -- 2.35.8

2 2

[PATCH v3 00/19] EFI: ti: Enable EFI capsule updates
by Jonathan Humphreys 24 Apr '24

24 Apr '24

Enable on disk capsule updates, which includes defining the firmware components (tiboot3, spl, u-boot) and enabling processing of raw capsule updates. This is enabled for several TI SoC based platforms: AM64, AM62, AM62p, BeaglePlay, J7, and BeagleboneAI. This series also includes enabling seral flash DFU for AM62 and MMC DFU for beagleplay. Changes from v1: - Added sysfw.itb capsule definition to beagleboneai64 - removed extra commas in structure definitions Changes from v2: - Added documentation on OSPI flash layouts - Improved comments for capsule GUIDs definitions - Defined board unique capsule GUIDs and put definitions in board specific files - Added a Capsule Update porting section to the documentation Jonathan Humphreys (19): doc: uefi: capsules: Start Capsule Update porting section board: am64x: Define capsule update firmware info configs: am64x: Enable EFI capsule update doc: board: ti: am64x: document OSPI layout board: j721e: Define capsule update firmware info configs: j721e: Enable EFI capsule update doc: board: ti: j721e: document OSPI layout board: beagleplay: Define capsule update firmware info configs: beagleplay: Enable DFU for MMC configs: beagleplay: Enable EFI capsule update board: am62px: Define capsule update firmware info configs: am62px: Enable EFI capsule update doc: board: ti: am62px: document OSPI layout configs: am62x: Enable serial flash DFU board: am62x: Define capsule update firmware info configs: am62x: Enable EFI capsule update doc: board: ti: am62x: document OSPI layout board: beagleboneai64: Define capsule update firmware info configs: beagleboneai64: Enable EFI capsule update board/beagle/beagleboneai64/Kconfig | 4 +- board/beagle/beagleboneai64/beagleboneai64.c | 38 +++++++++ board/beagle/beagleplay/Kconfig | 4 +- board/beagle/beagleplay/beagleplay.c | 33 ++++++++ board/ti/am62px/evm.c | 32 ++++++++ board/ti/am62x/evm.c | 32 ++++++++ board/ti/am64x/evm.c | 33 ++++++++ board/ti/j721e/evm.c | 38 +++++++++ configs/am62px_evm_a53_defconfig | 2 + configs/am62x_beagleplay_a53_defconfig | 5 ++ configs/am62x_evm_a53_defconfig | 3 + configs/am64x_evm_a53_defconfig | 2 + configs/j721e_beagleboneai64_a72_defconfig | 2 + configs/j721e_evm_a72_defconfig | 2 + doc/board/ti/am62px_sk.rst | 48 +++++++++++ doc/board/ti/am62x_sk.rst | 48 +++++++++++ doc/board/ti/am64x_evm.rst | 48 +++++++++++ doc/board/ti/j721e_evm.rst | 85 +++++++++++++------- doc/develop/uefi/uefi.rst | 12 +++ include/configs/am62px_evm.h | 24 ++++++ include/configs/am62x_evm.h | 24 ++++++ include/configs/am64x_evm.h | 24 ++++++ include/configs/beagleboneai64.h | 55 +++++++++++++ include/configs/beagleplay.h | 41 ++++++++++ include/configs/j721e_evm.h | 29 +++++++ 25 files changed, 635 insertions(+), 33 deletions(-) create mode 100644 include/configs/beagleboneai64.h create mode 100644 include/configs/beagleplay.h -- 2.34.1

4 23

[PATCH 1/4] arm: davinci: Migrate da850-evm to OF_UPSTREAM
by Adam Ford 24 Apr '24

24 Apr '24

The da850-evm can remove the U-Boot device trees if migrated to OF_UPSTREAM. This means pointing the device trees to the ti/davinci directory. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/arch/arm/dts/da850-evm.dts b/arch/arm/dts/da850-evm.dts deleted file mode 100644 index 378af9f344..0000000000 --- a/arch/arm/dts/da850-evm.dts +++ /dev/null @@ -1,453 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree for DA850 EVM board - * - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; -#include "da850.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - compatible = "ti,da850-evm", "ti,da850"; - model = "DA850/AM1808/OMAP-L138 EVM"; - - chosen { - stdout-path = &serial2; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - ethernet0 = &eth0; - spi0 = &spi1; - }; - - backlight: backlight-pwm { - pinctrl-names = "default"; - pinctrl-0 = <&ecap2_pins>; - power-supply = <&backlight_lcd>; - compatible = "pwm-backlight"; - /* - * The PWM here corresponds to production hardware. The - * schematic needs to be 1015171 (15 March 2010), Rev A - * or newer. - */ - pwms = <&ecap2 0 50000 0>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; - default-brightness-level = <7>; - }; - - panel { - compatible = "ti,tilcdc,panel"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - /* - * The vpif and the LCD are mutually exclusive. - * To enable VPIF, change the status below to 'disabled' then - * then change the status of the vpif below to 'okay' - */ - status = "okay"; - enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */ - - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <16>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - - display-timings { - native-mode = <&timing0>; - timing0: 480x272 { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <3>; - hback-porch = <2>; - hsync-len = <42>; - vback-porch = <3>; - vfront-porch = <4>; - vsync-len = <11>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - baseboard_3v3: fixedregulator-3v3 { - /* TPS73701DCQ */ - compatible = "regulator-fixed"; - regulator-name = "baseboard_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vbat>; - regulator-always-on; - regulator-boot-on; - }; - - baseboard_1v8: fixedregulator-1v8 { - /* TPS73701DCQ */ - compatible = "regulator-fixed"; - regulator-name = "baseboard_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vbat>; - regulator-always-on; - regulator-boot-on; - }; - - backlight_lcd: backlight-regulator { - compatible = "regulator-fixed"; - regulator-name = "lcd_backlight_pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; /* lcd_backlight_pwr */ - enable-active-high; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "DA850-OMAPL138 EVM"; - simple-audio-card,widgets = - "Line", "Line In", - "Line", "Line Out"; - simple-audio-card,routing = - "LINE1L", "Line In", - "LINE1R", "Line In", - "Line Out", "LLOUT", - "Line Out", "RLOUT"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&link0_codec>; - simple-audio-card,frame-master = <&link0_codec>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp0>; - system-clock-frequency = <24576000>; - }; - - link0_codec: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <24576000>; - }; - }; -}; - -&ecap2 { - status = "okay"; -}; - -&ref_clk { - clock-frequency = <24000000>; -}; - -&pmx_core { - status = "okay"; - - mcasp0_pins: pinmux_mcasp0_pins { - pinctrl-single,bits = < - /* - * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR, - * AFSR, AMUTE - */ - 0x00 0x11111111 0xffffffff - /* AXR11, AXR12 */ - 0x04 0x00011000 0x000ff000 - >; - }; - nand_pins: nand_pins { - pinctrl-single,bits = < - /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */ - 0x1c 0x10110110 0xf0ff0ff0 - /* - * EMA_D[0], EMA_D[1], EMA_D[2], - * EMA_D[3], EMA_D[4], EMA_D[5], - * EMA_D[6], EMA_D[7] - */ - 0x24 0x11111111 0xffffffff - /* EMA_A[1], EMA_A[2] */ - 0x30 0x01100000 0x0ff00000 - >; - }; -}; - -&sata { - status = "okay"; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&rtc0 { - status = "okay"; -}; - -&lcdc { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - tps: tps@48 { - reg = <0x48>; - }; - tlv320aic3106: tlv320aic3106@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x18>; - status = "okay"; - - /* Regulators */ - IOVDD-supply = <&vdcdc2_reg>; - AVDD-supply = <&baseboard_3v3>; - DRVDD-supply = <&baseboard_3v3>; - DVDD-supply = <&baseboard_1v8>; - }; - tca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - tca6416_bb: gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&wdt { - status = "okay"; -}; - -&mmc0 { - max-frequency = <50000000>; - bus-width = <4>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio 65 GPIO_ACTIVE_HIGH>; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins &spi1_cs0_pin>; - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p64"; - spi-max-frequency = <30000000>; - m25p,fast-read; - reg = <0>; - partition@0 { - label = "U-Boot-SPL"; - reg = <0x00000000 0x00010000>; - read-only; - }; - partition@1 { - label = "U-Boot"; - reg = <0x00010000 0x00080000>; - read-only; - }; - partition@2 { - label = "U-Boot-Env"; - reg = <0x00090000 0x00010000>; - read-only; - }; - partition@3 { - label = "Kernel"; - reg = <0x000a0000 0x00280000>; - }; - partition@4 { - label = "Filesystem"; - reg = <0x00320000 0x00400000>; - }; - partition@5 { - label = "MAC-Address"; - reg = <0x007f0000 0x00010000>; - read-only; - }; - }; -}; - -&mdio { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - bus_freq = <2200000>; -}; - -&eth0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mii_pins>; -}; - -&gpio { - status = "okay"; -}; - -/include/ "tps6507x.dtsi" - -&tps { - vdcdc1_2-supply = <&vbat>; - vdcdc3-supply = <&vbat>; - vldo1_2-supply = <&vbat>; - - regulators { - vdcdc1_reg: regulator@0 { - regulator-name = "VDCDC1_3.3V"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3450000>; - regulator-always-on; - regulator-boot-on; - }; - - vdcdc2_reg: regulator@1 { - regulator-name = "VDCDC2_3.3V"; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <3450000>; - regulator-always-on; - regulator-boot-on; - ti,defdcdc_default = <1>; - }; - - vdcdc3_reg: regulator@2 { - regulator-name = "VDCDC3_1.2V"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - ti,defdcdc_default = <1>; - }; - - ldo1_reg: regulator@3 { - regulator-name = "LDO1_1.8V"; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <1890000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo2_reg: regulator@4 { - regulator-name = "LDO2_1.2V"; - regulator-min-microvolt = <1140000>; - regulator-max-microvolt = <1320000>; - regulator-always-on; - regulator-boot-on; - }; - }; -}; - -&mcasp0 { - #sound-dai-cells = <0>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins>; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializer */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 0 0 - 0 0 0 0 - 0 0 0 1 - 2 0 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&edma0 { - ti,edma-reserved-slot-ranges = <32 50>; -}; - -&edma1 { - ti,edma-reserved-slot-ranges = <32 90>; -}; - -&aemif { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins>; - status = "okay"; - cs3 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <3>; - - nand@2000000,0 { - compatible = "ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x02000000 0x02000000 - 1 0x00000000 0x00008000>; - - ti,davinci-chipselect = <1>; - ti,davinci-mask-ale = <0>; - ti,davinci-mask-cle = <0>; - ti,davinci-mask-chipsel = <0>; - ti,davinci-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - ti,davinci-nand-use-bbt; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&vpif { - pinctrl-names = "default"; - pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>; - /* - * The vpif and the LCD are mutually exclusive. - * To enable VPIF, disable the ti,tilcdc,panel then - * change the status below to 'okay' - */ - status = "disabled"; -}; diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 25c5db4991..8fa2660a0c 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -9,6 +9,7 @@ config TARGET_DA850EVM select MACH_DAVINCI_DA850_EVM select SOC_DA850 select SUPPORT_SPL + imply OF_UPSTREAM config TARGET_OMAPL138_LCDK bool "OMAPL138 LCDK" diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 8130575926..05f29337dc 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -18,7 +18,7 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x80000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="da850-evm" +CONFIG_DEFAULT_DEVICE_TREE="ti/davinci/da850-evm" CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x8001ff00 diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 4d6efbebf3..936de61071 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -14,7 +14,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8001ff00 CONFIG_ENV_SIZE=0x2800 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="da850-evm" +CONFIG_DEFAULT_DEVICE_TREE="ti/davinci/da850-evm" CONFIG_SYS_LOAD_ADDR=0xc0700000 CONFIG_ENV_ADDR=0x60100000 CONFIG_LTO=y diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 330f88183c..2a4ea808f4 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -15,7 +15,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0000f20 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x0 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="da850-evm" +CONFIG_DEFAULT_DEVICE_TREE="ti/davinci/da850-evm" CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x8001ff00 -- 2.43.0

2 7

[PATCH 1/3] mach-ipq40xx: add CPU specific code
by Robert Marko 24 Apr '24

24 Apr '24

Provide basic DRAM info population from DT, cache setting and the board_init stub. Signed-off-by: Robert Marko <robert.marko(a)sartura.hr> --- arch/arm/mach-ipq40xx/Makefile | 7 ++++++ arch/arm/mach-ipq40xx/cpu.c | 44 ++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) create mode 100644 arch/arm/mach-ipq40xx/Makefile create mode 100644 arch/arm/mach-ipq40xx/cpu.c diff --git a/arch/arm/mach-ipq40xx/Makefile b/arch/arm/mach-ipq40xx/Makefile new file mode 100644 index 0000000000..d611de9933 --- /dev/null +++ b/arch/arm/mach-ipq40xx/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2024 Sartura Ltd. +# +# Author: Robert Marko <robert.marko(a)sartura.hr> + +obj-y += cpu.o diff --git a/arch/arm/mach-ipq40xx/cpu.c b/arch/arm/mach-ipq40xx/cpu.c new file mode 100644 index 0000000000..0446627a8f --- /dev/null +++ b/arch/arm/mach-ipq40xx/cpu.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * CPU code for Qualcomm IPQ40xx SoC + * + * Copyright (c) 2024 Sartura Ltd. + * + * Author: Robert Marko <robert.marko(a)sartura.hr> + */ + +#include <common.h> +#include <cpu_func.h> +#include <init.h> + +int dram_init(void) +{ + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + return fdtdec_setup_mem_size_base(); +} + +/* + * Enable/Disable D-cache. + * I-cache is already enabled in start.S + */ +void enable_caches(void) +{ + dcache_enable(); +} + +void disable_caches(void) +{ + dcache_disable(); +} + +/* + * In case boards need specific init code, they can override this stub. + */ +int __weak board_init(void) +{ + return 0; +} -- 2.44.0

2 5

[PATCH 00/10] Add support for Ethernet Boot on SK-AM62
by Siddharth Vadapalli 24 Apr '24

24 Apr '24

Hello, This series enables Ethernet Boot on SK-AM62 device. Product Link: https://www.ti.com/tool/SK-AM62 User Guide: https://www.ti.com/lit/pdf/spruj40 Ethernet Boot flow is as follows: 1. The BOOT MODE pins are configured for Ethernet Boot. 2. On powering on the device, ROM uses the Ethernet Port corresponding to CPSW3G's MAC Port 1 to transmit "TI K3 Bootp Boot". 3. The TFTP server and DHCP server on the receiver device need to be configured such that VCI string "TI K3 Bootp Boot" maps to the file "tiboot3.bin" and the TFTP server should be capable of transferring it to the device. 4. ROM loads and executes "tiboot3.bin" provided by the TFTP server. 5. The "tiboot3.bin" file is expected to be built using the config: am62x_evm_r5_ethboot_defconfig introduced in this series, which shall enable "tispl.bin" to be fetched over TFTP using "tiboot3.bin". 6. "tiboot3.bin" is configured to transmit "AM62X U-Boot R5 SPL" as its NET_VCI_STRING, thereby implying that the DHCP server and TFTP server need to be configured to transfer "tispl.bin" to the device. 7. "tiboot3.bin" loads and executes "tispl.bin" provided by the TFTP server. 8. The "tispl.bin" file is expected to be built using the config: am62x_evm_a53_defconfig which has been updated in this series to enable Ethernet Boot specific configs, allowing "u-boot.img" to be fetched over TFTP using "tispl.bin". 9. "tispl.bin" is configured to transmit "AM62X U-Boot A53 SPL" as its NET_VCI_STRING. The DHCP server and TFTP server need to be configured to transfer "u-boot.img" to the device for the aforementioned NET_VCI_STRING. 10. "tispl.bin" then fetches "u-boot.img" using TFTP and loads and executes it on the device, completing the process of Ethernet Boot on the device. NOTE: ROM configures CPSW3G's MAC Port 1 for 100 Mbps full-duplex mode of operation due to which it is expected that the Link Partner also supports the same mode of operation. Additionally, enabling "phy_gmii_sel" node at SPL stage will be necessary and is not added as a part of this series with the aim of adding the "bootph-all" property to its counterpart in Linux device-tree first. This series is based on commit: f28a77589e Merge tag 'dm-next-7jan23' of https://source.denx.de/u-boot/custodians/u-boot-dm into next of the next branch of u-boot. Regards, Siddharth. Andreas Dannenberg (1): arm: mach-k3: am62: Update SoC autogenerated data to enable Ethernet Boot Kishon Vijay Abraham I (7): board: ti: am62x: Init DRAM size in R5/A53 SPL firmware: ti_sci: Add No-OP for "RX_FL_CFG" soc: ti: k3-navss-ringacc: Initialize base address of ring cfg registers dma: ti: k3-udma: Add support for native configuration of chan/flow arm: mach-k3: am625_init: Probe AM65 CPSW NUSS configs: am62: Add configs for enabling ETHBOOT in R5SPL configs: am62x_evm_a53_defconfig: Enable configs required for Ethboot Siddharth Vadapalli (1): arm: dts: k3-am625-r5-sk: Enable DM services for main_pktdma Vignesh Raghavendra (1): soc: ti: k3-navss-ringacc: Fix reset ring API arch/arm/dts/k3-am625-r5-sk.dts | 5 ++ arch/arm/mach-k3/am625_init.c | 10 +++ arch/arm/mach-k3/r5/am62x/clk-data.c | 79 ++++++++-------- board/ti/am62x/evm.c | 3 + configs/am62x_evm_a53_defconfig | 8 ++ configs/am62x_evm_r5_ethboot_defconfig | 110 +++++++++++++++++++++++ drivers/dma/ti/k3-udma.c | 6 ++ drivers/firmware/ti_sci.c | 8 +- drivers/soc/ti/k3-navss-ringacc-u-boot.c | 9 +- drivers/soc/ti/k3-navss-ringacc.c | 7 +- 10 files changed, 202 insertions(+), 43 deletions(-) create mode 100644 configs/am62x_evm_r5_ethboot_defconfig -- 2.34.1

6 50

[PATCH] mtd: spi-nor: Add support to exit 4-byte mode
by Tejas Bhumkar 24 Apr '24

24 Apr '24

The Kria board features a recovery application that activates when the FW_EN button is pressed. Upon power-up flash operates in 3B mode, However, the recovery application changes it back to 4B mode. Following a reset, u-boot activates the CONFIG_SPI_FLASH_BAR and expects the flash to be in 3B mode. However, there's no code to handle this configuration. to address this issue, changes were made to disable the 4B mode when the CONFIG_SPI_FLASH_BAR is enabled. Additionally, spi_nor_wait_till_ready() was included because there is operation that places the device in a busy state before performing a nor read. Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar(a)amd.com> --- drivers/mtd/spi/spi-nor-core.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index f86003ca8c..47f65a4f5e 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1464,6 +1464,9 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, else read_len = remain_len; #endif + ret = spi_nor_wait_till_ready(nor); + if (ret) + goto read_err; ret = nor->read(nor, addr, read_len, buf); if (ret == 0) { @@ -4161,6 +4164,7 @@ int spi_nor_scan(struct spi_nor *nor) #else /* Configure the BAR - discover bank cmds and read current bank */ nor->addr_width = 3; + set_4byte(nor, info, 0); ret = read_bar(nor, info); if (ret < 0) return ret; -- 2.37.6

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