February 2024 - U-Boot

[PATCH 0/7] imx8mp: Enable PCIe/NVMe support
by Sumit Garg 23 Feb '24

23 Feb '24

pcie_imx doesn't seem to share any useful code for iMX8MP SoC and it is rather tied to quite old port of pcie_designware driver from Linux which suffices only iMX6 specific needs. But currently we have the common DWC specific bits which alligns pretty well with DW PCIe controller on iMX8MP SoC. So lets reuse those common bits instead as a new driver for iMX8 SoCs. It should be fairly easy to add support for other iMX8 variants to this driver. iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we can reuse the generic PHY infrastructure to power on PCIe PHY. Patch #1: Adds PCIe clocks support. Patch #2: Adds i.MX8MP reset controller support. Patch #3: Extend i.MX8MP power domain driver with PCIe support Patch #4: Expose high performance PLL clock required for PCIe PHY on verdin board. Patch #5: Adds standalone PCIe PHY support for i.MX8MP SoC. Patch #6: Adds DW PCIe controller support for iMX8MP SoC. Patch #7: Enable PCIe/NVMe support for verdin board. Testing with this patch-set included: Verdin iMX8MP # pci enum PCIE-0: Link up (Gen1-x1, Bus0) Verdin iMX8MP # Verdin iMX8MP # nvme scan Verdin iMX8MP # Verdin iMX8MP # nvme info Device 0: Vendor: 0x126f Rev: T0828A0 Prod: AA000000000000000720 Type: Hard Disk Capacity: 122104.3 MB = 119.2 GB (250069680 x 512) Verdin iMX8MP # Verdin iMX8MP # load nvme 0 $loadaddr <file-name> Sumit Garg (7): clk: imx8mp: Add support for PCIe clocks reset: imx: Add support for i.MX8MP reset controller imx8mp: power-domain: Add PCIe support imx8mp: power-domain: Expose high performance PLL clock phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY pci: Add DW PCIe controller support for iMX8MP SoC verdin-imx8mp_defconfig: Enable PCIe/NVMe support configs/verdin-imx8mp_defconfig | 9 + drivers/clk/imx/clk-imx8mp.c | 6 + drivers/pci/Kconfig | 8 + drivers/pci/Makefile | 1 + drivers/pci/pcie_dw_imx8.c | 348 ++++++++++++++++++++++++++ drivers/phy/Kconfig | 9 + drivers/phy/Makefile | 1 + drivers/phy/phy-imx8m-pcie.c | 246 ++++++++++++++++++ drivers/power/domain/imx8mp-hsiomix.c | 121 ++++++++- drivers/reset/reset-imx7.c | 114 +++++++++ 10 files changed, 859 insertions(+), 4 deletions(-) create mode 100644 drivers/pci/pcie_dw_imx8.c create mode 100644 drivers/phy/phy-imx8m-pcie.c -- 2.34.1

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[RESEND PATCH v2] arm64: zynqmp: Support semihosting boot method
by Sean Anderson 23 Feb '24

23 Feb '24

Currently, when we boot from JTAG we try to boot U-Boot from RAM. However, this is a bit tricky to time, since the debugger has to wait for SPL to initialize RAM before it can load U-Boot. This can result in long waits, since occasionally initializing RAM (and other things in psu_init) takes a long time to complete and the debugger must wait for this worst case. Support semihosting if it is enabled, as it lets U-Boot tell the debugger when we are ready for the image. This means we don't have to wait any more than necessary. We don't change the default config to ensure we don't break compatibility with existing debuggers that don't expect us to hit semihosting breakpoints. Signed-off-by: Sean Anderson <sean.anderson(a)linux.dev> --- I'm resending this from my linux.dev email as my regular email is mangling my patches. Changes in v2: - Fix typo in subject arch/arm/mach-zynqmp/spl.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index a0f35f36faa..5af735aa5ce 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -9,6 +9,7 @@ #include <image.h> #include <init.h> #include <log.h> +#include <semihosting.h> #include <spl.h> #include <linux/delay.h> @@ -66,6 +67,11 @@ void spl_board_init(void) } #endif +static u32 jtag_boot_device(void) +{ + return semihosting_enabled() ? BOOT_DEVICE_SMH : BOOT_DEVICE_RAM; +} + void board_boot_order(u32 *spl_boot_list) { spl_boot_list[0] = spl_boot_device(); @@ -75,7 +81,7 @@ void board_boot_order(u32 *spl_boot_list) if (spl_boot_list[0] == BOOT_DEVICE_MMC2) spl_boot_list[1] = BOOT_DEVICE_MMC1; - spl_boot_list[2] = BOOT_DEVICE_RAM; + spl_boot_list[2] = jtag_boot_device(); } u32 spl_boot_device(void) @@ -97,7 +103,7 @@ u32 spl_boot_device(void) switch (bootmode) { case JTAG_MODE: - return BOOT_DEVICE_RAM; + return jtag_boot_device(); #ifdef CONFIG_SPL_MMC case SD_MODE1: case SD1_LSHFT_MODE: /* not working on silicon v1 */ -- 2.35.1.1320.gc452695387.dirty

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[PATCH 0/2] Enable OSPI on j721e
by Jonathan Humphreys 23 Feb '24

23 Feb '24

This series enables OSPI storage and boot. fixes: 58d61fb5a77ef31f6aa5973b3ef9650c92edf5ed ("arm: dts: k3-j721e-sk: Add initial A72 specific dts support") Jonathan Humphreys (2): configs: j721e: Enable OSPI memory arm: mach-k3: j721e: Enable OSPI boot arch/arm/mach-k3/include/mach/j721e_spl.h | 5 +++-- arch/arm/mach-k3/j721e_init.c | 3 ++- configs/j721e_evm_a72_defconfig | 7 +++++++ configs/j721e_evm_r5_defconfig | 6 ++++++ 4 files changed, 18 insertions(+), 3 deletions(-) -- 2.34.1

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[PATCH] Check curve_name for null to avoid crash
by Bob Wolff 23 Feb '24

23 Feb '24

If mixed rsa and ecdsa keys are specified in dtsi, an rsa key can be sent into the ecdsa verify. Without the ecdsa,curve property, this function will crash due to lack of checking the null pointer return. Signed-off-by: Bob Wolff <bob.wolff68(a)gmail.com> --- lib/ecdsa/ecdsa-verify.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/lib/ecdsa/ecdsa-verify.c b/lib/ecdsa/ecdsa-verify.c index 0601700c4f..4d1835b598 100644 --- a/lib/ecdsa/ecdsa-verify.c +++ b/lib/ecdsa/ecdsa-verify.c @@ -31,6 +31,11 @@ static int fdt_get_key(struct ecdsa_public_key *key, const void *fdt, int node) int x_len, y_len; key->curve_name = fdt_getprop(fdt, node, "ecdsa,curve", NULL); + if (!key->curve_name) { + debug("Error: ecdsa cannot get 'ecdsa,curve' property from key. Likely not an ecdsa key.\n"); + return -ENOMSG; + } + key->size_bits = ecdsa_key_size(key->curve_name); if (key->size_bits == 0) { debug("Unknown ECDSA curve '%s'", key->curve_name); -- 2.39.3 (Apple Git-145)

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[PATCH v2] arm64: zynqmp: Support semihosting boot method
by Sean Anderson 22 Feb '24

22 Feb '24

From: Sean Anderson <sean.anderson(a)seco.com> Currently, when we boot from JTAG we try to boot U-Boot from RAM. However, this is a bit tricky to time, since the debugger has to wait for SPL to initialize RAM before it can load U-Boot. This can result in long waits, since occasionally initializing RAM (and other things in psu_init) takes a long time to complete and the debugger must wait for this worst case. Support semihosting if it is enabled, as it lets U-Boot tell the debugger when we are ready for the image. This means we don't have to wait any more than necessary. We don't change the default config to ensure we don't break compatibility with existing debuggers that don't expect us to hit semihosting breakpoints. Signed-off-by: Sean Anderson <sean.anderson(a)linux.dev> --- I'm resending this from my linux.dev email as my regular email is mangling my patches. Changes in v2: - Fix typo in subject arch/arm/mach-zynqmp/spl.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index a0f35f36faa..5af735aa5ce 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -9,6 +9,7 @@ #include <image.h> #include <init.h> #include <log.h> +#include <semihosting.h> #include <spl.h> #include <linux/delay.h> @@ -66,6 +67,11 @@ void spl_board_init(void) } #endif +static u32 jtag_boot_device(void) +{ + return semihosting_enabled() ? BOOT_DEVICE_SMH : BOOT_DEVICE_RAM; +} + void board_boot_order(u32 *spl_boot_list) { spl_boot_list[0] = spl_boot_device(); @@ -75,7 +81,7 @@ void board_boot_order(u32 *spl_boot_list) if (spl_boot_list[0] == BOOT_DEVICE_MMC2) spl_boot_list[1] = BOOT_DEVICE_MMC1; - spl_boot_list[2] = BOOT_DEVICE_RAM; + spl_boot_list[2] = jtag_boot_device(); } u32 spl_boot_device(void) @@ -97,7 +103,7 @@ u32 spl_boot_device(void) switch (bootmode) { case JTAG_MODE: - return BOOT_DEVICE_RAM; + return jtag_boot_device(); #ifdef CONFIG_SPL_MMC case SD_MODE1: case SD1_LSHFT_MODE: /* not working on silicon v1 */ -- 2.35.1.1320.gc452695387.dirty

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[PATCH 00/16] rockchip: add support for SARADCv2 and RK806 PMIC and regulators
by Quentin Schulz 22 Feb '24

22 Feb '24

The RK3588 has a new IP for SARADC compared to older SoCs of the same vendor but most of the boilerplate is shared, so rockchip-saradc.c driver is adapted instead of creating a new one. Because the SARADC requires a vref-supply which is commonly coming from a regulator of the RK806 PMIC, support for the RK806 PMIC and regulators are also added in this patch series. Finally, RK806 PMIC is the first one to actually support SPI as communication layer between the SoC and the PMIC (but supports I2C as well according to the datasheet). This adds support for RK806 over SPI though there should be no reason for RK806 over I2C to not work. Note that the DT now uses a different prefix for the buck and ldo node names and the RK806 is the first one to use nldo and pldo and while they both are LDOs, they have overlapping indices which makes it impossible to simply reuse the rk8xx_ldo driver and need to define new ones (though some callbacks can be reused, as is done in this patch series). The SARADC was tested by toggling the BIOS button connected over channel 0 on RK3588 Jaguar and using the adc or button commands to watch over the value. The PMIC was tested with the pmic command for reading the CHIP_VERS registers and writing to the WDT_REG (0x73). The regulators were tested by using a modified DT for RK3588 Jaguar and playing with the regulator command to enable/disable some buck/nldo/pldo and modify their output voltage. This has a light dependency on https://lore.kernel.org/u-boot/20240221-jaguar-v3-0-1f256a82201b@theobroma-… because of: - remove of asm/io.h include in favor of asm/arch-rockchip/hardware.h (both should be included if applied before the dependency) - Jaguar defconfig modified in this patch series is added in the aforementioned patch series, Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- Quentin Schulz (15): rockchip: spi: rk_spi: do not write bytes when in read-only mode regulator: rk8xx: remove unused functions regulator: rk8xx: add indirection level for some ldo callbacks power: rk8xx: add support for RK806 pmic: reword help text rockchip: adc: rockchip-saradc: use union for preparing for v2 rockchip: adc: rockchip-saradc: factor out channel_data callback rockchip: adc: rockchip-saradc: factor out start_channel callback rockchip: adc: rockchip-saradc: factor out stop callback rockchip: adc: rockchip-saradc: add support for RK3588 power: pmic: rk8xx: fix duplicate prompt rockchip: jaguar-rk3588: enable SARADC and derivatives adc: add missing depends on ADC for controller drivers button: add missing ADC dependency for BUTTON_ADC rockchip: boot_mode: fix rockchip_dnl_key_pressed requiring ADC support William Wu (1): regulator: rk8xx: fix SWITCH enable on RK809 arch/arm/mach-rockchip/boot_mode.c | 4 + cmd/pmic.c | 4 +- configs/jaguar-rk3588_defconfig | 11 +- drivers/adc/Kconfig | 4 + drivers/adc/rockchip-saradc.c | 176 +++++++++-- drivers/button/Kconfig | 1 + drivers/power/pmic/Kconfig | 2 +- drivers/power/pmic/rk8xx.c | 85 ++++++ drivers/power/regulator/rk8xx.c | 595 ++++++++++++++++++++++++++++++++++--- drivers/spi/rk_spi.c | 20 +- include/power/rk8xx_pmic.h | 21 +- 11 files changed, 848 insertions(+), 75 deletions(-) --- base-commit: dcf1b0a056cc81dc268d449c6e689fe80ca688ae change-id: 20240212-rk3588-saradc-ab0a9bda9306 Best regards, -- Quentin Schulz <quentin.schulz(a)theobroma-systems.com>

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[PATCH] arm64: zynqmp: Support semhosting boot method
by Sean Anderson 22 Feb '24

22 Feb '24

Currently, when we boot from JTAG we try to boot U-Boot from RAM. However, this is a bit tricky to time, since the debugger has to wait for SPL to initialize RAM before it can load U-Boot. This can result in long waits, since occasionally initializing RAM (and other things in psu_init) takes a long time to complete and the debugger must wait for this worst case. Support semihosting if it is enabled, as it lets U-Boot tell the debugger when we are ready for the image. This means we don't have to wait any more than necessary. We don't change the default config to ensure we don't break compatibility with existing debuggers that don't expect us to hit semihosting breakpoints. Signed-off-by: Sean Anderson <sean.anderson(a)seco.com> --- arch/arm/mach-zynqmp/spl.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index a0f35f36faa..5af735aa5ce 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -9,6 +9,7 @@ #include <image.h> #include <init.h> #include <log.h> +#include <semihosting.h> #include <spl.h> #include <linux/delay.h> @@ -66,6 +67,11 @@ void spl_board_init(void) } #endif +static u32 jtag_boot_device(void) +{ + return semihosting_enabled() ? BOOT_DEVICE_SMH : BOOT_DEVICE_RAM; +} + void board_boot_order(u32 *spl_boot_list) { spl_boot_list[0] = spl_boot_device(); @@ -75,7 +81,7 @@ void board_boot_order(u32 *spl_boot_list) if (spl_boot_list[0] == BOOT_DEVICE_MMC2) spl_boot_list[1] = BOOT_DEVICE_MMC1; - spl_boot_list[2] = BOOT_DEVICE_RAM; + spl_boot_list[2] = jtag_boot_device(); } u32 spl_boot_device(void) @@ -97,7 +103,7 @@ u32 spl_boot_device(void) switch (bootmode) { case JTAG_MODE: - return BOOT_DEVICE_RAM; + return jtag_boot_device(); #ifdef CONFIG_SPL_MMC case SD_MODE1: case SD1_LSHFT_MODE: /* not working on silicon v1 */ -- 2.35.1.1320.gc452695387.dirty [Embedded World 2024, SECO SpA]<https://www.messe-ticket.de/Nuernberg/embeddedworld2024/Register/ew24517689>

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[PULL] Please pull qcom/qcom-fixes-2024.04
by Caleb Connolly 22 Feb '24

22 Feb '24

Hi Tom, Just a few button fixes that I realise should probably make it in. The following changes since commit 37345abb97ef0dd9c50a03b2a72617612dcae585: Prepare v2024.04-rc2 (2024-02-13 18:16:57 -0500) are available in the Git repository at: git@source.denx.de:/u-boot/custodians/u-boot-snapdragon.git qcom-fixes-2024.04 for you to fetch changes up to 22f391e8be11986bae824509470cf11e7bac31b0: button: qcom-pmic: demote "unknown button" message to debug (2024-02-14 17:21:50 +0000) ---------------------------------------------------------------- Caleb Connolly (1): button: qcom-pmic: demote "unknown button" message to debug Dan Carpenter (1): button: qcom-pmic: fix some error checking drivers/button/button-qcom-pmic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

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[PATCH] arch: mach-k3: fix mapping higher DDR addresses as device memory
by Neha Malcom Francis 22 Feb '24

22 Feb '24

From: Sekhar Nori <nsekhar(a)ti.com> An entry in memory map table for MMU configuration is spilling over and inadvertently mapping DDR available at higher address (above 4GB address space) as device memory (nGnRnE). Fix this by adjusting entry size. Tested on AM62A SK by enabling CONFIG_CMD_TIME. Before this patch: => time crc32 0x881000000 0x20000000 crc32 for 881000000 ... 8a0ffffff ==> 5a7a5760 time: 1 minutes, 14.715 seconds After patch: => time crc32 0x881000000 0x20000000 crc32 for 881000000 ... 8a0ffffff ==> 3df1ce02 time: 2.711 seconds Signed-off-by: Sekhar Nori <nsekhar(a)ti.com> [n-francis(a)ti.com: rebased on next, retested on all devices inc. commit] Signed-off-by: Neha Malcom Francis <n-francis(a)ti.com> Cc: Andrew Davis <afd(a)ti.com> --- Boot logs: https://gist.github.com/nehamalcom/7b101ea8b97f5a9433a553ef881166a1 arch/arm/mach-k3/arm64-mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index b4308205b2..0e07b1b7ce 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -41,7 +41,7 @@ struct mm_region k3_mem_map[] = { }, { .virt = 0x500000000UL, .phys = 0x500000000UL, - .size = 0x400000000UL, + .size = 0x380000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN -- 2.34.1

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[PATCH] ARM: Enable CONFIG_64BIT for static analysis
by Dan Carpenter 22 Feb '24

22 Feb '24

In the Makefile there is a line that says this: # the checker needs the correct machine size CHECKFLAGS += $(if $(CONFIG_64BIT),-m64,-m32) So set CONFIG_64BIT so that we don't pass -m32 to the static checker. Signed-off-by: Dan Carpenter <dan.carpenter(a)linaro.org> --- arch/arm/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fde85dc0d537..4c7be7cf9c33 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1,11 +1,15 @@ menu "ARM architecture" depends on ARM +config 64BIT + bool + config SYS_ARCH default "arm" config ARM64 bool + select 64BIT select PHYS_64BIT select SYS_CACHE_SHIFT_6 imply SPL_SEPARATE_BSS -- 2.43.0

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