February 2024 - U-Boot

[RFC] rockchip: spl: Support reading FIT from eMMC boot partition
by Jonas Karlman 02 Feb '24

02 Feb '24

Enable support for loading FIT from eMMC boot partition when SUPPORT_EMMC_BOOT Kconfig option is enabled. FIT is only loaded from boot partition when the boot partition is set to boot0 (1) or boo1 (2) in the extcsd partition config. FIT is read from sector 1024 (512 KiB) of the configured boot partition. Following can be used to write U-Boot to boot partition 1 of eMMC: # Load TPL+SPL from SD-card => load mmc 1:1 20000000 idbloader.img => mmc dev 0 # Access eMMC user partition => mmc partconf 0 0 0 0 # Write TPL+SPL to eMMC user partition (512 KiB @ 32 KiB) => mmc write 20000000 40 400 # Load FIT from SD-card => load mmc 1:1 20000000 u-boot.itb => mmc dev 0 # Access eMMC boot partition 1 => mmc partconf 0 0 0 1 # Write FIT to eMMC boot partition 1 (2 MiB @ 512 KiB) => mmc write 20000000 400 1000 # Configure to use boot partition 1 => mmc partconf 0 0 1 0 # Show partition config => mmc partconf 0 Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- - Is loading FIT from emmc boot partition a feature of intereset to anyone else? - I used a @ 512 KiB offset for FIT, should leave enough space for e.g. TPL/SPL, vendor storage or environment before FIT. - Is @ 512 KiB offset a good default option? Or would e.g. @ 0 or @ 32KiB a more apropriate offset? - This does not add kind of fallback to use the normal @ 8 MiB offset in user partition. Is that something that would be needed? --- arch/arm/mach-rockchip/spl.c | 23 +++++++++++++++++++++++ configs/generic-rk3568_defconfig | 1 + configs/generic-rk3588_defconfig | 1 + 3 files changed, 25 insertions(+) diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index c4d3983a6735..2015d9d72dbd 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -68,9 +68,32 @@ u32 spl_boot_device(void) u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { + if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT) && !IS_SD(mmc)) { + switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) { + case 1: + case 2: + /* Read FIT from a boot partition */ + return MMCSD_MODE_EMMCBOOT; + } + } + return MMCSD_MODE_RAW; } +unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect) +{ + if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT) && !IS_SD(mmc)) { + switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) { + case 1: + case 2: + /* Read FIT from sector 1024 (512 KiB) of boot partition */ + return 0x400; + } + } + + return raw_sect; +} + #define TIMER_LOAD_COUNT_L 0x00 #define TIMER_LOAD_COUNT_H 0x04 #define TIMER_CONTROL_REG 0x10 diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig index 18a62b0033a0..b90ecb643dc7 100644 --- a/configs/generic-rk3568_defconfig +++ b/configs/generic-rk3568_defconfig @@ -51,6 +51,7 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_MISC=y # CONFIG_ROCKCHIP_IODOMAIN is not set CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig index 4755b27c1dea..a9329eb1c625 100644 --- a/configs/generic-rk3588_defconfig +++ b/configs/generic-rk3588_defconfig @@ -52,6 +52,7 @@ CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_MISC=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_DW=y -- 2.43.0

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Help Needed: No UART Output in Mainline U-Boot on MT7620A (ZBT WE826-T2)
by Richard Thanki 02 Feb '24

02 Feb '24

Dear U-Boot Community, I am working on porting mainline U-Boot to a standard MT7620A wireless router, specifically the ZBT WE826-T2 (https://openwrt.org/toh/zbtlink/we-826). After building and flashing the mainline U-Boot, I'm encountering an issue where there is no output over UART. So far, I've tried the default configurations for both MT7620 RFB and MT7620-MT7530 RFB targets, with the latter being more of an experimental test as my board lacks a gigabit switch. I’m flashing the standard `u-boot.bin` image. I’ve tried disabling the 'skip low-level configuration' in 'make menuconfig,’ but the issue persists. Despite these efforts, the router's behaviour remains unchanged, showing the same LED behaviour (one of the led’s infrequently but regularly flashing) whether the new U-Boot is flashed or the flash chip is entirely erased. In comparing the Device Trees (DTs) for OpenWrt: - https://github.com/openwrt/openwrt/blob/master/target/linux/ramips/dts/mt76… - https://github.com/openwrt/openwrt/blob/master/target/linux/ramips/dts/mt76… with those in U-Boot - https://github.com/u-boot/u-boot/blob/master/arch/mips/dts/mediatek%2Cmt762… - https://github.com/u-boot/u-boot/blob/master/arch/mips/dts/mt7620.dtsi both look similar to all important characteristics. I noticed both use the uartlite for serial. I’m using Ubuntu 20.04 to compile using OpenWrt’s pre-built toolchain. Any insights or guidance on this matter would be greatly appreciated, especially if someone has experience with UART issues on MT7620A-based hardware in mainline U-Boot. Resolving this could pave the way for easier ports to similar devices. Thank you in advance for your support. Rich

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Re: [PATCH] sunxi: dram: h6: fix the unreliability related to the DDR3 sequence
by Andre Przywara 01 Feb '24

01 Feb '24

On Mon, 22 Jan 2024 22:15:30 +0100 patrick9876(a)free.fr wrote: Hi Patrick, > From: Patrick Lerda <patrick9876(a)free.fr> > > Indeed, the DDR3 has a non-zero probability to not be properly > initialized. This could be the PLL that is not locked or anything else. > When this happens and the code tests the correct board configuration, > the proper board configuration is not set. The board could end with > half the expected memory size, or u-boot could stall. > > This change adds a loop to execute the DDR3 sequence again until the > stable state is reached. > > My H6 TX6 board was prone to this issue. Once fixed with this change, > the same board can now handle 10000+ consecutive reboots properly. That's certainly an interesting approach, though I feel like it papers over something. So for instance if the PLL is not locked, we should rather fix that than going the Windows way (retry, reboot, reinstall) ;-) But indeed there are some reports about instability of the DRAM init, reporting twice the size being a common issue. For a start, can you try to apply this series? https://patchwork.ozlabs.org/project/uboot/list/?series=378679 Also there is this patch: https://lore.kernel.org/u-boot/20231001161336.31140-2-viraniac@gmail.com/ And while I am still a bit sceptical about this solution, this looks better than just retrying to me. I would be grateful if you could test these patches and report back. Cheers, Andre > Fixes: ec9cdaaa13d ("sunxi: dram: h6: Improve DDR3 config detection") > Signed-off-by: Patrick Lerda <patrick9876(a)free.fr> > --- > arch/arm/mach-sunxi/dram_sun50i_h6.c | 207 ++++++++++++++------------- > 1 file changed, 111 insertions(+), 96 deletions(-) > > diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c > index 62bc2a0231..462adb1c9e 100644 > --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c > +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c > @@ -420,116 +420,131 @@ static bool mctl_channel_init(struct dram_para *para) > (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; > struct sunxi_mctl_phy_reg * const mctl_phy = > (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; > - int i; > + int i, j = 0; > u32 val; > > - setbits_le32(&mctl_ctl->dfiupd[0], BIT(31) | BIT(30)); > - setbits_le32(&mctl_ctl->zqctl[0], BIT(31) | BIT(30)); > - writel(0x2f05, &mctl_ctl->sched[0]); > - setbits_le32(&mctl_ctl->rfshctl3, BIT(0)); > - setbits_le32(&mctl_ctl->dfimisc, BIT(0)); > - setbits_le32(&mctl_ctl->unk_0x00c, BIT(8)); > - clrsetbits_le32(&mctl_phy->pgcr[1], 0x180, 0xc0); > - /* TODO: non-LPDDR3 types */ > - clrsetbits_le32(&mctl_phy->pgcr[2], GENMASK(17, 0), ns_to_t(7800)); > - clrbits_le32(&mctl_phy->pgcr[6], BIT(0)); > - clrsetbits_le32(&mctl_phy->dxccr, 0xee0, 0x220); > - /* TODO: VT compensation */ > - clrsetbits_le32(&mctl_phy->dsgcr, BIT(0), 0x440060); > - clrbits_le32(&mctl_phy->vtcr[1], BIT(1)); > - > - for (i = 0; i < 4; i++) > - clrsetbits_le32(&mctl_phy->dx[i].gcr[0], 0xe00, 0x800); > - for (i = 0; i < 4; i++) > - clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, 0x5555); > - for (i = 0; i < 4; i++) > - clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, 0x1010); > - > - udelay(100); > + do { > + setbits_le32(&mctl_ctl->dfiupd[0], BIT(31) | BIT(30)); > + setbits_le32(&mctl_ctl->zqctl[0], BIT(31) | BIT(30)); > + writel(0x2f05, &mctl_ctl->sched[0]); > + setbits_le32(&mctl_ctl->rfshctl3, BIT(0)); > + setbits_le32(&mctl_ctl->dfimisc, BIT(0)); > + setbits_le32(&mctl_ctl->unk_0x00c, BIT(8)); > + clrsetbits_le32(&mctl_phy->pgcr[1], 0x180, 0xc0); > + /* TODO: non-LPDDR3 types */ > + clrsetbits_le32(&mctl_phy->pgcr[2], GENMASK(17, 0), > + ns_to_t(7800)); > + clrbits_le32(&mctl_phy->pgcr[6], BIT(0)); > + clrsetbits_le32(&mctl_phy->dxccr, 0xee0, 0x220); > + /* TODO: VT compensation */ > + clrsetbits_le32(&mctl_phy->dsgcr, BIT(0), 0x440060); > + clrbits_le32(&mctl_phy->vtcr[1], BIT(1)); > > - if (para->ranks == 2) > - setbits_le32(&mctl_phy->dtcr[1], 0x30000); > - else > - clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000); > + for (i = 0; i < 4; i++) > + clrsetbits_le32(&mctl_phy->dx[i].gcr[0], 0xe00, 0x800); > + for (i = 0; i < 4; i++) > + clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, > + 0x5555); > + for (i = 0; i < 4; i++) > + clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, > + 0x1010); > > - if (sunxi_dram_is_lpddr(para->type)) > - clrbits_le32(&mctl_phy->dtcr[1], BIT(1)); > - if (para->ranks == 2) { > - writel(0x00010001, &mctl_phy->rankidr); > - writel(0x20000, &mctl_phy->odtcr); > - } else { > - writel(0x0, &mctl_phy->rankidr); > - writel(0x10000, &mctl_phy->odtcr); > - } > + udelay(100); > > - /* set bits [3:0] to 1? 0 not valid in ZynqMP d/s */ > - if (para->type == SUNXI_DRAM_TYPE_LPDDR3) > - clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040); > - else > - clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000000); > - if (para->clk <= 792) { > - if (para->clk <= 672) { > - if (para->clk <= 600) > - val = 0x300; > - else > - val = 0x400; > + if (para->ranks == 2) > + setbits_le32(&mctl_phy->dtcr[1], 0x30000); > + else > + clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000); > + > + if (sunxi_dram_is_lpddr(para->type)) > + clrbits_le32(&mctl_phy->dtcr[1], BIT(1)); > + if (para->ranks == 2) { > + writel(0x00010001, &mctl_phy->rankidr); > + writel(0x20000, &mctl_phy->odtcr); > } else { > - val = 0x500; > + writel(0x0, &mctl_phy->rankidr); > + writel(0x10000, &mctl_phy->odtcr); > } > - } else { > - val = 0x600; > - } > - /* FIXME: NOT REVIEWED YET */ > - clrsetbits_le32(&mctl_phy->zq[0].zqcr, 0x700, val); > - clrsetbits_le32(&mctl_phy->zq[0].zqpr[0], 0xff, > - CONFIG_DRAM_ZQ & 0xff); > - clrbits_le32(&mctl_phy->zq[0].zqor[0], 0xfffff); > - setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ >> 8) & 0xff); > - setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xf00) - 0x100); > - setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xff00) << 4); > - clrbits_le32(&mctl_phy->zq[1].zqpr[0], 0xfffff); > - setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ >> 16) & 0xff); > - setbits_le32(&mctl_phy->zq[1].zqpr[0], ((CONFIG_DRAM_ZQ >> 8) & 0xf00) - 0x100); > - setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ & 0xff0000) >> 4); > - if (para->type == SUNXI_DRAM_TYPE_LPDDR3) { > - for (i = 1; i < 14; i++) > - writel(0x06060606, &mctl_phy->acbdlr[i]); > - } > > - val = PIR_ZCAL | PIR_DCAL | PIR_PHYRST | PIR_DRAMINIT | PIR_QSGATE | > - PIR_RDDSKW | PIR_WRDSKW | PIR_RDEYE | PIR_WREYE; > - if (para->type == SUNXI_DRAM_TYPE_DDR3) > - val |= PIR_DRAMRST | PIR_WL; > - mctl_phy_pir_init(val); > + /* set bits [3:0] to 1? 0 not valid in ZynqMP d/s */ > + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) > + clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, > + 0x10000040); > + else > + clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, > + 0x10000000); > + if (para->clk <= 792) { > + if (para->clk <= 672) { > + if (para->clk <= 600) > + val = 0x300; > + else > + val = 0x400; > + } else { > + val = 0x500; > + } > + } else { > + val = 0x600; > + } > + /* FIXME: NOT REVIEWED YET */ > + clrsetbits_le32(&mctl_phy->zq[0].zqcr, 0x700, val); > + clrsetbits_le32(&mctl_phy->zq[0].zqpr[0], 0xff, > + CONFIG_DRAM_ZQ & 0xff); > + clrbits_le32(&mctl_phy->zq[0].zqor[0], 0xfffff); > + setbits_le32(&mctl_phy->zq[0].zqor[0], > + (CONFIG_DRAM_ZQ >> 8) & 0xff); > + setbits_le32(&mctl_phy->zq[0].zqor[0], > + (CONFIG_DRAM_ZQ & 0xf00) - 0x100); > + setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xff00) > + << 4); > + clrbits_le32(&mctl_phy->zq[1].zqpr[0], 0xfffff); > + setbits_le32(&mctl_phy->zq[1].zqpr[0], > + (CONFIG_DRAM_ZQ >> 16) & 0xff); > + setbits_le32(&mctl_phy->zq[1].zqpr[0], > + ((CONFIG_DRAM_ZQ >> 8) & 0xf00) - 0x100); > + setbits_le32(&mctl_phy->zq[1].zqpr[0], > + (CONFIG_DRAM_ZQ & 0xff0000) >> 4); > + if (para->type == SUNXI_DRAM_TYPE_LPDDR3) { > + for (i = 1; i < 14; i++) > + writel(0x06060606, &mctl_phy->acbdlr[i]); > + } > > - /* TODO: DDR4 types ? */ > - for (i = 0; i < 4; i++) > - writel(0x00000909, &mctl_phy->dx[i].gcr[5]); > + val = PIR_ZCAL | PIR_DCAL | PIR_PHYRST | PIR_DRAMINIT | > + PIR_QSGATE | PIR_RDDSKW | PIR_WRDSKW | PIR_RDEYE | > + PIR_WREYE; > + if (para->type == SUNXI_DRAM_TYPE_DDR3) > + val |= PIR_DRAMRST | PIR_WL; > + mctl_phy_pir_init(val); > > - for (i = 0; i < 4; i++) { > - if (IS_ENABLED(CONFIG_DRAM_ODT_EN)) > - val = 0x0; > - else > - val = 0xaaaa; > - clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, val); > + /* TODO: DDR4 types ? */ > + for (i = 0; i < 4; i++) > + writel(0x00000909, &mctl_phy->dx[i].gcr[5]); > > - if (IS_ENABLED(CONFIG_DRAM_ODT_EN)) > - val = 0x0; > - else > - val = 0x2020; > - clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, val); > - } > + for (i = 0; i < 4; i++) { > + if (IS_ENABLED(CONFIG_DRAM_ODT_EN)) > + val = 0x0; > + else > + val = 0xaaaa; > + clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, val); > > - mctl_bit_delay_set(para); > - udelay(1); > + if (IS_ENABLED(CONFIG_DRAM_ODT_EN)) > + val = 0x0; > + else > + val = 0x2020; > + clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, val); > + } > > - setbits_le32(&mctl_phy->pgcr[6], BIT(0)); > - clrbits_le32(&mctl_phy->pgcr[6], 0xfff8); > - for (i = 0; i < 4; i++) > - clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff); > - udelay(10); > + mctl_bit_delay_set(para); > + udelay(1); > + > + setbits_le32(&mctl_phy->pgcr[6], BIT(0)); > + clrbits_le32(&mctl_phy->pgcr[6], 0xfff8); > + for (i = 0; i < 4; i++) > + clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff); > + udelay(10); > + val = readl(&mctl_phy->pgsr[0]) & 0xff00000; > + } while (val && j++ < 64); > > - if (readl(&mctl_phy->pgsr[0]) & 0xff00000) { > + if (val) { > /* Oops! There's something wrong! */ > debug("PLL = %x\n", readl(0x3001010)); > debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0]));

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[PATCH 1/1] sunxi: sun4i: Introduce KConfig option SPL_SYS_CLK_FREQ
by Ludwig Kormann 01 Feb '24

01 Feb '24

This option can be used to modify the initial SPL CPU clock frequency. This follows an earlier discussion regarding A20 CPUs dying after reboot in SPL initialization due to incompatible CPU clock frequency and core voltage. [1] First attempt was to update PLL1_CFG_DEFAULT to a fixed lower frequency (144MHz), which fixed the observed issue but might not suit all A20 users. A KConfig option should be the better solution. [1] https://lists.denx.de/pipermail/u-boot/2024-January/544897.html Signed-off-by: Ludwig Kormann <ludwig.kormann(a)ict42.de> --- arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 4 ++++ arch/arm/mach-sunxi/Kconfig | 8 ++++++++ arch/arm/mach-sunxi/clock_sun4i.c | 11 ++++++++++- 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 2cec91cb20..11b350824e 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -134,12 +134,16 @@ struct sunxi_ccm_reg { #define CCM_PLL1_CFG_PLL4_EXCH_SHIFT 25 #define CCM_PLL1_CFG_BIAS_CUR_SHIFT 20 #define CCM_PLL1_CFG_DIVP_SHIFT 16 +#define CCM_PLL1_CFG_DIVP_MASK (0x3 << CCM_PLL1_CFG_DIVP_SHIFT) #define CCM_PLL1_CFG_LCK_TMR_SHIFT 13 #define CCM_PLL1_CFG_FACTOR_N_SHIFT 8 +#define CCM_PLL1_CFG_FACTOR_N_MASK (0x1f << CCM_PLL1_CFG_FACTOR_N_SHIFT) #define CCM_PLL1_CFG_FACTOR_K_SHIFT 4 +#define CCM_PLL1_CFG_FACTOR_K_MASK (0x3 << CCM_PLL1_CFG_FACTOR_K_SHIFT) #define CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT 3 #define CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT 2 #define CCM_PLL1_CFG_FACTOR_M_SHIFT 0 +#define CCM_PLL1_CFG_FACTOR_M_MASK (0x3 << CCM_PLL1_CFG_FACTOR_M_SHIFT) #define PLL1_CFG_DEFAULT 0xa1005000 diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index fe89aec6b9..85e3a26855 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -705,6 +705,14 @@ config SYS_CLK_FREQ default 1008000000 if MACH_SUN50I_H616 default 1008000000 if MACH_SUN8I_R528 +if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I +config SPL_SYS_CLK_FREQ + int "sunxi SPL CPU clock frequency" + default 384 + ---help--- + A static value for the sunxi SPL CPU frequency, must be a multiple of 24. +endif + config SYS_CONFIG_NAME default "suniv" if MACH_SUNIV default "sun4i" if MACH_SUN4I diff --git a/arch/arm/mach-sunxi/clock_sun4i.c b/arch/arm/mach-sunxi/clock_sun4i.c index 8f1d1b65f0..04623c1d09 100644 --- a/arch/arm/mach-sunxi/clock_sun4i.c +++ b/arch/arm/mach-sunxi/clock_sun4i.c @@ -25,7 +25,16 @@ void clock_init_safe(void) APB0_DIV_1 << APB0_DIV_SHIFT | CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, &ccm->cpu_ahb_apb0_cfg); - writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); + writel((PLL1_CFG_DEFAULT & + ~(CCM_PLL1_CFG_FACTOR_N_MASK | + CCM_PLL1_CFG_FACTOR_K_MASK | + CCM_PLL1_CFG_FACTOR_M_MASK | + CCM_PLL1_CFG_DIVP_MASK)) | + (CONFIG_SPL_SYS_CLK_FREQ / 24) << CCM_PLL1_CFG_FACTOR_N_SHIFT | + 0 << CCM_PLL1_CFG_FACTOR_K_SHIFT | + 0 << CCM_PLL1_CFG_FACTOR_M_SHIFT | + 0 << CCM_PLL1_CFG_DIVP_SHIFT, + &ccm->pll1_cfg); sdelay(200); writel(AXI_DIV_1 << AXI_DIV_SHIFT | AHB_DIV_2 << AHB_DIV_SHIFT | -- 2.39.2

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[PATCH 1/1] doc: board: starfive: fix rendering of OpenSBI logo
by Heinrich Schuchardt 01 Feb '24

01 Feb '24

The rendering of the OpenSBI logo should look like the screen output. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- doc/board/starfive/visionfive2.rst | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/doc/board/starfive/visionfive2.rst b/doc/board/starfive/visionfive2.rst index 6cb033ead04..abda8ac21bc 100644 --- a/doc/board/starfive/visionfive2.rst +++ b/doc/board/starfive/visionfive2.rst @@ -133,14 +133,14 @@ Sample boot log from StarFive VisionFive2 board Trying to boot from MMC2 OpenSBI v1.2-80-g4b28afc - ____ _____ ____ _____ - / __ \ / ____| _ \_ _| + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| | | | |_ __ ___ _ __ | (___ | |_) || | | | | | '_ \ / _ \ '_ \ \___ \| _ < | | | |__| | |_) | __/ | | |____) | |_) || |_ - \____/| .__/ \___|_| |_|_____/|___/_____| - | | - |_| + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| Platform Name : StarFive VisionFive 2 v1.3B Platform Features : medeleg -- 2.43.0

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[PATCH 1/1] sunxi: sun4i: add missing sdelay() to clock_init_safe()
by Ludwig Kormann 01 Feb '24

01 Feb '24

This delay is required after switching the clock source. See “A20 Reference manual v1.4” Page 50 / section “1.5.4.16. CPU/AHB/APB0 CLOCK RATIO”: “If the clock source is changed, at most to wait for 8 present running clock cycles.” This is already implemented in clock_set_pll1(), but was still missing in clock_init_safe(). Signed-off-by: Ludwig Kormann <ludwig.kormann(a)ict42.de> --- arch/arm/mach-sunxi/clock_sun4i.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-sunxi/clock_sun4i.c b/arch/arm/mach-sunxi/clock_sun4i.c index 8f1d1b65f0..ac3b7a801f 100644 --- a/arch/arm/mach-sunxi/clock_sun4i.c +++ b/arch/arm/mach-sunxi/clock_sun4i.c @@ -25,6 +25,7 @@ void clock_init_safe(void) APB0_DIV_1 << APB0_DIV_SHIFT | CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, &ccm->cpu_ahb_apb0_cfg); + sdelay(20); writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); sdelay(200); writel(AXI_DIV_1 << AXI_DIV_SHIFT | @@ -32,6 +33,7 @@ void clock_init_safe(void) APB0_DIV_1 << APB0_DIV_SHIFT | CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, &ccm->cpu_ahb_apb0_cfg); + sdelay(20); #ifdef CONFIG_MACH_SUN7I setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); #endif -- 2.39.2

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[GIT PULL] Please pull u-boot-amlogic-fixes-20240201
by Neil Armstrong 01 Feb '24

01 Feb '24

Hi Tom, Please pull this simple fix avoiding printing the board model twice. Thanks, Neil The following changes since commit 6faba41927bdc8973b59678649ef83c564cc421e: Prepare v2024.04-rc1 (2024-01-29 20:53:19 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-amlogic.git tags/u-boot-amlogic-fixes-20240201 for you to fetch changes up to 076529725f16f07a5cb2d5feba25d62b5f5a5872: ARM: meson: stop printing board model after sysinfo update (2024-01-30 09:35:51 +0100) ---------------------------------------------------------------- - stop printing board model twice after sysinfo update ---------------------------------------------------------------- Neil Armstrong (1): ARM: meson: stop printing board model after sysinfo update arch/arm/mach-meson/board-info.c | 10 ---------- 1 file changed, 10 deletions(-)

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Please pull u-boot-watchdog/master
by Stefan Roese 01 Feb '24

01 Feb '24

Hi Tom, please pull the following watchdog related last minute fixes: ---------------------------------------------------------------- - add andes atcwdt200 support (Randolph) ---------------------------------------------------------------- Here the Azure build, without any issues: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=339&view=results Thanks, Stefan The following changes since commit b6d8969bcb94321dfed1399f2eaa8768ba42caaa: Merge tag 'u-boot-at91-2024.04-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 (2024-01-31 10:44:33 -0500) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-watchdog.git for you to fetch changes up to 094eda0660d419f35e10c49fade75a6738a56137: configs: andes: add watchdog support fot andes ae350 (2024-02-01 09:08:44 +0100) ---------------------------------------------------------------- Randolph (2): drivers: watchdog: add andes atcwdt200 support configs: andes: add watchdog support fot andes ae350 configs/ae350_rv32_defconfig | 4 + configs/ae350_rv32_spl_defconfig | 4 + configs/ae350_rv32_spl_xip_defconfig | 4 + configs/ae350_rv32_xip_defconfig | 4 + configs/ae350_rv64_defconfig | 4 + configs/ae350_rv64_spl_defconfig | 4 + configs/ae350_rv64_spl_xip_defconfig | 4 + configs/ae350_rv64_xip_defconfig | 4 + drivers/watchdog/Kconfig | 6 + drivers/watchdog/Makefile | 1 + drivers/watchdog/atcwdt200_wdt.c | 220 +++++++++++++++++++++++++++++++++++ 11 files changed, 259 insertions(+) create mode 100644 drivers/watchdog/atcwdt200_wdt.c

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[PATCH 0/3] usb: ehci-generic: setup a bulk of phy when possible
by Yang Xiwen via B4 Relay 01 Feb '24

01 Feb '24

one USB controller can have multiple ports specified in dts, all of them should be setup to make use of all possible ports. Signed-off-by: Yang Xiwen <forbidden405(a)outlook.com> --- Yang Xiwen (3): phy: add generic_setup(shutdown)_phy_bulk() test: phy: test generic_setup(shutdown)_phy_bulk() usb: ehci: Make usage of generic_{setup,shutdown}_phy_bulk() helpers drivers/phy/phy-uclass.c | 33 +++++++++++++++++++++++++++++++++ drivers/usb/host/ehci-generic.c | 8 ++++---- include/generic-phy.h | 29 +++++++++++++++++++++++++++++ test/dm/phy.c | 4 ++++ 4 files changed, 70 insertions(+), 4 deletions(-) --- base-commit: b6d8969bcb94321dfed1399f2eaa8768ba42caaa change-id: 20240201-ehci-6c3aa7d97932 Best regards, -- Yang Xiwen <forbidden405(a)outlook.com>

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[PATCH V4 1/2] drivers: watchdog: add andes atcwdt200 support
by Randolph 01 Feb '24

01 Feb '24

This patch adds an implementation of the Andes watchdog ATCWDT200 driver. Signed-off-by: CL Wang <cl634(a)andestech.com> Signed-off-by: Randolph <randolph(a)andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang(a)andestech.com> --- drivers/watchdog/Kconfig | 6 + drivers/watchdog/Makefile | 1 + drivers/watchdog/atcwdt200_wdt.c | 220 +++++++++++++++++++++++++++++++ 3 files changed, 227 insertions(+) create mode 100644 drivers/watchdog/atcwdt200_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 569726119c..8318fd77a3 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -130,6 +130,12 @@ config WDT_AT91 Select this to enable Microchip watchdog timer, which can be found on some AT91 devices. +config WDT_ATCWDT200 + bool "Andes watchdog timer support" + depends on WDT + help + Select this to enable Andes ATCWDT200 watchdog timer + config WDT_BCM6345 bool "BCM6345 watchdog timer support" depends on WDT && (ARCH_BMIPS || BCM6856 || \ diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 5520d3d9ae..7b39adcf0f 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_WDT_ARM_SMC) += arm_smc_wdt.o obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o +obj-$(CONFIG_WDT_ATCWDT200) += atcwdt200_wdt.o obj-$(CONFIG_WDT_BCM2835) += bcm2835_wdt.o obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o diff --git a/drivers/watchdog/atcwdt200_wdt.c b/drivers/watchdog/atcwdt200_wdt.c new file mode 100644 index 0000000000..a29b42d607 --- /dev/null +++ b/drivers/watchdog/atcwdt200_wdt.c @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation. + * + */ + +#include <asm/io.h> +#include <dm.h> +#include <hang.h> +#include <linux/bitops.h> +#include <wdt.h> + +#define NODE_NOT_FOUND 0xFFFFFFFF + +#define WDT_WP_MAGIC 0x5aa5 +#define WDT_RESTART_MAGIC 0xcafe + +/* Control Register */ +#define REG_WDT_ID 0x00 +#define REG_WDT_CFG 0x10 +#define REG_WDT_RS 0x14 +#define REG_WDT_WE 0x18 +#define REG_WDT_STA 0x1C + +#define RST_TIME_OFF 8 +#define RST_TIME_MSK (0x7 << RST_TIME_OFF) +#define RST_CLK_128 (0 << RST_TIME_OFF) +#define RST_CLK_256 (1 << RST_TIME_OFF) +#define RST_CLK_512 (2 << RST_TIME_OFF) +#define RST_CLK_1024 (3 << RST_TIME_OFF) +#define INT_TIME_OFF 4 +#define INT_TIME_MSK (0xf << INT_TIME_OFF) +#define INT_CLK_2_6 (0 << INT_TIME_OFF) /* clk period*2^6 */ +#define INT_CLK_2_8 (1 << INT_TIME_OFF) /* clk period*2^8 */ +#define INT_CLK_2_10 (2 << INT_TIME_OFF) /* clk period*2^10 */ +#define INT_CLK_2_11 (3 << INT_TIME_OFF) /* clk period*2^11 */ +#define INT_CLK_2_12 (4 << INT_TIME_OFF) /* clk period*2^12 */ +#define INT_CLK_2_13 (5 << INT_TIME_OFF) /* clk period*2^13 */ +#define INT_CLK_2_14 (6 << INT_TIME_OFF) /* clk period*2^14 */ +#define INT_CLK_2_15 (7 << INT_TIME_OFF) /* clk period*2^15 */ +#define INT_CLK_2_17 (8 << INT_TIME_OFF) /* clk period*2^17 */ +#define INT_CLK_2_19 (9 << INT_TIME_OFF) /* clk period*2^19 */ +#define INT_CLK_2_21 (10 << INT_TIME_OFF) /* clk period*2^21 */ +#define INT_CLK_2_23 (11 << INT_TIME_OFF) /* clk period*2^23 */ +#define INT_CLK_2_25 (12 << INT_TIME_OFF) /* clk period*2^25 */ +#define INT_CLK_2_27 (13 << INT_TIME_OFF) /* clk period*2^27 */ +#define INT_CLK_2_29 (14 << INT_TIME_OFF) /* clk period*2^29 */ +#define INT_CLK_2_31 (15 << INT_TIME_OFF) /* clk period*2^31 */ +#define INT_CLK_MIN 0x0 +#define INT_CLK_MAX_16B 0x7 +#define INT_CLK_MAX_32B 0xF +#define RST_EN BIT(3) +#define INT_EN BIT(2) +#define CLK_PCLK BIT(1) +#define WDT_EN BIT(0) +#define INT_EXPIRED BIT(0) + +#define INT_TIME_ARRAY 16 +#define RST_TIME_ARRAY 8 + +struct wdt_priv { + void __iomem *base; + u32 wdt_clk_src; + u32 clk_freq; + u8 max_clk; +}; + +static inline u8 atcwdt_get_2_power_of_n(u8 index, u8 type) +{ + const u8 div_int[INT_TIME_ARRAY] = {6, 8, 10, 11, 12, 13, 14, 15, + 17, 19, 21, 23, 25, 27, 29, 31}; + const u8 div_rst[RST_TIME_ARRAY] = {7, 8, 9, 10, 11, 12, 13, 14}; + const u8 *pdiv; + + if (type == RST_TIME_ARRAY) + pdiv = div_rst; + else + pdiv = div_int; + + if (index >= type) + index = type - 1; + + return pdiv[index]; +} + +static u8 atcwdt_search_msb(u64 freq_ms, u8 type) +{ + u64 result; + u64 freq_sec; + u8 index; + + freq_sec = freq_ms / 1000; + for (index = 0; index < type; index++) { + result = freq_sec >> atcwdt_get_2_power_of_n(index, type); + + if (result <= 1) + break; + } + + return index; +} + +static int atcwdt_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + struct wdt_priv *priv = dev_get_priv(dev); + u64 rst_max_count; + u32 rst_max_time_ms; + u64 rst_time_ms; + u64 int_time_ms; + u8 rst_time; + u8 int_time; + + rst_max_count = 1 << atcwdt_get_2_power_of_n(RST_TIME_ARRAY, RST_TIME_ARRAY); + rst_max_time_ms = (rst_max_count * 1000) / priv->clk_freq; + + if (timeout > rst_max_time_ms) { + int_time_ms = timeout - rst_max_time_ms; + rst_time_ms = rst_max_time_ms; + } else { + int_time_ms = 0; + rst_time_ms = timeout; + } + + rst_time = atcwdt_search_msb(rst_time_ms * priv->clk_freq, RST_TIME_ARRAY); + + if (int_time_ms) { + int_time = atcwdt_search_msb(int_time_ms * priv->clk_freq, INT_TIME_ARRAY); + if (int_time > priv->max_clk) + int_time = priv->max_clk; + } else { + int_time = 0; + } + + writel(WDT_WP_MAGIC, priv->base + REG_WDT_WE); + writel(((rst_time << RST_TIME_OFF) & RST_TIME_MSK) | ((int_time << INT_TIME_OFF) & + INT_TIME_MSK) | INT_EN | RST_EN | priv->wdt_clk_src | WDT_EN, + priv->base + REG_WDT_CFG); + + return 0; +} + +static int atcwdt_wdt_stop(struct udevice *dev) +{ + struct wdt_priv *priv = dev_get_priv(dev); + + writel(WDT_WP_MAGIC, priv->base + REG_WDT_WE); + writel(0, priv->base + REG_WDT_CFG); + + return 0; +} + +static int atcwdt_wdt_restart(struct udevice *dev) +{ + struct wdt_priv *priv = dev_get_priv(dev); + + writel(WDT_WP_MAGIC, priv->base + REG_WDT_WE); + writel(WDT_RESTART_MAGIC, priv->base + REG_WDT_RS); + setbits_le32(priv->base + REG_WDT_STA, INT_EXPIRED); + + return 0; +} + +static int atcwdt_wdt_expire_now(struct udevice *dev, ulong flags) +{ + atcwdt_wdt_start(dev, 0, 0); + hang(); + + return 0; +} + +static int atcwdt_wdt_probe(struct udevice *dev) +{ + struct wdt_priv *priv = dev_get_priv(dev); + int timer_16bit; + + priv->base = dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EFAULT; + + priv->wdt_clk_src = dev_read_u32_default(dev, "clock-source", NODE_NOT_FOUND); + if (priv->wdt_clk_src == NODE_NOT_FOUND || priv->wdt_clk_src > 1) + priv->wdt_clk_src = CLK_PCLK; + + timer_16bit = dev_read_u32_default(dev, "16bit_timer", NODE_NOT_FOUND); + if (timer_16bit == 1 || timer_16bit == NODE_NOT_FOUND) + priv->max_clk = INT_CLK_MAX_16B; + else + priv->max_clk = INT_CLK_MAX_32B; + + priv->clk_freq = dev_read_u32_default(dev, "clock-frequency", NODE_NOT_FOUND); + if (priv->clk_freq == NODE_NOT_FOUND) { + printf("atcwdt200: Please provide a valid \"clock-frequency\" in DTB\n"); + return -EINVAL; + } + + atcwdt_wdt_stop(dev); + + return 0; +} + +static const struct wdt_ops atcwdt_wdt_ops = { + .start = atcwdt_wdt_start, + .reset = atcwdt_wdt_restart, + .stop = atcwdt_wdt_stop, + .expire_now = atcwdt_wdt_expire_now, +}; + +static const struct udevice_id atcwdt_wdt_ids[] = { + {.compatible = "andestech,atcwdt200"}, + {} +}; + +U_BOOT_DRIVER(atcwdt) = { + .name = "atcwdt200", + .id = UCLASS_WDT, + .probe = atcwdt_wdt_probe, + .of_match = atcwdt_wdt_ids, + .ops = &atcwdt_wdt_ops, + .priv_auto = sizeof(struct wdt_priv), +}; -- 2.34.1

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