February 2024 - U-Boot

[PATCH] arm64: zynqmp: Describe 25MHz fixed clock for PL GEMs
by Michal Simek 06 Feb '24

06 Feb '24

Describe 25Mhz fixed oscilator which is providing clock for PL based ethernet IPs. Physicially it is one chip but it is described as 2 fixed clock to be aligned with other SOM versions which were using integrated clock generators where clocks could be adjusted via i2c (si5332 chips). Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/zynqmp-sck-kd-g-revA.dtso | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index 766f78303eee..b3fc17cbd577 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -32,6 +32,18 @@ #clock-cells = <0>; clock-frequency = <26000000>; }; + + clk_25_0: clock4 { /* u92/u91 - GEM2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clk_25_1: clock5 { /* u92/u91 - GEM3 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; }; &can0 { -- 2.36.1

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[PATCH] configs: versal: Enable CONFIG_LTO for mini qspi/ospi
by Venkatesh Yadav Abbarapu 06 Feb '24

06 Feb '24

Adding a tiny bit more code for mini u-boot leads to a OCM image overflow. Fix this by enabling LTO for this board, so that such changes still can be made to the common U-Boot code. Enable building mini u-boot image with LTO, which results in about 8KB reduction in size. Signed-off-by: Michal Simek <michal.simek(a)amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- configs/xilinx_versal_mini_ospi_defconfig | 1 + configs/xilinx_versal_mini_qspi_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig index 72a123d965..7a110350c2 100644 --- a/configs/xilinx_versal_mini_ospi_defconfig +++ b/configs/xilinx_versal_mini_ospi_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_VERSAL_NO_DDR=y # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_LTO=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_AUTOBOOT is not set diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig index d9fbac986c..58945a1cac 100644 --- a/configs/xilinx_versal_mini_qspi_defconfig +++ b/configs/xilinx_versal_mini_qspi_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_VERSAL_NO_DDR=y # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_LTO=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_AUTOBOOT is not set -- 2.25.1

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[PATCH] configs: versal_net: Enable CONFIG_LTO for mini qspi/ospi
by Venkatesh Yadav Abbarapu 06 Feb '24

06 Feb '24

Adding a tiny bit more code for mini u-boot leads to a OCM image overflow. Fix this by enabling LTO for this board, so that such changes still can be made to the common U-Boot code. Enable building mini u-boot image with LTO, which results in about 8KB reduction in size. Signed-off-by: Michal Simek <michal.simek(a)amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- configs/xilinx_versal_net_mini_ospi_defconfig | 1 + configs/xilinx_versal_net_mini_qspi_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig index 5f42243d22..d78c9f8059 100644 --- a/configs/xilinx_versal_net_mini_ospi_defconfig +++ b/configs/xilinx_versal_net_mini_ospi_defconfig @@ -15,6 +15,7 @@ CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-ospi-single" CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0xBBF80000 +CONFIG_LTO=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_AUTOBOOT is not set diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig index 4fa83faa40..b0567f857a 100644 --- a/configs/xilinx_versal_net_mini_qspi_defconfig +++ b/configs/xilinx_versal_net_mini_qspi_defconfig @@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini-qspi-single" CONFIG_SYS_MEM_RSVD_FOR_MMU=y # CONFIG_PSCI_RESET is not set CONFIG_SYS_LOAD_ADDR=0xBBF80000 +CONFIG_LTO=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y # CONFIG_AUTOBOOT is not set -- 2.25.1

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[PATCH] arm64: zynqmp: Sync clock labels with kr260 revB
by Michal Simek 06 Feb '24

06 Feb '24

Board description describes the hard part of chip (PS) but programmable logic (PL) part is not described in this file. But clocks on the board are not only connected to PS but also wired to PL. And because two revisions are available where revA is using one si5332 and revB multiple clock chips using the same clock labels helping with keeping only one device tree overlay which targets PL. That's why synchronize clock labels and use labels from revB which are more generic. Unfortunately if there is driver for si5332 chip split could happen again but it is still worth to do it now and solve this issue when occurs. Reported-by: Sagar Karmarkar <sagar.karmarkar(a)amd.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index 7717abf7bd8a..39ca98a9d47f 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -25,37 +25,37 @@ io-channels = <&u14 0>, <&u14 1>, <&u14 2>; }; - si5332_0: si5332-0 { /* u17 - GEM0/1 */ + clk_125: si5332-0 { /* u17 - GEM0/1 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; - si5332_1: si5332-1 { /* u17 - DP */ + clk_27: si5332-1 { /* u17 - DP */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; - si5332_2: si5332-2 { /* u17 - USB */ + clk_26: si5332-2 { /* u17 - USB */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; - si5332_3: si5332-3 { /* u17 - SFP+ */ + clk_156: si5332-3 { /* u17 - SFP+ */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <156250000>; }; - si5332_4: si5332-4 { /* u17 - GEM2 */ + clk_25_0: si5332-4 { /* u17 - GEM2 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; - si5332_5: si5332-5 { /* u17 - GEM3 */ + clk_25_1: si5332-5 { /* u17 - GEM3 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; @@ -115,7 +115,7 @@ &psgtr { status = "okay"; /* gem0/1, dp, usb */ - clocks = <&si5332_0>, <&si5332_1>, <&si5332_2>; + clocks = <&clk_125>, <&clk_27>, <&clk_26>; clock-names = "ref0", "ref1", "ref2"; }; -- 2.36.1

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[PATCH] arm64: zynqmp: Add 'silabs, skip-recall' to all si570 clk nodes
by Michal Simek 06 Feb '24

06 Feb '24

From: Saeed Nowshadi <saeed.nowshadi(a)amd.com> Without 'silabs,skip-recall' property, the driver on System Controller re-calibrates the output clock frequency at probe() time based on the NVRAM setting. This re-calibration causes a glitch on the output clock. At power-on, Versal is also booting and expecting a glitch-free clock for its correct operation. System Controller should skip the re-calibration step to prevent any clock instability for Versal. Signed-off-by: Saeed Nowshadi <saeed.nowshadi(a)amd.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index f1b0a4aa65dd..0b97fa3f28ac 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -449,6 +449,7 @@ factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_zsfp_clk"; + silabs,skip-recall; }; }; i2c@6 { /* USER_SI570_1 */ @@ -463,6 +464,7 @@ factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "si570_user1"; + silabs,skip-recall; }; }; @@ -560,6 +562,7 @@ factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk2"; + silabs,skip-recall; }; }; i2c@5 { /* LPDDR4_SI570_CLK1 */ @@ -574,6 +577,7 @@ factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk1"; + silabs,skip-recall; }; }; i2c@6 { /* HSDP_SI570 */ @@ -588,6 +592,7 @@ factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; + silabs,skip-recall; }; }; i2c@7 { /* 8A34001 - U219B and J310 connector */ -- 2.36.1

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[PATCH] arm64: xilinx: Enable EFI_HTTP_BOOT by default
by Michal Simek 06 Feb '24

06 Feb '24

Enable EFI_HTTP_BOOT to be able to booting OS via http. In case of that dhcp server is not providing dns server IP set it up via setenv dnsip <ip addr>. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- I am ignoring defconfig sync because it needs to done because of cda3f81b06f5 ("cmd/flash: Make this default y for CFI and NOR only") anyway that's why I will just enable feature and Tom will run resync at some point to remove automatically selected options. --- configs/xilinx_versal_net_virt_defconfig | 1 + configs/xilinx_versal_virt_defconfig | 1 + configs/xilinx_zynqmp_kria_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 371d14eb89b7..0f1d990936f3 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -146,3 +146,4 @@ CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y CONFIG_TPM=y +CONFIG_EFI_HTTP_BOOT=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 5f76a305ab32..3c55dd8dcde9 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -153,3 +153,4 @@ CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y CONFIG_TPM=y +CONFIG_EFI_HTTP_BOOT=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index 0dc6c5b6877f..28b28f68411f 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -224,3 +224,4 @@ CONFIG_EFI_SET_TIME=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_HTTP_BOOT=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 2742e38b599e..1fcae45e95db 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -242,3 +242,4 @@ CONFIG_EFI_SET_TIME=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_HTTP_BOOT=y -- 2.36.1

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[PATCH] soc: zynqmp: Add the IDcode for dr_SE and eg_SE variants
by Venkatesh Yadav Abbarapu 06 Feb '24

06 Feb '24

ID code is added for zu67dr_SE, zu11eg_SE, zu19eg_SE and zu47dr_SE variants. SE is the select edition of restricted devices with the capabilities. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- drivers/soc/soc_xilinx_zynqmp.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index d9a5944965..786825d920 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -35,13 +35,15 @@ static const char zynqmp_family[] = "ZynqMP"; #define IDCODE2_PL_INIT_SHIFT 9 #define IDCODE2_PL_INIT_MASK BIT(IDCODE2_PL_INIT_SHIFT) -#define ZYNQMP_VERSION_SIZE 7 +#define ZYNQMP_VERSION_SIZE 10 enum { ZYNQMP_VARIANT_EG = BIT(0), ZYNQMP_VARIANT_EV = BIT(1), ZYNQMP_VARIANT_CG = BIT(2), ZYNQMP_VARIANT_DR = BIT(3), + ZYNQMP_VARIANT_DR_SE = BIT(4), + ZYNQMP_VARIANT_EG_SE = BIT(5), }; struct zynqmp_device { @@ -105,6 +107,11 @@ static const struct zynqmp_device zynqmp_devices[] = { .device = 11, .variants = ZYNQMP_VARIANT_EG, }, + { + .id = 0x04741093, + .device = 11, + .variants = ZYNQMP_VARIANT_EG_SE, + }, { .id = 0x04750093, .device = 15, @@ -120,6 +127,11 @@ static const struct zynqmp_device zynqmp_devices[] = { .device = 19, .variants = ZYNQMP_VARIANT_EG, }, + { + .id = 0x0475C093, + .device = 19, + .variants = ZYNQMP_VARIANT_EG_SE, + }, { .id = 0x047E1093, .device = 21, @@ -170,6 +182,11 @@ static const struct zynqmp_device zynqmp_devices[] = { .device = 47, .variants = ZYNQMP_VARIANT_DR, }, + { + .id = 0x047FA093, + .device = 47, + .variants = ZYNQMP_VARIANT_DR_SE, + }, { .id = 0x047FB093, .device = 48, @@ -185,6 +202,11 @@ static const struct zynqmp_device zynqmp_devices[] = { .device = 67, .variants = ZYNQMP_VARIANT_DR, }, + { + .id = 0x046d7093, + .device = 67, + .variants = ZYNQMP_VARIANT_DR_SE, + }, { .id = 0x04712093, .device = 24, @@ -271,8 +293,12 @@ static int soc_xilinx_zynqmp_detect_machine(struct udevice *dev, u32 idcode, "cg" : "eg", sizeof(priv->machine)); } else if (device->variants & ZYNQMP_VARIANT_EG) { strlcat(priv->machine, "eg", sizeof(priv->machine)); + } else if (device->variants & ZYNQMP_VARIANT_EG_SE) { + strlcat(priv->machine, "eg_SE", sizeof(priv->machine)); } else if (device->variants & ZYNQMP_VARIANT_DR) { strlcat(priv->machine, "dr", sizeof(priv->machine)); + } else if (device->variants & ZYNQMP_VARIANT_DR_SE) { + strlcat(priv->machine, "dr_SE", sizeof(priv->machine)); } return 0; -- 2.25.1

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[PATCH v2 0/4] phycore-imx8mp: Add USB support
by Benjamin Hahn 06 Feb '24

06 Feb '24

add support for various USB features like USB storage, USB mass storage as well as booting and flashing emmc via UUU. Signed-off-by: Benjamin Hahn <B.Hahn(a)phytec.de> --- Changes in v2: - sync kernel devicetree before making changes - Link to v1: https://lore.kernel.org/r/20240129-usb_support-v1-0-8bd2fe84005b@phytec.de --- Benjamin Hahn (4): imx8mp-phyboard-pollux-rdk: sync with kernel devicetree from v6.8-rc2 phycore-imx8mp: add USB host support phycore-imx8mp: add USB mass storage support phycore-imx8mp: add support for booting and flashing emmc via UUU .../arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 4 + arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 162 ++++++++++++++++++++- board/phytec/phycore_imx8mp/phycore-imx8mp.c | 4 + configs/phycore-imx8mp_defconfig | 33 ++++- include/configs/phycore_imx8mp.h | 5 + 5 files changed, 204 insertions(+), 4 deletions(-) --- base-commit: e7f9e5eb584dd0b5d1b1ff82fe607d6da9940cc6 change-id: 20240126-usb_support-403f47d71ac1 Best regards, -- Benjamin Hahn <B.Hahn(a)phytec.de>

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[PATCH] scripts: dtc-version: Don't show error messages
by Dragan Simic 06 Feb '24

06 Feb '24

Prevent the error messages produced by which(1), such as the one quoted below, from being visible in the build outputs. which: no dtc in (./scripts/dtc) This makes the build outputs look a tiny bit cleaner. Signed-off-by: Dragan Simic <dsimic(a)manjaro.org> --- scripts/dtc-version.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/dtc-version.sh b/scripts/dtc-version.sh index 53ff868bcdce..6d3d7b68fdfa 100755 --- a/scripts/dtc-version.sh +++ b/scripts/dtc-version.sh @@ -15,7 +15,7 @@ if [ ${#dtc} -eq 0 ]; then exit 1 fi -if ! which $dtc >/dev/null ; then +if ! which $dtc >/dev/null 2>/dev/null ; then echo "Error: Cannot find dtc: $dtc" exit 1 fi

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[PATCH v3 0/3] Random Number Generator fixes
by Weizhao Ouyang 06 Feb '24

06 Feb '24

This series aim to fix smccc bind issue and add a list command for RNG devices. Changelog: v2 --> v3 - remove fallback smc call - add Fixes tag v1 --> v2 - check SMCCC_ARCH_FEATURES - update commit message and rng help info Weizhao Ouyang (3): firmware: psci: Fix bind_smccc_features psci check driver: rng: Fix SMCCC TRNG crash cmd: rng: Add rng list command cmd/rng.c | 23 ++++++++++++++++++----- drivers/firmware/psci.c | 5 ++++- drivers/rng/smccc_trng.c | 2 +- include/linux/arm-smccc.h | 6 ++++++ 4 files changed, 29 insertions(+), 7 deletions(-) -- 2.39.2

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