February 2024 - U-Boot

[PATCH V5 0/2] firmware: ti_sci: zero the secure_hdr in do_xfer
by Dhruva Gole 07 Feb '24

07 Feb '24

This series adds a fix to make the initial 4 bytes of the secure_hdr to be 0 as per the protocol requirement as of now. Also, inorder to provide a little more context to people add a comment to explain why secure calls are made from uboot For context, please refer to the discussion from the first patch here: https://lore.kernel.org/all/20240124101558.184411-1-d-gole@ti.com/ Boot tested for sanity on AM62x SK and J721S2: https://gist.github.com/DhruvaG2000/9ca35d1261e8b30f1c2d4a514b9cd941 Changelog: v4 --> v5 Pick Nishanth's review and also s/sizeof(var)/sizeof(*var) in 1/2 v3 --> v4 Improve commit message in 1/2 and add comment in 2/2 v2 --> v3 Address Kamlesh's comment on v2: use sizeof(struct ti_sci_secure_msg_hdr) v1 --> v2 Rebased on top of latest master branch Cc: Nishanth Menon <nm(a)ti.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: Neha Francis <n-francis(a)ti.com> Cc: Manorit Chawdhry <m-chawdhry(a)ti.com> Cc: Vignesh Raghavendra <vigneshr(a)ti.com> Cc: Kamlesh Gurudasani <kamlesh(a)ti.com> Cc: Andrew Davis <afd(a)ti.com> Dhruva Gole (2): firmware: ti_sci: fix the secure_hdr in do_xfer firmware: ti_sci: Add comment explaining the is_secure code drivers/firmware/ti_sci.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) base-commit: d5c0c990c3128401810514c66b41b386096d206e prerequisite-patch-id: 2ed0c527b6ebf850744d9ff0eca0300a125f7796 -- 2.34.1

2 4

[RESEND PATCH v2] arm: mach-k3: j721s2_init: Support less than max DDR controllers
by Neha Malcom Francis 07 Feb '24

07 Feb '24

The number of DDR controllers to be initialised and used should depend on the device tree with the constraint of the maximum number of controllers the device supports. Since J721S2 has multiple (2) controllers, instead of hardcoding the number of probes, move to depending on the device tree UCLASS_RAM nodes present. Signed-off-by: Neha Malcom Francis <n-francis(a)ti.com> --- Changes since v1: https://lore.kernel.org/all/20240130074139.2627793-1-n-francis@ti.com/ - Moved away from using loop since J721S2 has only two controllers (Udit) Boot logs: https://gist.github.com/nehamalcom/740e3dcc1e94ca36250f0248d73f6b37 arch/arm/mach-k3/j721s2_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c index fb0708bae1..3374889558 100644 --- a/arch/arm/mach-k3/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2_init.c @@ -228,7 +228,7 @@ void k3_mem_init(void) panic("DRAM 0 init failed: %d\n", ret); ret = uclass_next_device_err(&dev); - if (ret) + if (ret && ret != -ENODEV) panic("DRAM 1 init failed: %d\n", ret); } spl_enable_cache(); -- 2.34.1

3 2

[PATCH v4] dma: ti: k3-udma: Use ring_idx to pair k3 nav rings
by MD Danish Anwar 07 Feb '24

07 Feb '24

Use ring_idx to pair rings. ring_idx will be same as tx flow_id for all non-negative flow_ids. For negative flow_ids, ring_idx will be tchan->id added with bchan_cnt. Signed-off-by: MD Danish Anwar <danishanwar(a)ti.com> --- Changes from v3 to v4: *) No functional change. Splitted the patch out of the series as suggested by Nishant. v3: https://lore.kernel.org/all/20240124064930.1787929-2-danishanwar@ti.com/ drivers/dma/ti/k3-udma.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 8a62d63dfe..eea9ec9659 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -876,13 +876,20 @@ static int udma_alloc_tx_resources(struct udma_chan *uc) { struct k3_nav_ring_cfg ring_cfg; struct udma_dev *ud = uc->ud; - int ret; + struct udma_tchan *tchan; + int ring_idx, ret; ret = udma_get_tchan(uc); if (ret) return ret; - ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, uc->tchan->id, -1, + tchan = uc->tchan; + if (tchan->tflow_id >= 0) + ring_idx = tchan->tflow_id; + else + ring_idx = ud->bchan_cnt + tchan->id; + + ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, ring_idx, -1, &uc->tchan->t_ring, &uc->tchan->tc_ring); if (ret) { -- 2.34.1

4 3

[PATCH 1/1] common: event: check event_type_name() argument
by Heinrich Schuchardt 07 Feb '24

07 Feb '24

In event_type_name() we should avoid possible buffer overruns by checking the type argument. Addresses-Coverity-ID: 478862 Out-of-bounds access Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- common/event.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/common/event.c b/common/event.c index dc61b9672f3..16c2ba6cc92 100644 --- a/common/event.c +++ b/common/event.c @@ -56,7 +56,10 @@ _Static_assert(ARRAY_SIZE(type_name) == EVT_COUNT, "event type_name size"); const char *event_type_name(enum event_t type) { #if CONFIG_IS_ENABLED(EVENT_DEBUG) - return type_name[type]; + if (type < ARRAY_SIZE(type_name)) + return type_name[type]; + else + return "(unknown)"; #else return "(unknown)"; #endif -- 2.43.0

2 1

[PATCH v1] arm: dts: nuvoton: modify npcm8xx reset property
by Jim Liu 07 Feb '24

07 Feb '24

Change reset method from generic to reset driver Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> --- arch/arm/dts/nuvoton-common-npcm8xx.dtsi | 2 + arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi | 71 ++++++++---------------- 2 files changed, 24 insertions(+), 49 deletions(-) diff --git a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi index 1694ef8849..db7517cc9b 100644 --- a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/reset/nuvoton,npcm8xx-reset.h> / { #address-cells = <2>; @@ -152,6 +153,7 @@ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_APB5>; clock-names = "clk_apb5"; + resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_PSPI2>; status = "disabled"; }; diff --git a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi index 4c6d5bed44..bc047d4b44 100644 --- a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi +++ b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi @@ -20,34 +20,7 @@ compatible = "nuvoton,npcm845-reset", "syscon", "simple-mfd"; reg = <0x0 0xf0801000 0x0 0xC4>; - rstc1: reset-controller1 { - compatible = "syscon-reset"; - #reset-cells = <1>; - regmap = <&rstc>; - offset = <NPCM8XX_RESET_IPSRST1>; - mask = <0xFFFFFFFF>; - }; - rstc2: reset-controller2 { - compatible = "syscon-reset"; - #reset-cells = <1>; - regmap = <&rstc>; - offset = <NPCM8XX_RESET_IPSRST2>; - mask = <0xFFFFFFFF>; - }; - rstc3: reset-controller3 { - compatible = "syscon-reset"; - #reset-cells = <1>; - regmap = <&rstc>; - offset = <NPCM8XX_RESET_IPSRST3>; - mask = <0xFFFFFFFF>; - }; - rstc4: reset-controller4 { - compatible = "syscon-reset"; - #reset-cells = <1>; - regmap = <&rstc>; - offset = <NPCM8XX_RESET_IPSRST4>; - mask = <0xFFFFFFFF>; - }; + #reset-cells = <2>; }; clk: clock-controller@f0801000 { @@ -70,7 +43,7 @@ clock-names = "stmmaceth"; pinctrl-names = "default"; pinctrl-0 = <&rg1mdio_pins>; - resets = <&rstc2 NPCM8XX_RESET_GMAC1>; + resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_GMAC1>; status = "disabled"; }; @@ -85,7 +58,7 @@ pinctrl-names = "default"; pinctrl-0 = <&rg2_pins &rg2mdio_pins>; - resets = <&rstc2 NPCM8XX_RESET_GMAC2>; + resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_GMAC2>; status = "disabled"; }; @@ -101,7 +74,7 @@ pinctrl-0 = <&r1_pins &r1err_pins &r1md_pins>; - resets = <&rstc1 NPCM8XX_RESET_GMAC3>; + resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_GMAC3>; status = "disabled"; }; @@ -117,7 +90,7 @@ pinctrl-0 = <&r2_pins &r2err_pins &r2md_pins>; - resets = <&rstc1 NPCM8XX_RESET_GMAC4>; + resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_GMAC4>; status = "disabled"; }; @@ -125,7 +98,7 @@ compatible = "nuvoton,npcm845-ehci"; reg = <0x0 0xf0828100 0x0 0x1000>; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstc2 NPCM8XX_RESET_USBH1>; + resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_USBH1>; status = "disabled"; }; @@ -133,21 +106,21 @@ compatible = "nuvoton,npcm845-ehci"; reg = <0x0 0xf082a100 0x0 0x1000>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstc4 NPCM8XX_RESET_USBH2>; + resets = <&rstc NPCM8XX_RESET_IPSRST4 NPCM8XX_RESET_USBH2>; status = "disabled"; }; ohci1: usb@f0829000 { compatible = "nuvoton,npcm845-ohci"; reg = <0x0 0xF0829000 0x0 0x1000>; - resets = <&rstc2 NPCM8XX_RESET_USBH1>; + resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_USBH1>; status = "disabled"; }; ohci2: usb@f082b000 { compatible = "nuvoton,npcm845-ohci"; reg = <0x0 0xF082B000 0x0 0x1000>; - resets = <&rstc4 NPCM8XX_RESET_USBH2>; + resets = <&rstc NPCM8XX_RESET_IPSRST4 NPCM8XX_RESET_USBH2>; status = "disabled"; }; @@ -160,21 +133,21 @@ compatible = "nuvoton,npcm845-usb-phy"; #phy-cells = <1>; reg = <1>; - resets = <&rstc3 NPCM8XX_RESET_USBPHY1>; + resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_USBPHY1>; status = "disabled"; }; usbphy2: usbphy@2 { compatible = "nuvoton,npcm845-usb-phy"; #phy-cells = <1>; reg = <2>; - resets = <&rstc3 NPCM8XX_RESET_USBPHY2>; + resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_USBPHY2>; status = "disabled"; }; usbphy3: usbphy@3 { compatible = "nuvoton,npcm845-usb-phy"; #phy-cells = <1>; reg = <3>; - resets = <&rstc4 NPCM8XX_RESET_USBPHY3>; + resets = <&rstc NPCM8XX_RESET_IPSRST4 NPCM8XX_RESET_USBPHY3>; status = "disabled"; }; }; @@ -186,7 +159,7 @@ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc3 NPCM8XX_RESET_UDC0>; + resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC0>; status = "disable"; }; @@ -197,7 +170,7 @@ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc1 NPCM8XX_RESET_UDC1>; + resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC1>; status = "disable"; }; @@ -208,7 +181,7 @@ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc1 NPCM8XX_RESET_UDC2>; + resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC2>; status = "disable"; }; @@ -219,7 +192,7 @@ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc1 NPCM8XX_RESET_UDC3>; + resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC3>; status = "disable"; }; @@ -230,7 +203,7 @@ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc1 NPCM8XX_RESET_UDC4>; + resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC4>; status = "disable"; }; @@ -241,7 +214,7 @@ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc1 NPCM8XX_RESET_UDC5>; + resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC5>; status = "disable"; }; @@ -252,7 +225,7 @@ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc1 NPCM8XX_RESET_UDC6>; + resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC6>; status = "disable"; }; @@ -263,7 +236,7 @@ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc3 NPCM8XX_RESET_UDC7>; + resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC7>; status = "disable"; }; @@ -274,7 +247,7 @@ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc3 NPCM8XX_RESET_UDC8>; + resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC8>; status = "disable"; }; @@ -285,7 +258,7 @@ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk NPCM8XX_CLK_SU>; clock-names = "clk_usb_bridge"; - resets = <&rstc3 NPCM8XX_RESET_UDC9>; + resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC9>; status = "disable"; }; -- 2.25.1

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[PATCH] scripts/gen_compile_commands: update to Linux v6.7
by Brandon Maier 07 Feb '24

07 Feb '24

Adds support for assembly files and updates the LINE_PATTERN so it supports both "cmd" and "savedcmd", which allows reverting the U-Boot modification in commit 97fbb2eb016b ("scripts/gen_compile_commands.py: adapt _LINE_PATTERN"). Upstream commits: - 880946158b011 gen_compile_commands.py: fix path resolve with symlinks in it - 9e56d3be4bfd2 gen_compile_commands: Sort output compile commands by file name - 52c15e7e79285 gen_compile_commands: Allow the line prefix to still be cmd_ - 1c67921444bf6 gen_compile_commands: add assembly files to compilation database Signed-off-by: Brandon Maier <brandon.maier(a)collins.com> Cc: Joao Marcos Costa <jmcosta944(a)gmail.com> --- scripts/gen_compile_commands.py | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/scripts/gen_compile_commands.py b/scripts/gen_compile_commands.py index cdca85e6b07..fec513e5547 100755 --- a/scripts/gen_compile_commands.py +++ b/scripts/gen_compile_commands.py @@ -21,7 +21,7 @@ _DEFAULT_OUTPUT = 'compile_commands.json' _DEFAULT_LOG_LEVEL = 'WARNING' _FILENAME_PATTERN = r'^\..*\.cmd$' -_LINE_PATTERN = r'^cmd_[^ ]*\.o := (.* )([^ ]*\.c) *(;|$)' +_LINE_PATTERN = r'^(saved)?cmd_[^ ]*\.o := (?P<command_prefix>.* )(?P<file_path>[^ ]*\.[cS]) *(;|$)' _VALID_LOG_LEVELS = ['DEBUG', 'INFO', 'WARNING', 'ERROR', 'CRITICAL'] # The tools/ directory adopts a different build system, and produces .cmd # files in a different format. Do not support it. @@ -66,7 +66,7 @@ def parse_arguments(): args = parser.parse_args() return (args.log_level, - os.path.abspath(args.directory), + os.path.realpath(args.directory), args.output, args.ar, args.paths if len(args.paths) > 0 else [args.directory]) @@ -174,8 +174,8 @@ def process_line(root_directory, command_prefix, file_path): # by Make, so this code replaces the escaped version with '#'. prefix = command_prefix.replace('\#', '#').replace('$(pound)', '#') - # Use os.path.abspath() to normalize the path resolving '.' and '..' . - abs_path = os.path.abspath(os.path.join(root_directory, file_path)) + # Return the canonical path, eliminating any symbolic links encountered in the path. + abs_path = os.path.realpath(os.path.join(root_directory, file_path)) if not os.path.exists(abs_path): raise ValueError('File %s not found' % abs_path) return { @@ -215,15 +215,15 @@ def main(): result = line_matcher.match(f.readline()) if result: try: - entry = process_line(directory, result.group(1), - result.group(2)) + entry = process_line(directory, result.group('command_prefix'), + result.group('file_path')) compile_commands.append(entry) except ValueError as err: logging.info('Could not add line from %s: %s', cmdfile, err) with open(output, 'wt') as f: - json.dump(compile_commands, f, indent=2, sort_keys=True) + json.dump(sorted(compile_commands, key=lambda x: x["file"]), f, indent=2, sort_keys=True) if __name__ == '__main__': -- 2.43.0

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Pull request: u-boot-rockchip-20240207
by Kever Yang 07 Feb '24

07 Feb '24

Hi Tom, Please pull the updates for rockchip platform: - Add board: rv1126 Sonoff iHost board - rv1126 ddr4 support; - Enable BOOTSTD_FULL for RK3399 and RK3588; - rk3036 spl stack addr fix; - dts sync from linux v6.8-rc1 for rk356x, rk3588, rv1126; - Enable eMMC HS200 mode by default for rk3568 and rk3588; CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/19556 Thanks, - Kever The following changes since commit 819abd0a1eaff9a921f5b917e152b85dab302e33: Merge tag 'smbios-2024-04-rc2' of https://source.denx.de/u-boot/custodians/u-boot-efi (2024-02-03 09:11:25 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-rockchip.git tags/u-boot-rockchip-20240207 for you to fetch changes up to b8f1f60c23c9b3edb70159c4e2b1be232a008ee3: arm: dts: rockpro64: Add RockPro64 smbios (2024-02-07 10:49:13 +0800) ---------------------------------------------------------------- Andy Yan (1): rockchip: rk3588-evb: Enable USB support Jonas Karlman (15): net: designware: Reset eth phy before phy connect rockchip: rk3328-rock-pi-e: Enable DM_ETH_PHY and PHY_REALTEK rockchip: rk356x: Sync device tree from linux v6.7 rockchip: rk356x: Sync device tree from linux v6.8-rc1 rockchip: rk356x: Move common uart2 props to rk356x-u-boot.dtsi rockchip: rk3588: Sync device tree with linux v6.7 rockchip: rk3588: Sync device tree from linux v6.8-rc1 rockchip: rk3588: Add default u-boot,spl-boot-order prop rockchip: rk35xx: Remove unnecessary status props rockchip: rk3588: Enable eMMC HS200 mode rockchip: rk3588-quartzpro64: Enable AHCI, PCI and USB rockchip: rk35xx: Remove use of eMMC DDR52 mode rockchip: rk35xx: Enable eMMC HS200 mode by default mmc: rockchip_sdhci: Fix HS400 mode write on RK3568 rockchip: rk3568-generic: Enable eMMC HS200 mode Kever Yang (2): spl: Make SPL_STACK available for ROCKCHIP_RK3036 without spl framework configs: rockchip: rk3036: Fix CONFIG_SPL_STACK define Shantur Rathore (2): arch: arm: mach-rockchip: Kconfig: Enable BOOTSTD_FULL for RK3399 and RK3588 arm: dts: rockpro64: Add RockPro64 smbios Tim Lunn (6): arm: dts: rockchip: Sync rv1126 dts from linux 6.8-rc1 ram: rockchip: Add rv1126 ddr4 support rockchip: Convert rv1126 to standard boot board: rockchip: Add Sonoff iHost board rockchip: rv1126: select SPL_OPTEE_IMAGE rockchip: rv1126: Move RAM disk address YouMin Chen (1): rockchip: sdram: fix LPDDR5 bank info for sys_reg version 3 arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 22 ++ arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 7 - arch/arm/dts/rk3566-anbernic-rgxx3.dtsi | 42 ++- arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 13 - arch/arm/dts/rk3566-quartz64-a.dts | 7 +- arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi | 13 - arch/arm/dts/rk3566-quartz64-b.dts | 2 - arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 13 - arch/arm/dts/rk3566-radxa-cm3-io.dts | 5 +- arch/arm/dts/rk3566-soquartz-blade.dts | 4 + arch/arm/dts/rk3566-soquartz-cm4.dts | 4 + arch/arm/dts/rk3566-soquartz-model-a.dts | 4 + arch/arm/dts/rk3566-soquartz-u-boot.dtsi | 13 - arch/arm/dts/rk3566-soquartz.dtsi | 4 - arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi | 13 - arch/arm/dts/rk3568-evb-u-boot.dtsi | 17 - arch/arm/dts/rk3568-evb.dts | 3 - arch/arm/dts/rk3568-generic-u-boot.dtsi | 11 - arch/arm/dts/rk3568-generic.dts | 12 +- arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi | 13 - arch/arm/dts/rk3568-lubancat-2.dts | 3 - arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 13 - arch/arm/dts/rk3568-nanopi-r5s.dtsi | 3 - arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi | 13 - arch/arm/dts/rk3568-odroid-m1.dts | 3 - arch/arm/dts/rk3568-radxa-cm3i.dtsi | 3 - arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 13 - arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 13 - arch/arm/dts/rk3568-rock-3a.dts | 7 +- arch/arm/dts/rk356x-u-boot.dtsi | 12 +- arch/arm/dts/rk356x.dtsi | 20 +- arch/arm/dts/rk3588-edgeble-neu6a-io.dts | 4 - arch/arm/dts/rk3588-edgeble-neu6b-io.dts | 6 +- arch/arm/dts/rk3588-evb1-v10.dts | 99 ++++- arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi | 6 - arch/arm/dts/rk3588-nanopc-t6.dts | 10 +- arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi | 6 - arch/arm/dts/rk3588-orangepi-5-plus.dts | 1 - arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi | 6 - arch/arm/dts/rk3588-quartzpro64.dts | 2 +- arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 13 - arch/arm/dts/rk3588-rock-5b.dts | 13 +- arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi | 8 - arch/arm/dts/rk3588-turing-rk1.dtsi | 6 +- arch/arm/dts/rk3588-u-boot.dtsi | 2 +- arch/arm/dts/rk3588s-orangepi-5.dts | 9 +- arch/arm/dts/rk3588s-pinctrl.dtsi | 2 +- arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi | 7 - arch/arm/dts/rk3588s-rock-5a.dts | 10 +- arch/arm/dts/rk3588s-u-boot.dtsi | 49 +-- arch/arm/dts/rk3588s.dtsi | 152 ++++++++ arch/arm/dts/rv1126-edgeble-neu2-io.dts | 70 ++++ arch/arm/dts/rv1126-edgeble-neu2.dtsi | 27 +- arch/arm/dts/rv1126-pinctrl.dtsi | 130 +++++++ arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi | 13 + arch/arm/dts/rv1126-sonoff-ihost.dts | 29 ++ arch/arm/dts/rv1126-sonoff-ihost.dtsi | 404 +++++++++++++++++++++ arch/arm/dts/rv1126.dtsi | 185 ++++++++++ arch/arm/mach-rockchip/Kconfig | 7 + arch/arm/mach-rockchip/rk3588/syscon_rk3588.c | 2 +- arch/arm/mach-rockchip/rv1126/Kconfig | 8 + arch/arm/mach-rockchip/sdram.c | 9 +- board/itead/sonoff-ihost/Kconfig | 16 + board/itead/sonoff-ihost/MAINTAINERS | 6 + common/spl/Kconfig | 3 +- configs/evb-rk3036_defconfig | 1 + configs/evb-rk3588_defconfig | 14 + configs/generic-rk3568_defconfig | 5 +- configs/kylin-rk3036_defconfig | 1 + configs/nanopc-t6-rk3588_defconfig | 2 + configs/nanopi-r5c-rk3568_defconfig | 2 - configs/nanopi-r5s-rk3568_defconfig | 2 - configs/neu6a-io-rk3588_defconfig | 2 + configs/neu6b-io-rk3588_defconfig | 2 + configs/orangepi-5-plus-rk3588_defconfig | 2 + configs/quartzpro64-rk3588_defconfig | 27 ++ configs/radxa-e25-rk3568_defconfig | 2 - configs/rock-pi-e-rk3328_defconfig | 2 + configs/rock5a-rk3588s_defconfig | 2 + configs/rock5b-rk3588_defconfig | 2 + configs/rockpro64-rk3399_defconfig | 2 + configs/sonoff-ihost-rv1126_defconfig | 60 +++ configs/turing-rk1-rk3588_defconfig | 2 + doc/board/rockchip/rockchip.rst | 1 + drivers/mmc/rockchip_sdhci.c | 9 +- drivers/net/designware.c | 7 + .../ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc | 75 ++++ .../ram/rockchip/sdram-rv1126-ddr4-detect-328.inc | 75 ++++ .../ram/rockchip/sdram-rv1126-ddr4-detect-396.inc | 75 ++++ .../ram/rockchip/sdram-rv1126-ddr4-detect-528.inc | 75 ++++ .../ram/rockchip/sdram-rv1126-ddr4-detect-664.inc | 75 ++++ .../ram/rockchip/sdram-rv1126-ddr4-detect-784.inc | 75 ++++ .../ram/rockchip/sdram-rv1126-ddr4-detect-924.inc | 75 ++++ drivers/ram/rockchip/sdram_rv1126.c | 8 + include/configs/neural-compute-module-2.h | 6 - include/configs/rv1126_common.h | 5 +- include/configs/sonoff-ihost.h | 10 + include/dt-bindings/clock/rk3568-cru.h | 1 + include/dt-bindings/soc/rockchip,vop2.h | 4 + 100 files changed, 1984 insertions(+), 370 deletions(-) create mode 100644 arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi create mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dts create mode 100644 arch/arm/dts/rv1126-sonoff-ihost.dtsi create mode 100644 board/itead/sonoff-ihost/Kconfig create mode 100644 board/itead/sonoff-ihost/MAINTAINERS create mode 100644 configs/sonoff-ihost-rv1126_defconfig create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-1056.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-328.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-396.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-528.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-664.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-784.inc create mode 100644 drivers/ram/rockchip/sdram-rv1126-ddr4-detect-924.inc create mode 100644 include/configs/sonoff-ihost.h

2 1

[PATCH 00/10] Add AVS support for J721S2
by Manorit Chawdhry 07 Feb '24

07 Feb '24

This series does the DT sync with Linux 6.8-rc1 as that has the pmic nodes required for AVS support and then adds AVS Support for J721S2. AVS Test for J721S2: https://gist.github.com/manorit2001/d7690ded6ef685aa8ffa5b16746cc529 Boot Test results: https://gist.github.com/manorit2001/6775d721b3df5a690497d94d012b93c4 Signed-off-by: Manorit Chawdhry <m-chawdhry(a)ti.com> --- Manorit Chawdhry (10): arm: dts: k3-j721s2*: Sync with 6.8-rc1 arm: dts: k3-am68*: Sync with 6.8-rc1 drivers: misc: k3_avs: Use soc_match_device instead of compatible. drivers: misc: k3_avs: Check return code while programming AVS drivers: misc: k3_avs: Add AVS Support for J721S2. drivers: power: pmic: Fix compatible for J721S2 arm: mach-k3: j721s2_init: Initialize AVS Class 0 arm: dts: j721s2: Add VTM node in R5 DONOTMERGE: arm: dts: j721s2: Fix Power domain for VTM node. configs: j721s2_evm_r5_defconfig: Add AVS Configs arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi | 18 +- arch/arm/dts/k3-am68-sk-base-board.dts | 1 + .../dts/k3-j721s2-common-proc-board-u-boot.dtsi | 18 +- arch/arm/dts/k3-j721s2-main.dtsi | 9 +- arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi | 23 ++- arch/arm/dts/k3-j721s2-r5-common-proc-board.dts | 9 + arch/arm/dts/k3-j721s2-som-p0.dtsi | 193 ++++++++++++++++++ arch/arm/mach-k3/j721s2_init.c | 8 + configs/j721s2_evm_r5_defconfig | 6 + drivers/misc/k3_avs.c | 216 ++++++++++++--------- drivers/power/pmic/tps65941.c | 2 +- 11 files changed, 385 insertions(+), 118 deletions(-) --- base-commit: 6faba41927bdc8973b59678649ef83c564cc421e change-id: 20240130-b4-upstream-j721s2-avs-8c187d3fe26a Best regards, -- Manorit Chawdhry <m-chawdhry(a)ti.com>

4 17

[PATCH v3] common: usb-hub: Reset hub port before scanning
by Shantur Rathore 07 Feb '24

07 Feb '24

Currently when a hub is turned on, all the ports are powered on. This works well for hubs which have individual power control. For the hubs without individual power control this has no effect. Mostly in these scenarios the hub port is powered before the USB controller is enabled, this can lead to some devices in unexpected state. With this patch, we explicitly reset the port while powering up hub This resets the port for hubs without port power control and has no effect on hubs with port power control as the port is still off. Before this patch AMicro AM8180 based NVME to USB adapter won't be detected as a USB3.0 Mass Storage device but with this it works as expected. Tested working after this patch: 1. AMicro AM8180 based NVME to USB Adapter 2. Kingston DataTraveler 3.0 3. GenesysLogic USB3.0 Hub The drives were tested while connected directly and via the hub. Signed-off-by: Shantur Rathore <i(a)shantur.com> --- Changes in v3: - Split up patches as seperate series Changes in v2: - As requested, added fix for regulator-always-on in RockPro64 common/usb_hub.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/common/usb_hub.c b/common/usb_hub.c index 70279f301d..3fb7e14d10 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -174,8 +174,10 @@ static void usb_hub_power_on(struct usb_hub_device *hub) debug("enabling power on all ports\n"); for (i = 0; i < dev->maxchild; i++) { + usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_RESET); + debug("Reset : port %d returns %lX\n", i + 1, dev->status); usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER); - debug("port %d returns %lX\n", i + 1, dev->status); + debug("PowerOn : port %d returns %lX\n", i + 1, dev->status); } #ifdef CONFIG_SANDBOX -- 2.40.1

5 20

[PATCH] arm: mach-k3: Refactor QoS settings
by Aradhya Bhatia 07 Feb '24

07 Feb '24

Refactor common QoS code into a new common header file, and the soc specific setup_qos functions into a common API. Rename $(soc)_qos_count and $(soc)_qos_data variables to qos_count and qos_data. When QoS settings of more SoCs are added, only one pair will be defined at a time, based on the config SOC_K3_$(soc). This refactoring has been done for 2 major purposes. - The auto-generated $(soc)_qos_data.c and $(soc)_qos.h files cannot have any code that is specific to any bootloader. Those files have to remain agnostic of different bootloader implementations and their header files. - The existing implementation was less than ideal and would have enabled multiple $(soc)_qos_count and $(soc)_qos_data variables for all SoC variants. Signed-off-by: Aradhya Bhatia <a-bhatia1(a)ti.com> --- arch/arm/mach-k3/Kconfig | 8 +++++++ arch/arm/mach-k3/am62a7_init.c | 14 ------------ arch/arm/mach-k3/common.c | 12 ++++++++++ arch/arm/mach-k3/common.h | 8 +++++++ arch/arm/mach-k3/include/mach/hardware.h | 9 -------- arch/arm/mach-k3/include/mach/k3-qos.h | 22 +++++++++++++++++++ arch/arm/mach-k3/r5/am62ax/Makefile | 2 +- .../{include/mach => r5/am62ax}/am62a_qos.h | 0 .../{am62a_qos_data.c => am62a_qos_uboot.c} | 9 ++++---- 9 files changed, 56 insertions(+), 28 deletions(-) create mode 100644 arch/arm/mach-k3/include/mach/k3-qos.h rename arch/arm/mach-k3/{include/mach => r5/am62ax}/am62a_qos.h (100%) rename arch/arm/mach-k3/r5/am62ax/{am62a_qos_data.c => am62a_qos_uboot.c} (85%) diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 03898424c954..ffc4a9c29029 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -139,6 +139,14 @@ config K3_DM_FW bootloader, it makes RM and PM services not being available during R5 SPL execution time. +config K3_QOS + bool "Enable Quality of Service (QoS) Settings for TI K3 SoCs" + default y if CPU_V7R && SOC_K3_AM62A7 + help + This option enables the R5 SPL to apply QoS settings for various + HW controllers inside the TI K3 SoCs. The files for QoS settings are + generated from Sysconfig and k3-resource-partitioning tools. + config K3_X509_SWRV int "SWRV for X509 certificate used for boot images" default 1 diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c index d72e19936b9b..080274e3af58 100644 --- a/arch/arm/mach-k3/am62a7_init.c +++ b/arch/arm/mach-k3/am62a7_init.c @@ -69,20 +69,6 @@ static void ctrl_mmr_unlock(void) mmr_unlock(PADCFG_MMR1_BASE, 1); } -#if (IS_ENABLED(CONFIG_CPU_V7R)) -static void setup_qos(void) -{ - u32 i; - - for (i = 0; i < am62a_qos_count; i++) - writel(am62a_qos_data[i].val, (uintptr_t)am62a_qos_data[i].reg); -} -#else -static void setup_qos(void) -{ -} -#endif - void board_init_f(ulong dummy) { struct udevice *dev; diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index f411366778f0..b54f2ddc4729 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -28,6 +28,8 @@ #include <elf.h> #include <soc.h> +#include <asm/arch/k3-qos.h> + #if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF) enum { IMAGE_ID_ATF, @@ -595,3 +597,13 @@ int misc_init_r(void) void __weak do_board_detect(void) { } + +#if (IS_ENABLED(CONFIG_K3_QOS)) +void setup_qos(void) +{ + u32 i; + + for (i = 0; i < qos_count; i++) + writel(qos_data[i].val, (uintptr_t)qos_data[i].reg); +} +#endif diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index e9db9fbfb63d..53aa186b31a4 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -45,3 +45,11 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size); struct ti_sci_handle *get_ti_sci_handle(void); void do_board_detect(void); void ti_secure_image_check_binary(void **p_image, size_t *p_size); + +#if (IS_ENABLED(CONFIG_K3_QOS)) +void setup_qos(void); +#else +static inline void setup_qos(void) +{ +} +#endif diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index a1a9dfbde66c..52ef82e70b07 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -30,7 +30,6 @@ #ifdef CONFIG_SOC_K3_AM62A7 #include "am62a_hardware.h" -#include "am62a_qos.h" #endif /* Assuming these addresses and definitions stay common across K3 devices */ @@ -97,12 +96,4 @@ struct rom_extended_boot_data { u32 num_components; }; -struct k3_qos_data { - u32 reg; - u32 val; -}; - -extern struct k3_qos_data am62a_qos_data[]; -extern u32 am62a_qos_count; - #endif /* _ASM_ARCH_HARDWARE_H_ */ diff --git a/arch/arm/mach-k3/include/mach/k3-qos.h b/arch/arm/mach-k3/include/mach/k3-qos.h new file mode 100644 index 000000000000..e00e1de5b9cb --- /dev/null +++ b/arch/arm/mach-k3/include/mach/k3-qos.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Quality of Service (QoS) Configuration Header File + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ +#ifndef _K3_QOS_H_ +#define _K3_QOS_H_ + +#include <linux/kernel.h> + +struct k3_qos_data { + u32 reg; + u32 val; +}; + +#if (IS_ENABLED(CONFIG_K3_QOS)) +extern struct k3_qos_data qos_data[]; +extern u32 qos_count; +#endif + +#endif /* _K3_QOS_H_ */ diff --git a/arch/arm/mach-k3/r5/am62ax/Makefile b/arch/arm/mach-k3/r5/am62ax/Makefile index 02a941805e9a..e4e55ce5c7dd 100644 --- a/arch/arm/mach-k3/r5/am62ax/Makefile +++ b/arch/arm/mach-k3/r5/am62ax/Makefile @@ -4,4 +4,4 @@ obj-y += clk-data.o obj-y += dev-data.o -obj-y += am62a_qos_data.o +obj-y += am62a_qos_uboot.o diff --git a/arch/arm/mach-k3/include/mach/am62a_qos.h b/arch/arm/mach-k3/r5/am62ax/am62a_qos.h similarity index 100% rename from arch/arm/mach-k3/include/mach/am62a_qos.h rename to arch/arm/mach-k3/r5/am62ax/am62a_qos.h diff --git a/arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c b/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c similarity index 85% rename from arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c rename to arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c index 38db4f2f5c8e..9a82944d5fe9 100644 --- a/arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c +++ b/arch/arm/mach-k3/r5/am62ax/am62a_qos_uboot.c @@ -5,10 +5,11 @@ * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ */ -#include <asm/arch/hardware.h> -#include "common.h" -struct k3_qos_data am62a_qos_data[] = { +#include <asm/arch/k3-qos.h> +#include "am62a_qos.h" + +struct k3_qos_data qos_data[] = { /* modules_qosConfig0 - 1 endpoints, 4 channels */ { .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0, @@ -43,4 +44,4 @@ struct k3_qos_data am62a_qos_data[] = { }, }; -uint32_t am62a_qos_count = sizeof(am62a_qos_data) / sizeof(am62a_qos_data[0]); +u32 qos_count = ARRAY_SIZE(qos_data); base-commit: daa3100250839dd30626f7f4b7daf041f1114f1c -- 2.34.1

2 2