February 2024 - U-Boot

[PATCH 1/3] ARM: renesas: Disable EFI on R-Car Gen2
by Marek Vasut 12 Feb '24

12 Feb '24

These systems are unlikely to use EFI as this functionality has not been enabled until it got pulled in by Kconfig default. This functionality does add some 60-70 kiB to the u-boot.img size, which overflows the size limit. Disable it. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- Cc: Niklas Söderlund <niklas.soderlund+renesas(a)ragnatech.se> Cc: Paul Barker <paul.barker.ct(a)bp.renesas.com> --- configs/alt_defconfig | 2 ++ configs/blanche_defconfig | 2 ++ configs/gose_defconfig | 2 ++ configs/koelsch_defconfig | 2 ++ configs/lager_defconfig | 2 ++ configs/porter_defconfig | 2 ++ configs/silk_defconfig | 2 ++ configs/stout_defconfig | 2 ++ 8 files changed, 16 insertions(+) diff --git a/configs/alt_defconfig b/configs/alt_defconfig index 31f38bd3a5b..35707a65960 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -68,6 +68,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" +CONFIG_PARTITION_UUIDS=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -106,3 +107,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig index 59e9b3af846..f328af84dfa 100644 --- a/configs/blanche_defconfig +++ b/configs/blanche_defconfig @@ -44,6 +44,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_PARTITION_UUIDS=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y @@ -82,3 +83,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/gose_defconfig b/configs/gose_defconfig index 4220b9349b7..92bb5911765 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -68,6 +68,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" +CONFIG_PARTITION_UUIDS=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -104,3 +105,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index d39533cc393..8d9c3b94499 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -68,6 +68,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" +CONFIG_PARTITION_UUIDS=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -104,3 +105,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/lager_defconfig b/configs/lager_defconfig index da2ba58c6b0..d00314c60e4 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -68,6 +68,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" +CONFIG_PARTITION_UUIDS=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -106,3 +107,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/porter_defconfig b/configs/porter_defconfig index 0a805deff65..a343c8e83de 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -68,6 +68,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" +CONFIG_PARTITION_UUIDS=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -104,3 +105,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/silk_defconfig b/configs/silk_defconfig index 7c6b5b59c93..5f08ae0fcf9 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -68,6 +68,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" +CONFIG_PARTITION_UUIDS=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -106,3 +107,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/stout_defconfig b/configs/stout_defconfig index 8fad272cf55..0375630adea 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -68,6 +68,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k(u-boot-env2),768k(u-boot),-(user)" +CONFIG_PARTITION_UUIDS=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -105,3 +106,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_EFI_LOADER is not set -- 2.43.0

2 5

[PATCH v2] armv8: crypto: SHA-512 using ARMv8 Crypto Extensions
by Igor Opaniuk 12 Feb '24

12 Feb '24

From: Igor Opaniuk <igor.opaniuk(a)gmail.com> Add support for the SHA-512 Secure Hash Algorithm which uses ARMv8 Crypto Extensions. The CPU should support ARMv8.2 instruction set and implement SHA512H, SHA512H2, SHA512SU0, and SHA512SU1 instructions. This information can be obtained from ID_AA64ISAR0_EL1 (AArch64 Instruction Set Attribute Register 0), bits [15:12] should be 0b0010 [1], that indicates support for SHA512* instructions in AArch64 state. As not all ARMv8-base SoCs support that, ARMV8_CE_SHA512 is left disabled by default for now. Validated in QEMU for ARMv8 with compiled-in SHA-2 support (because of absence of hw with ARMv8.2-A ready SoC at hand): => hash sha512 0x40200000 0x2000000 sha512 for 40200000 ... 421fffff ==> 1aeae269f4eb7c37... The implementation is based on original implementation from Ard Biesheuvel in Linux kernel [2] [1] https://developer.arm.com/documentation/ddi0601/2023-12/AArch64-Registers/I… [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arc… CC: Ard Biesheuvel <ardb(a)kernel.org>> CC: Loic Poulain <loic.poulain(a)linaro.org> Signed-off-by: Igor Opaniuk <igor.opaniuk(a)gmail.com> --- Changes in v2: - Dropped "Default n" in Kconfig as Michal Simek suggested - Adjusted commit message about QEMU validation arch/arm/cpu/armv8/Kconfig | 4 + arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/sha512_ce_core.S | 210 ++++++++++++++++++++++++++++ arch/arm/cpu/armv8/sha512_ce_glue.c | 20 +++ lib/sha512.c | 6 +- 5 files changed, 239 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv8/sha512_ce_core.S create mode 100644 arch/arm/cpu/armv8/sha512_ce_glue.c diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 9f0fb369f7..37b8b60914 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -204,6 +204,10 @@ config ARMV8_CE_SHA256 bool "SHA-256 digest algorithm (ARMv8 Crypto Extensions)" default y if SHA256 +config ARMV8_CE_SHA512 + bool "SHA-512 digest algorithm (ARMv8 Crypto Extensions)" + depends on SHA512 + endif endif diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index bba4f570db..3894f2bb2a 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -45,3 +45,4 @@ obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/ obj-$(CONFIG_XEN) += xen/ obj-$(CONFIG_ARMV8_CE_SHA1) += sha1_ce_glue.o sha1_ce_core.o obj-$(CONFIG_ARMV8_CE_SHA256) += sha256_ce_glue.o sha256_ce_core.o +obj-$(CONFIG_ARMV8_CE_SHA512) += sha512_ce_glue.o sha512_ce_core.o \ No newline at end of file diff --git a/arch/arm/cpu/armv8/sha512_ce_core.S b/arch/arm/cpu/armv8/sha512_ce_core.S new file mode 100644 index 0000000000..906291f35b --- /dev/null +++ b/arch/arm/cpu/armv8/sha512_ce_core.S @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto + * Extensions + * + * Copyright (C) 2018 Linaro Ltd <ard.biesheuvel(a)linaro.org> + * Copyright (C) 2024 Igor Opaniuk <igor.opaniuk(a)gmail.com> + */ + + #include <config.h> + #include <linux/linkage.h> + #include <asm/system.h> + #include <asm/macro.h> + + .macro adr_l, dst, sym + adrp \dst, \sym + add \dst, \dst, :lo12:\sym + .endm + + .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19 + .set .Lq\b, \b + .set .Lv\b\().2d, \b + .endr + + .macro sha512h, rd, rn, rm + .inst 0xce608000 | .L\rd | (.L\rn << 5) | (.L\rm << 16) + .endm + + .macro sha512h2, rd, rn, rm + .inst 0xce608400 | .L\rd | (.L\rn << 5) | (.L\rm << 16) + .endm + + .macro sha512su0, rd, rn + .inst 0xcec08000 | .L\rd | (.L\rn << 5) + .endm + + .macro sha512su1, rd, rn, rm + .inst 0xce608800 | .L\rd | (.L\rn << 5) | (.L\rm << 16) + .endm + + /* + * The SHA-512 round constants + */ + .section ".rodata", "a" + .align 4 +.Lsha512_rcon: + .quad 0x428a2f98d728ae22, 0x7137449123ef65cd + .quad 0xb5c0fbcfec4d3b2f, 0xe9b5dba58189dbbc + .quad 0x3956c25bf348b538, 0x59f111f1b605d019 + .quad 0x923f82a4af194f9b, 0xab1c5ed5da6d8118 + .quad 0xd807aa98a3030242, 0x12835b0145706fbe + .quad 0x243185be4ee4b28c, 0x550c7dc3d5ffb4e2 + .quad 0x72be5d74f27b896f, 0x80deb1fe3b1696b1 + .quad 0x9bdc06a725c71235, 0xc19bf174cf692694 + .quad 0xe49b69c19ef14ad2, 0xefbe4786384f25e3 + .quad 0x0fc19dc68b8cd5b5, 0x240ca1cc77ac9c65 + .quad 0x2de92c6f592b0275, 0x4a7484aa6ea6e483 + .quad 0x5cb0a9dcbd41fbd4, 0x76f988da831153b5 + .quad 0x983e5152ee66dfab, 0xa831c66d2db43210 + .quad 0xb00327c898fb213f, 0xbf597fc7beef0ee4 + .quad 0xc6e00bf33da88fc2, 0xd5a79147930aa725 + .quad 0x06ca6351e003826f, 0x142929670a0e6e70 + .quad 0x27b70a8546d22ffc, 0x2e1b21385c26c926 + .quad 0x4d2c6dfc5ac42aed, 0x53380d139d95b3df + .quad 0x650a73548baf63de, 0x766a0abb3c77b2a8 + .quad 0x81c2c92e47edaee6, 0x92722c851482353b + .quad 0xa2bfe8a14cf10364, 0xa81a664bbc423001 + .quad 0xc24b8b70d0f89791, 0xc76c51a30654be30 + .quad 0xd192e819d6ef5218, 0xd69906245565a910 + .quad 0xf40e35855771202a, 0x106aa07032bbd1b8 + .quad 0x19a4c116b8d2d0c8, 0x1e376c085141ab53 + .quad 0x2748774cdf8eeb99, 0x34b0bcb5e19b48a8 + .quad 0x391c0cb3c5c95a63, 0x4ed8aa4ae3418acb + .quad 0x5b9cca4f7763e373, 0x682e6ff3d6b2b8a3 + .quad 0x748f82ee5defb2fc, 0x78a5636f43172f60 + .quad 0x84c87814a1f0ab72, 0x8cc702081a6439ec + .quad 0x90befffa23631e28, 0xa4506cebde82bde9 + .quad 0xbef9a3f7b2c67915, 0xc67178f2e372532b + .quad 0xca273eceea26619c, 0xd186b8c721c0c207 + .quad 0xeada7dd6cde0eb1e, 0xf57d4f7fee6ed178 + .quad 0x06f067aa72176fba, 0x0a637dc5a2c898a6 + .quad 0x113f9804bef90dae, 0x1b710b35131c471b + .quad 0x28db77f523047d84, 0x32caab7b40c72493 + .quad 0x3c9ebe0a15c9bebc, 0x431d67c49c100d4c + .quad 0x4cc5d4becb3e42b6, 0x597f299cfc657e2a + .quad 0x5fcb6fab3ad6faec, 0x6c44198c4a475817 + + .macro dround, i0, i1, i2, i3, i4, rc0, rc1, in0, in1, in2, in3, in4 + .ifnb \rc1 + ld1 {v\rc1\().2d}, [x4], #16 + .endif + add v5.2d, v\rc0\().2d, v\in0\().2d + ext v6.16b, v\i2\().16b, v\i3\().16b, #8 + ext v5.16b, v5.16b, v5.16b, #8 + ext v7.16b, v\i1\().16b, v\i2\().16b, #8 + add v\i3\().2d, v\i3\().2d, v5.2d + .ifnb \in1 + ext v5.16b, v\in3\().16b, v\in4\().16b, #8 + sha512su0 v\in0\().2d, v\in1\().2d + .endif + sha512h q\i3, q6, v7.2d + .ifnb \in1 + sha512su1 v\in0\().2d, v\in2\().2d, v5.2d + .endif + add v\i4\().2d, v\i1\().2d, v\i3\().2d + sha512h2 q\i3, q\i1, v\i0\().2d + .endm + + /* + * void sha512_ce_transform(struct sha512_state *sst, u8 const *src, + * int blocks) + */ + .text +ENTRY(sha512_ce_transform) + /* load state */ + ld1 {v8.2d-v11.2d}, [x0] + + /* load first 4 round constants */ + adr_l x3, .Lsha512_rcon + ld1 {v20.2d-v23.2d}, [x3], #64 + + /* load input */ +0: ld1 {v12.2d-v15.2d}, [x1], #64 + ld1 {v16.2d-v19.2d}, [x1], #64 + sub w2, w2, #1 +#if __BYTE_ORDER == __LITTLE_ENDIAN + rev64 v12.16b, v12.16b + rev64 v13.16b, v13.16b + rev64 v14.16b, v14.16b + rev64 v15.16b, v15.16b + rev64 v16.16b, v16.16b + rev64 v17.16b, v17.16b + rev64 v18.16b, v18.16b + rev64 v19.16b, v19.16b +#endif + mov x4, x3 // rc pointer + + mov v0.16b, v8.16b + mov v1.16b, v9.16b + mov v2.16b, v10.16b + mov v3.16b, v11.16b + + // v0 ab cd -- ef gh ab + // v1 cd -- ef gh ab cd + // v2 ef gh ab cd -- ef + // v3 gh ab cd -- ef gh + // v4 -- ef gh ab cd -- + + dround 0, 1, 2, 3, 4, 20, 24, 12, 13, 19, 16, 17 + dround 3, 0, 4, 2, 1, 21, 25, 13, 14, 12, 17, 18 + dround 2, 3, 1, 4, 0, 22, 26, 14, 15, 13, 18, 19 + dround 4, 2, 0, 1, 3, 23, 27, 15, 16, 14, 19, 12 + dround 1, 4, 3, 0, 2, 24, 28, 16, 17, 15, 12, 13 + + dround 0, 1, 2, 3, 4, 25, 29, 17, 18, 16, 13, 14 + dround 3, 0, 4, 2, 1, 26, 30, 18, 19, 17, 14, 15 + dround 2, 3, 1, 4, 0, 27, 31, 19, 12, 18, 15, 16 + dround 4, 2, 0, 1, 3, 28, 24, 12, 13, 19, 16, 17 + dround 1, 4, 3, 0, 2, 29, 25, 13, 14, 12, 17, 18 + + dround 0, 1, 2, 3, 4, 30, 26, 14, 15, 13, 18, 19 + dround 3, 0, 4, 2, 1, 31, 27, 15, 16, 14, 19, 12 + dround 2, 3, 1, 4, 0, 24, 28, 16, 17, 15, 12, 13 + dround 4, 2, 0, 1, 3, 25, 29, 17, 18, 16, 13, 14 + dround 1, 4, 3, 0, 2, 26, 30, 18, 19, 17, 14, 15 + + dround 0, 1, 2, 3, 4, 27, 31, 19, 12, 18, 15, 16 + dround 3, 0, 4, 2, 1, 28, 24, 12, 13, 19, 16, 17 + dround 2, 3, 1, 4, 0, 29, 25, 13, 14, 12, 17, 18 + dround 4, 2, 0, 1, 3, 30, 26, 14, 15, 13, 18, 19 + dround 1, 4, 3, 0, 2, 31, 27, 15, 16, 14, 19, 12 + + dround 0, 1, 2, 3, 4, 24, 28, 16, 17, 15, 12, 13 + dround 3, 0, 4, 2, 1, 25, 29, 17, 18, 16, 13, 14 + dround 2, 3, 1, 4, 0, 26, 30, 18, 19, 17, 14, 15 + dround 4, 2, 0, 1, 3, 27, 31, 19, 12, 18, 15, 16 + dround 1, 4, 3, 0, 2, 28, 24, 12, 13, 19, 16, 17 + + dround 0, 1, 2, 3, 4, 29, 25, 13, 14, 12, 17, 18 + dround 3, 0, 4, 2, 1, 30, 26, 14, 15, 13, 18, 19 + dround 2, 3, 1, 4, 0, 31, 27, 15, 16, 14, 19, 12 + dround 4, 2, 0, 1, 3, 24, 28, 16, 17, 15, 12, 13 + dround 1, 4, 3, 0, 2, 25, 29, 17, 18, 16, 13, 14 + + dround 0, 1, 2, 3, 4, 26, 30, 18, 19, 17, 14, 15 + dround 3, 0, 4, 2, 1, 27, 31, 19, 12, 18, 15, 16 + dround 2, 3, 1, 4, 0, 28, 24, 12 + dround 4, 2, 0, 1, 3, 29, 25, 13 + dround 1, 4, 3, 0, 2, 30, 26, 14 + + dround 0, 1, 2, 3, 4, 31, 27, 15 + dround 3, 0, 4, 2, 1, 24, , 16 + dround 2, 3, 1, 4, 0, 25, , 17 + dround 4, 2, 0, 1, 3, 26, , 18 + dround 1, 4, 3, 0, 2, 27, , 19 + + /* update state */ + add v8.2d, v8.2d, v0.2d + add v9.2d, v9.2d, v1.2d + add v10.2d, v10.2d, v2.2d + add v11.2d, v11.2d, v3.2d + + /* handled all input blocks? */ + cbnz w2, 0b + + /* store new state */ +3: st1 {v8.2d-v11.2d}, [x0] + mov w0, w2 + ret +ENDPROC(sha512_ce_transform) diff --git a/arch/arm/cpu/armv8/sha512_ce_glue.c b/arch/arm/cpu/armv8/sha512_ce_glue.c new file mode 100644 index 0000000000..4db78c8efd --- /dev/null +++ b/arch/arm/cpu/armv8/sha512_ce_glue.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sha512_ce_glue.c - SHA-512 secure hash using ARMv8 Crypto Extensions + * + * Copyright (C) 2024 Igor Opaniuk <igor.opaniuk(a)gmail.com> + */ + +#include <u-boot/sha512.h> + +extern void sha512_ce_transform(u64 state[SHA512_SUM_LEN / 8], u8 const *src, + u32 blocks); + +void sha512_block_fn(sha512_context *ctx, const unsigned char *data, + unsigned int blocks) +{ + if (!blocks) + return; + + sha512_ce_transform(ctx->state, data, blocks); +} diff --git a/lib/sha512.c b/lib/sha512.c index ffe2c5cd96..186ca4d2ca 100644 --- a/lib/sha512.c +++ b/lib/sha512.c @@ -16,6 +16,8 @@ #include <compiler.h> #include <u-boot/sha512.h> +#include <linux/compiler_attributes.h> + const uint8_t sha384_der_prefix[SHA384_DER_LEN] = { 0x30, 0x41, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x02, 0x05, @@ -187,8 +189,8 @@ sha512_transform(uint64_t *state, const uint8_t *input) a = b = c = d = e = f = g = h = t1 = t2 = 0; } -static void sha512_block_fn(sha512_context *sst, const uint8_t *src, - int blocks) +__weak void sha512_block_fn(sha512_context *sst, const uint8_t *src, + int blocks) { while (blocks--) { sha512_transform(sst->state, src); -- 2.34.1

3 2

[PATCH v2 0/3] imx93_var_som: Enable AHAB support
by Mathieu Othacehe 12 Feb '24

12 Feb '24

Hello, In this v2, I moved imx93_probe_mu to a dedicated header. Thanks, Mathieu Changelog: v2: Move imx93_probe_mu declaration to a header file Link to the previous revision: v1: https://lists.denx.de/pipermail/u-boot/2024-February/545528.html Mathieu Othacehe (3): imx93: Use a header for imx9_probe_mu declaration board: imx93_var_som: Probe ELE MU configs: imx93_var_som: Enable AHAB support arch/arm/include/asm/arch-imx9/mu.h | 13 +++++++++++++ board/freescale/imx93_evk/spl.c | 2 +- board/phytec/phycore_imx93/spl.c | 2 +- board/variscite/imx93_var_som/spl.c | 5 +++-- configs/imx93_var_som_defconfig | 1 + 5 files changed, 19 insertions(+), 4 deletions(-) create mode 100644 arch/arm/include/asm/arch-imx9/mu.h -- 2.41.0

3 5

[PATCH v2] spi: mxc_spi: Add imx6ul-ecspi compatible string
by Marek Vasut 12 Feb '24

12 Feb '24

Recent i.MX8MP DTs use new fsl,imx6ul-ecspi compatible string instead of the fsl,imx51-ecspi compatible string. Add the new compatible string to fix ECSPI operation on i.MX8MP. For details, see Linux: 48d74376fb68 ("arm64: dts: imx8mp: update ecspi compatible and clk") 8eb1252bbedf ("spi: imx: remove ERR009165 workaround on i.mx6ul") Fixes: 451799a6ceac ("arm: dts: imx8mp: Sync the DT with kernel 6.4-rc4") Reviewed-by: Fabio Estevam <festevam(a)gmail.com> Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: "NXP i.MX U-Boot Team" <uboot-imx(a)nxp.com> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Jagan Teki <jagan(a)amarulasolutions.com> Cc: Stefano Babic <sbabic(a)denx.de> --- V2: - Update commit message - Specify kernel commit where this got introduced - Add Fixes tag --- drivers/spi/mxc_spi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 33360a18329..e291092c481 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -670,6 +670,7 @@ static const struct dm_spi_ops mxc_spi_ops = { static const struct udevice_id mxc_spi_ids[] = { { .compatible = "fsl,imx51-ecspi" }, + { .compatible = "fsl,imx6ul-ecspi" }, { } }; -- 2.43.0

2 1

[PATCH] ARM: imx: Let SPL configure ECSPI1 clock on Data Modul i.MX8M Plus eDM SBC
by Marek Vasut 12 Feb '24

12 Feb '24

The SPL clock code does configure the ECSPI clock frequency, which has to match the mxc-spi driver configuration for successful SPI NOR boot. Drop the assigned-clock from DT ecspi1 node on this board to let the SPL clock code do the configuration and keep it aligned with the driver expectation. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: "NXP i.MX U-Boot Team" <uboot-imx(a)nxp.com> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Jagan Teki <jagan(a)amarulasolutions.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi index cb6ea356fd7..805b5f57955 100644 --- a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi @@ -45,6 +45,9 @@ }; &ecspi1 { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; + /delete-property/ assigned-clock-parents; bootph-pre-ram; flash@0 { bootph-pre-ram; -- 2.43.0

2 2

[PATCH] button: qcom-pmic: demote "unknown button" message to debug
by Caleb Connolly 12 Feb '24

12 Feb '24

This message isn't an error (there can be a watchdog subnode for example) but it shouldn't be printed unless this driver is being debugged. Demote it to a debug print. Signed-off-by: Caleb Connolly <caleb.connolly(a)linaro.org> --- drivers/button/button-qcom-pmic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/button/button-qcom-pmic.c b/drivers/button/button-qcom-pmic.c index 34a976d1e6c6..e6702139ca2d 100644 --- a/drivers/button/button-qcom-pmic.c +++ b/drivers/button/button-qcom-pmic.c @@ -133,7 +133,7 @@ static int button_qcom_pmic_bind(struct udevice *parent) } else if (NODE_IS_RESIN(node)) { uc_plat->label = "vol_down"; } else { - printf("Unknown button node '%s' should be 'pwrkey' or 'resin'\n", + debug("Unknown button node '%s' should be 'pwrkey' or 'resin'\n", ofnode_get_name(node)); device_unbind(dev); } -- 2.43.0

3 2

[PATCH] log: make global data relocatable
by Thomas Weißschuh 12 Feb '24

12 Feb '24

When `gd` is relocated during `spl_relocate_stack_gd()` the doubly-linked circular list in the `log_head` member is broken. The last element of the list should point back to the initial `list_head`, but as the initial `list_head` is moved the pointer becomes stale. As a result the loop in `log_dispatch` would never finish. Migrate the list to a singly-linked non-circular one which is easily relocatable. This should also remove the special handling introduced in commit e7595aa350ae ("x86: Allow logging to be used in SPL reliably"). Signed-off-by: Thomas Weißschuh <thomas.weissschuh(a)linutronix.de> --- common/log.c | 15 +++++++++------ include/asm-generic/global_data.h | 2 +- include/log.h | 2 +- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/common/log.c b/common/log.c index b2de57fcb3b8..098d40c86d81 100644 --- a/common/log.c +++ b/common/log.c @@ -109,7 +109,7 @@ struct log_device *log_device_find_by_name(const char *drv_name) { struct log_device *ldev; - list_for_each_entry(ldev, &gd->log_head, sibling_node) { + for (ldev = gd->log_head; ldev; ldev = ldev->sibling_node) { if (!strcmp(drv_name, ldev->drv->name)) return ldev; } @@ -218,7 +218,7 @@ static int log_dispatch(struct log_rec *rec, const char *fmt, va_list args) /* Emit message */ gd->processing_msg = true; - list_for_each_entry(ldev, &gd->log_head, sibling_node) { + for (ldev = gd->log_head; ldev; ldev = ldev->sibling_node) { if ((ldev->flags & LOGDF_ENABLE) && log_passes_filters(ldev, rec)) { if (!rec->msg) { @@ -400,7 +400,7 @@ static struct log_device *log_find_device_by_drv(struct log_driver *drv) { struct log_device *ldev; - list_for_each_entry(ldev, &gd->log_head, sibling_node) { + for (ldev = gd->log_head; ldev; ldev = ldev->sibling_node) { if (ldev->drv == drv) return ldev; } @@ -433,13 +433,16 @@ int log_init(void) struct log_driver *drv = ll_entry_start(struct log_driver, log_driver); const int count = ll_entry_count(struct log_driver, log_driver); struct log_driver *end = drv + count; + struct log_device **log_head; + + gd->log_head = NULL; + log_head = (struct log_device **)&gd->log_head; /* * We cannot add runtime data to the driver since it is likely stored * in rodata. Instead, set up a 'device' corresponding to each driver. * We only support having a single device for each driver. */ - INIT_LIST_HEAD((struct list_head *)&gd->log_head); while (drv < end) { struct log_device *ldev; @@ -451,8 +454,8 @@ int log_init(void) INIT_LIST_HEAD(&ldev->filter_head); ldev->drv = drv; ldev->flags = drv->flags; - list_add_tail(&ldev->sibling_node, - (struct list_head *)&gd->log_head); + *log_head = ldev; + log_head = &ldev->sibling_node; drv++; } gd->flags |= GD_FLG_LOG_READY; diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index fcc3c6e14ca3..a9a407b801c2 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -404,7 +404,7 @@ struct global_data { /** * @log_head: list of logging devices */ - struct list_head log_head; + struct log_device *log_head; /** * @log_fmt: bit mask for logging format * diff --git a/include/log.h b/include/log.h index 6e84f080ef3d..961233684d2a 100644 --- a/include/log.h +++ b/include/log.h @@ -455,7 +455,7 @@ struct log_device { unsigned short flags; struct log_driver *drv; struct list_head filter_head; - struct list_head sibling_node; + struct log_device *sibling_node; }; enum { --- base-commit: e8f2404e093daf6cc3ac2b3233e3c6770d13e371 change-id: 20240208-spl-logging-14a1257c3147 Best regards, -- Thomas Weißschuh <thomas.weissschuh(a)linutronix.de>

1 0

[PATCH] doc: rockchip: Clarify the rkspi image format further
by Dragan Simic 12 Feb '24

12 Feb '24

As discussed on the U-Boot mailing list, [1][2] only some Rockchip SoCs suffer from a bug in their BROMs that requires a specific format for their SPI images, which was the reason for the rkspi format to be introduced. Improve the description of the rkspi format a bit to mention this, for future reference and to make understanding it easier. [1] https://lore.kernel.org/u-boot/c32129ba-db25-4b9d-9a4a-032d88dfb9cd@kwiboo.… [2] https://lore.kernel.org/u-boot/CACdvmAjfCWicRd=LKKyob7fZo79AFkUQKy0e1HBb0zy… Signed-off-by: Dragan Simic <dsimic(a)manjaro.org> --- doc/README.rockchip | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/doc/README.rockchip b/doc/README.rockchip index 84caff8a24d3..e0c5c395ec6a 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -649,7 +649,12 @@ sector is used. The header is the same as with rksd and the maximum size is also 32KB (before spreading). The image should be written to the start of SPI flash. -See above for instructions on how to write a SPI image. +Only the BROMs of some Rockchip SoCs, such as the RK3399, suffer from a bug +that mandates the above-described data spreading, thus requiring the rkspi +format to be used for their SPI images. Rockchip SoCs that don't suffer +from this bug use the rksd format for their SPI images. + +See the section above for instructions on how to write an SPI image. rkmux.py --------

4 5

[PATCH v1] armv8: crypto: SHA-512 using ARMv8 Crypto Extensions
by Igor Opaniuk 12 Feb '24

12 Feb '24

From: Igor Opaniuk <igor.opaniuk(a)gmail.com> Add support for the SHA-512 Secure Hash Algorithm which uses ARMv8 Crypto Extensions. The CPU should support ARMv8.2 instruction set and implement SHA512H, SHA512H2, SHA512SU0, and SHA512SU1 instructions. This information can be obtained from ID_AA64ISAR0_EL1 (AArch64 Instruction Set Attribute Register 0), bits [15:12] should be 0b0010 [1], that indicates support for SHA512* instructions in AArch64 state. As not all ARMv8-base SoCs support that, ARMV8_CE_SHA512 is left disabled by default for now. Tested in QEMU for ARMv8 with compiled-in SHA-2 support. Even on emulated cpu the hashing speed increase was visible: With CE usage: => time hash sha512 0x40200000 0x2000000 Calculate hash Calculate hash sha512 for 40200000 ... 421fffff ==> 1aeae269f4eb7c37... time: 0.215 seconds Without CE usage: => time hash sha512 0x40200000 0x2000000 sha512 for 40200000 ... 421fffff ==> 1aeae269f4eb7c37... time: 0.356 seconds Real HW tests should provide much more improvement and objective results with 10x speed increase at least. The implementation is based on original implementation from Ard Biesheuvel in Linux kernel [2] [1] https://developer.arm.com/documentation/ddi0601/2023-12/AArch64-Registers/I… [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arc… CC: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> CC: Loic Poulain <loic.poulain(a)linaro.org> Signed-off-by: Igor Opaniuk <igor.opaniuk(a)gmail.com> --- arch/arm/cpu/armv8/Kconfig | 5 + arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/sha512_ce_core.S | 210 ++++++++++++++++++++++++++++ arch/arm/cpu/armv8/sha512_ce_glue.c | 20 +++ lib/sha512.c | 6 +- 5 files changed, 240 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv8/sha512_ce_core.S create mode 100644 arch/arm/cpu/armv8/sha512_ce_glue.c diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 9f0fb369f7..fd5c26421b 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -204,6 +204,11 @@ config ARMV8_CE_SHA256 bool "SHA-256 digest algorithm (ARMv8 Crypto Extensions)" default y if SHA256 +config ARMV8_CE_SHA512 + bool "SHA-512 digest algorithm (ARMv8 Crypto Extensions)" + depends on SHA512 + default n + endif endif diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index bba4f570db..3894f2bb2a 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -45,3 +45,4 @@ obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/ obj-$(CONFIG_XEN) += xen/ obj-$(CONFIG_ARMV8_CE_SHA1) += sha1_ce_glue.o sha1_ce_core.o obj-$(CONFIG_ARMV8_CE_SHA256) += sha256_ce_glue.o sha256_ce_core.o +obj-$(CONFIG_ARMV8_CE_SHA512) += sha512_ce_glue.o sha512_ce_core.o \ No newline at end of file diff --git a/arch/arm/cpu/armv8/sha512_ce_core.S b/arch/arm/cpu/armv8/sha512_ce_core.S new file mode 100644 index 0000000000..906291f35b --- /dev/null +++ b/arch/arm/cpu/armv8/sha512_ce_core.S @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto + * Extensions + * + * Copyright (C) 2018 Linaro Ltd <ard.biesheuvel(a)linaro.org> + * Copyright (C) 2024 Igor Opaniuk <igor.opaniuk(a)gmail.com> + */ + + #include <config.h> + #include <linux/linkage.h> + #include <asm/system.h> + #include <asm/macro.h> + + .macro adr_l, dst, sym + adrp \dst, \sym + add \dst, \dst, :lo12:\sym + .endm + + .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19 + .set .Lq\b, \b + .set .Lv\b\().2d, \b + .endr + + .macro sha512h, rd, rn, rm + .inst 0xce608000 | .L\rd | (.L\rn << 5) | (.L\rm << 16) + .endm + + .macro sha512h2, rd, rn, rm + .inst 0xce608400 | .L\rd | (.L\rn << 5) | (.L\rm << 16) + .endm + + .macro sha512su0, rd, rn + .inst 0xcec08000 | .L\rd | (.L\rn << 5) + .endm + + .macro sha512su1, rd, rn, rm + .inst 0xce608800 | .L\rd | (.L\rn << 5) | (.L\rm << 16) + .endm + + /* + * The SHA-512 round constants + */ + .section ".rodata", "a" + .align 4 +.Lsha512_rcon: + .quad 0x428a2f98d728ae22, 0x7137449123ef65cd + .quad 0xb5c0fbcfec4d3b2f, 0xe9b5dba58189dbbc + .quad 0x3956c25bf348b538, 0x59f111f1b605d019 + .quad 0x923f82a4af194f9b, 0xab1c5ed5da6d8118 + .quad 0xd807aa98a3030242, 0x12835b0145706fbe + .quad 0x243185be4ee4b28c, 0x550c7dc3d5ffb4e2 + .quad 0x72be5d74f27b896f, 0x80deb1fe3b1696b1 + .quad 0x9bdc06a725c71235, 0xc19bf174cf692694 + .quad 0xe49b69c19ef14ad2, 0xefbe4786384f25e3 + .quad 0x0fc19dc68b8cd5b5, 0x240ca1cc77ac9c65 + .quad 0x2de92c6f592b0275, 0x4a7484aa6ea6e483 + .quad 0x5cb0a9dcbd41fbd4, 0x76f988da831153b5 + .quad 0x983e5152ee66dfab, 0xa831c66d2db43210 + .quad 0xb00327c898fb213f, 0xbf597fc7beef0ee4 + .quad 0xc6e00bf33da88fc2, 0xd5a79147930aa725 + .quad 0x06ca6351e003826f, 0x142929670a0e6e70 + .quad 0x27b70a8546d22ffc, 0x2e1b21385c26c926 + .quad 0x4d2c6dfc5ac42aed, 0x53380d139d95b3df + .quad 0x650a73548baf63de, 0x766a0abb3c77b2a8 + .quad 0x81c2c92e47edaee6, 0x92722c851482353b + .quad 0xa2bfe8a14cf10364, 0xa81a664bbc423001 + .quad 0xc24b8b70d0f89791, 0xc76c51a30654be30 + .quad 0xd192e819d6ef5218, 0xd69906245565a910 + .quad 0xf40e35855771202a, 0x106aa07032bbd1b8 + .quad 0x19a4c116b8d2d0c8, 0x1e376c085141ab53 + .quad 0x2748774cdf8eeb99, 0x34b0bcb5e19b48a8 + .quad 0x391c0cb3c5c95a63, 0x4ed8aa4ae3418acb + .quad 0x5b9cca4f7763e373, 0x682e6ff3d6b2b8a3 + .quad 0x748f82ee5defb2fc, 0x78a5636f43172f60 + .quad 0x84c87814a1f0ab72, 0x8cc702081a6439ec + .quad 0x90befffa23631e28, 0xa4506cebde82bde9 + .quad 0xbef9a3f7b2c67915, 0xc67178f2e372532b + .quad 0xca273eceea26619c, 0xd186b8c721c0c207 + .quad 0xeada7dd6cde0eb1e, 0xf57d4f7fee6ed178 + .quad 0x06f067aa72176fba, 0x0a637dc5a2c898a6 + .quad 0x113f9804bef90dae, 0x1b710b35131c471b + .quad 0x28db77f523047d84, 0x32caab7b40c72493 + .quad 0x3c9ebe0a15c9bebc, 0x431d67c49c100d4c + .quad 0x4cc5d4becb3e42b6, 0x597f299cfc657e2a + .quad 0x5fcb6fab3ad6faec, 0x6c44198c4a475817 + + .macro dround, i0, i1, i2, i3, i4, rc0, rc1, in0, in1, in2, in3, in4 + .ifnb \rc1 + ld1 {v\rc1\().2d}, [x4], #16 + .endif + add v5.2d, v\rc0\().2d, v\in0\().2d + ext v6.16b, v\i2\().16b, v\i3\().16b, #8 + ext v5.16b, v5.16b, v5.16b, #8 + ext v7.16b, v\i1\().16b, v\i2\().16b, #8 + add v\i3\().2d, v\i3\().2d, v5.2d + .ifnb \in1 + ext v5.16b, v\in3\().16b, v\in4\().16b, #8 + sha512su0 v\in0\().2d, v\in1\().2d + .endif + sha512h q\i3, q6, v7.2d + .ifnb \in1 + sha512su1 v\in0\().2d, v\in2\().2d, v5.2d + .endif + add v\i4\().2d, v\i1\().2d, v\i3\().2d + sha512h2 q\i3, q\i1, v\i0\().2d + .endm + + /* + * void sha512_ce_transform(struct sha512_state *sst, u8 const *src, + * int blocks) + */ + .text +ENTRY(sha512_ce_transform) + /* load state */ + ld1 {v8.2d-v11.2d}, [x0] + + /* load first 4 round constants */ + adr_l x3, .Lsha512_rcon + ld1 {v20.2d-v23.2d}, [x3], #64 + + /* load input */ +0: ld1 {v12.2d-v15.2d}, [x1], #64 + ld1 {v16.2d-v19.2d}, [x1], #64 + sub w2, w2, #1 +#if __BYTE_ORDER == __LITTLE_ENDIAN + rev64 v12.16b, v12.16b + rev64 v13.16b, v13.16b + rev64 v14.16b, v14.16b + rev64 v15.16b, v15.16b + rev64 v16.16b, v16.16b + rev64 v17.16b, v17.16b + rev64 v18.16b, v18.16b + rev64 v19.16b, v19.16b +#endif + mov x4, x3 // rc pointer + + mov v0.16b, v8.16b + mov v1.16b, v9.16b + mov v2.16b, v10.16b + mov v3.16b, v11.16b + + // v0 ab cd -- ef gh ab + // v1 cd -- ef gh ab cd + // v2 ef gh ab cd -- ef + // v3 gh ab cd -- ef gh + // v4 -- ef gh ab cd -- + + dround 0, 1, 2, 3, 4, 20, 24, 12, 13, 19, 16, 17 + dround 3, 0, 4, 2, 1, 21, 25, 13, 14, 12, 17, 18 + dround 2, 3, 1, 4, 0, 22, 26, 14, 15, 13, 18, 19 + dround 4, 2, 0, 1, 3, 23, 27, 15, 16, 14, 19, 12 + dround 1, 4, 3, 0, 2, 24, 28, 16, 17, 15, 12, 13 + + dround 0, 1, 2, 3, 4, 25, 29, 17, 18, 16, 13, 14 + dround 3, 0, 4, 2, 1, 26, 30, 18, 19, 17, 14, 15 + dround 2, 3, 1, 4, 0, 27, 31, 19, 12, 18, 15, 16 + dround 4, 2, 0, 1, 3, 28, 24, 12, 13, 19, 16, 17 + dround 1, 4, 3, 0, 2, 29, 25, 13, 14, 12, 17, 18 + + dround 0, 1, 2, 3, 4, 30, 26, 14, 15, 13, 18, 19 + dround 3, 0, 4, 2, 1, 31, 27, 15, 16, 14, 19, 12 + dround 2, 3, 1, 4, 0, 24, 28, 16, 17, 15, 12, 13 + dround 4, 2, 0, 1, 3, 25, 29, 17, 18, 16, 13, 14 + dround 1, 4, 3, 0, 2, 26, 30, 18, 19, 17, 14, 15 + + dround 0, 1, 2, 3, 4, 27, 31, 19, 12, 18, 15, 16 + dround 3, 0, 4, 2, 1, 28, 24, 12, 13, 19, 16, 17 + dround 2, 3, 1, 4, 0, 29, 25, 13, 14, 12, 17, 18 + dround 4, 2, 0, 1, 3, 30, 26, 14, 15, 13, 18, 19 + dround 1, 4, 3, 0, 2, 31, 27, 15, 16, 14, 19, 12 + + dround 0, 1, 2, 3, 4, 24, 28, 16, 17, 15, 12, 13 + dround 3, 0, 4, 2, 1, 25, 29, 17, 18, 16, 13, 14 + dround 2, 3, 1, 4, 0, 26, 30, 18, 19, 17, 14, 15 + dround 4, 2, 0, 1, 3, 27, 31, 19, 12, 18, 15, 16 + dround 1, 4, 3, 0, 2, 28, 24, 12, 13, 19, 16, 17 + + dround 0, 1, 2, 3, 4, 29, 25, 13, 14, 12, 17, 18 + dround 3, 0, 4, 2, 1, 30, 26, 14, 15, 13, 18, 19 + dround 2, 3, 1, 4, 0, 31, 27, 15, 16, 14, 19, 12 + dround 4, 2, 0, 1, 3, 24, 28, 16, 17, 15, 12, 13 + dround 1, 4, 3, 0, 2, 25, 29, 17, 18, 16, 13, 14 + + dround 0, 1, 2, 3, 4, 26, 30, 18, 19, 17, 14, 15 + dround 3, 0, 4, 2, 1, 27, 31, 19, 12, 18, 15, 16 + dround 2, 3, 1, 4, 0, 28, 24, 12 + dround 4, 2, 0, 1, 3, 29, 25, 13 + dround 1, 4, 3, 0, 2, 30, 26, 14 + + dround 0, 1, 2, 3, 4, 31, 27, 15 + dround 3, 0, 4, 2, 1, 24, , 16 + dround 2, 3, 1, 4, 0, 25, , 17 + dround 4, 2, 0, 1, 3, 26, , 18 + dround 1, 4, 3, 0, 2, 27, , 19 + + /* update state */ + add v8.2d, v8.2d, v0.2d + add v9.2d, v9.2d, v1.2d + add v10.2d, v10.2d, v2.2d + add v11.2d, v11.2d, v3.2d + + /* handled all input blocks? */ + cbnz w2, 0b + + /* store new state */ +3: st1 {v8.2d-v11.2d}, [x0] + mov w0, w2 + ret +ENDPROC(sha512_ce_transform) diff --git a/arch/arm/cpu/armv8/sha512_ce_glue.c b/arch/arm/cpu/armv8/sha512_ce_glue.c new file mode 100644 index 0000000000..4db78c8efd --- /dev/null +++ b/arch/arm/cpu/armv8/sha512_ce_glue.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sha512_ce_glue.c - SHA-512 secure hash using ARMv8 Crypto Extensions + * + * Copyright (C) 2024 Igor Opaniuk <igor.opaniuk(a)gmail.com> + */ + +#include <u-boot/sha512.h> + +extern void sha512_ce_transform(u64 state[SHA512_SUM_LEN / 8], u8 const *src, + u32 blocks); + +void sha512_block_fn(sha512_context *ctx, const unsigned char *data, + unsigned int blocks) +{ + if (!blocks) + return; + + sha512_ce_transform(ctx->state, data, blocks); +} diff --git a/lib/sha512.c b/lib/sha512.c index ffe2c5cd96..186ca4d2ca 100644 --- a/lib/sha512.c +++ b/lib/sha512.c @@ -16,6 +16,8 @@ #include <compiler.h> #include <u-boot/sha512.h> +#include <linux/compiler_attributes.h> + const uint8_t sha384_der_prefix[SHA384_DER_LEN] = { 0x30, 0x41, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x02, 0x05, @@ -187,8 +189,8 @@ sha512_transform(uint64_t *state, const uint8_t *input) a = b = c = d = e = f = g = h = t1 = t2 = 0; } -static void sha512_block_fn(sha512_context *sst, const uint8_t *src, - int blocks) +__weak void sha512_block_fn(sha512_context *sst, const uint8_t *src, + int blocks) { while (blocks--) { sha512_transform(sst->state, src); -- 2.34.1

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[PATCH] mtd: spi-nor: Add NO_CHIP_ERASE flag
by Tejas Bhumkar 12 Feb '24

12 Feb '24

Since the opcode SPINOR_OP_CHIP_ERASE (0xc7) is not supported for the mt35xu02g flash, the NO_CHIP_ERASE flag has been added to enable sector erase functionality instead. Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar(a)amd.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 38a287487e..bfbdf7570b 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -329,7 +329,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, #endif /* CONFIG_SPI_FLASH_MT35XU */ { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, - { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ /* Spansion/Cypress -- single (large) sector size only, at least -- 2.27.0

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