February 2024 - U-Boot

[PATCH] doc: fix mistyped "env flags" command
by Thomas Weißschuh 12 Feb '24

12 Feb '24

Signed-off-by: Thomas Weißschuh <thomas(a)t-8ch.de> --- doc/usage/cmd/env.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/usage/cmd/env.rst b/doc/usage/cmd/env.rst index a859e32798cb..a7e21693a672 100644 --- a/doc/usage/cmd/env.rst +++ b/doc/usage/cmd/env.rst @@ -350,7 +350,7 @@ edit exists CONFIG_CMD_ENV_EXISTS -flsgs +flags CONFIG_CMD_ENV_FLAGS erase --- base-commit: d7aaaf4223d0a2f9f8c9eed47d7431860b3116d8 change-id: 20240211-doc-flsgs-31daddb198ec Best regards, -- Thomas Weißschuh <thomas(a)t-8ch.de>

2 1

Pull request doc-2024-04-rc2
by Heinrich Schuchardt 12 Feb '24

12 Feb '24

Dear Tom, The following changes since commit 91c37c4a20db24a4fc1d565c70035072d355cce0: Merge tag 'u-boot-imx-master-20240212' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2024-02-12 09:26:20 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-efi.git tags/doc-2024-04-rc2 for you to fetch changes up to 2eb39c9adafb4210c6bcf0aed75a34493c098c8e: doc/develop/codingstyle.rst: Clarify include section (2024-02-12 17:35:34 +0100) ---------------------------------------------------------------- Pull request doc-2024-04-rc2 Documenation: * Fix and extend utf8_to_utf32_stream() documentation * Fix rendering of OpenSBI logo in VisionFive 2 description * Document imxrt1170-evk board * codingstyle.rst: Clarify include section UEFI: * simplify error message in efi_disk_create_raw() ---------------------------------------------------------------- Heinrich Schuchardt (2): doc: board: starfive: fix rendering of OpenSBI logo efi_loader: simplify error message in efi_disk_create_raw() Janne Grunau (1): lib: charset: Fix and extend utf8_to_utf32_stream() documentation Jesse Taube (1): doc: imx: imxrt1170: Document imxrt1170-evk board Tom Rini (1): doc/develop/codingstyle.rst: Clarify include section doc/board/nxp/imxrt1170-evk.rst | 50 ++++++++++++++++++++++++++++++++++++++ doc/board/nxp/index.rst | 1 + doc/board/starfive/visionfive2.rst | 10 ++++---- doc/develop/codingstyle.rst | 23 +++++++++--------- include/charset.h | 14 +++++++++-- lib/efi_loader/efi_disk.c | 3 ++- 6 files changed, 81 insertions(+), 20 deletions(-) create mode 100644 doc/board/nxp/imxrt1170-evk.rst

2 1

[PATCH 0/4] board: beagle: Enable 32k and debounce configuration
by Nishanth Menon 12 Feb '24

12 Feb '24

Hi, This is a follow up from [1] - Without the 32k crystal configuration, wlan does'nt work. Debounce is needed for HDMI hpd gpio interrupt. At least the 32k configuration has been done for toradex and phytec boards, follow similar model of programming. This series is based on master commit e8f2404e093d + the findfdt series[2]. Nishanth Menon (4): board: beagle: beagleplay: Enable 32k crystal configs: am62x_beagleplay_r5_defconfig: Enable SPL_BOARD_INIT arm: mach-k3: am62: Add Debounce configuration register definitions board: beagle: beagleplay: Configure debounce registers arch/arm/mach-k3/include/mach/am62_hardware.h | 3 + board/beagle/beagleplay/beagleplay.c | 61 +++++++++++++++++++ configs/am62x_beagleplay_r5_defconfig | 1 + 3 files changed, 65 insertions(+) [1] https://lore.kernel.org/u-boot/20230725185253.2123433-4-nm@ti.com/ [2] https://lore.kernel.org/all/20240130130615.670783-1-nm@ti.com/ -- 2.43.0

2 6

[PATCH v2] net: designware: Support high memory nodes
by Nils Le Roux 12 Feb '24

12 Feb '24

Some platforms (such as the Lichee Pi 4A) have their dwmac device addressable only in high memory space. Storing the node's base address on 32 bits is not possible in such case. Use platform's physical address type to store the base address. Signed-off-by: Nils Le Roux <gilbsgilbert(a)gmail.com> Cc: Andre Przywara <andre.przywara(a)arm.com> --- Changes in v2: - explicitly define and handle ioaddr as a virtual address - use an intermediate variable to assign the PCI base address - use appropriate placeholder to print physical addresses --- drivers/net/designware.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index a174344b3e..78bfce07f6 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -678,8 +678,8 @@ int designware_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); struct dw_eth_dev *priv = dev_get_priv(dev); - u32 iobase = pdata->iobase; - ulong ioaddr; + phys_addr_t iobase = pdata->iobase; + void *ioaddr; int ret, err; struct reset_ctl_bulk reset_bulk; #ifdef CONFIG_CLK @@ -740,16 +740,18 @@ int designware_eth_probe(struct udevice *dev) * or via a PCI bridge, fill in plat before we probe the hardware. */ if (IS_ENABLED(CONFIG_PCI) && device_is_on_pci_bus(dev)) { - dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); - iobase &= PCI_BASE_ADDRESS_MEM_MASK; - iobase = dm_pci_mem_to_phys(dev, iobase); + u32 pcibase; + dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &pcibase); + pcibase &= PCI_BASE_ADDRESS_MEM_MASK; + + iobase = dm_pci_mem_to_phys(dev, pcibase); pdata->iobase = iobase; pdata->phy_interface = PHY_INTERFACE_MODE_RMII; } - debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); - ioaddr = iobase; + debug("%s, iobase=%pa, priv=%p\n", __func__, &iobase, priv); + ioaddr = phys_to_virt(iobase); priv->mac_regs_p = (struct eth_mac_regs *)ioaddr; priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET); priv->interface = pdata->phy_interface; -- 2.43.0

3 6

[PATCH RFC] pinctrl: add support for HiSilicon HiSTB SoCs
by Yang Xiwen via B4 Relay 12 Feb '24

12 Feb '24

From: Yang Xiwen <forbidden405(a)outlook.com> The first supported SoC is Hi3798MV200. Signed-off-by: Yang Xiwen <forbidden405(a)outlook.com> --- This patchset adds support for HiSTB ioconfig module. The module is used to set pins config(e.g. pull-up, pull-down, drive-strength etc..) and pinmux. The first supported chip is Hi3798MV200. Adding support for Hi3798CV200 should be also easy. Below is an example of the dts node: ```dts ioconfig: pinctrl@8a21000 { compatible = "hisilicon,hi3798mv200-ioconfig"; reg = <0x8a21000 0x180>; #pinctrl-cells = <1>; emmc_default: emmc-default-state { cdata-pins { // CDATA0-7 pins = "W20", "V20", "U20", "V19", "Y21", "W21", "V21", "U21"; bias-pullup; slew-rate = <1>; drive-strength = <8>; function = "emmc_cdata"; }; cclk-pin { pins = "T18"; bias-pullup; slew-rate = <1>; drive-strength = <8>; function = "emmc_cclk"; }; ccmd-pin { pins = "T20"; bias-pullup; slew-rate = <1>; drive-strength = <6>; function = "emmc_ccmd"; }; reset-pin { pins = "R20"; bias-disable; slew-rate = <1>; drive-strength = <1>; function = "emmc_rst"; }; datastrobe-pin { pins = "R21"; bias-pullup; slew-rate; drive-strength = <1>; function = "emmc_datastrobe"; }; }; }; ``` --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/hisilicon/Kconfig | 21 ++ drivers/pinctrl/hisilicon/Makefile | 6 + drivers/pinctrl/hisilicon/pinctrl-hi3798mv2x.c | 319 +++++++++++++++++++++++++ drivers/pinctrl/hisilicon/pinctrl-histb.c | 276 +++++++++++++++++++++ drivers/pinctrl/hisilicon/pinctrl-histb.h | 132 ++++++++++ 7 files changed, 756 insertions(+) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index a1d53cfbdb..d600a30492 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -346,6 +346,7 @@ endif source "drivers/pinctrl/broadcom/Kconfig" source "drivers/pinctrl/exynos/Kconfig" +source "drivers/pinctrl/hisilicon/Kconfig" source "drivers/pinctrl/intel/Kconfig" source "drivers/pinctrl/mediatek/Kconfig" source "drivers/pinctrl/meson/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 0e929d8ca0..79fb800faf 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -36,3 +36,4 @@ obj-$(CONFIG_$(SPL_)PINCTRL_STMFX) += pinctrl-stmfx.o obj-y += broadcom/ obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o obj-$(CONFIG_PINCTRL_STARFIVE) += starfive/ +obj-$(CONFIG_PINCTRL_HISILICON) += hisilicon/ diff --git a/drivers/pinctrl/hisilicon/Kconfig b/drivers/pinctrl/hisilicon/Kconfig new file mode 100644 index 0000000000..33c3048940 --- /dev/null +++ b/drivers/pinctrl/hisilicon/Kconfig @@ -0,0 +1,21 @@ +config PINCTRL_HISILICON + bool + +config PINCTRL_HISTB + bool "HiSilicon HiSTB pinctrl framework" + depends on PINCTRL + select PINCTRL_HISILICON + imply PINCONF + help + Support HiSTB SoCs IOCONFIG module + +menu "HiSTB pinctrl drivers" + depends on PINCTRL_HISTB + +config PINCTRL_HI3798MV2X + bool "HiSilicon Hi3798MV2X pinctrl driver" + depends on ARCH_HI3798MV2X + help + Support IOCONFIG on Hi3798MV2X SoCs + +endmenu diff --git a/drivers/pinctrl/hisilicon/Makefile b/drivers/pinctrl/hisilicon/Makefile new file mode 100644 index 0000000000..5afb64d4b6 --- /dev/null +++ b/drivers/pinctrl/hisilicon/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright 2024 (r) Yang Xiwen <forbidden405(a)foxmail.com> + +obj-$(CONFIG_PINCTRL_HISTB) += pinctrl-histb.o +obj-$(CONFIG_PINCTRL_HI3798MV2X) += pinctrl-hi3798mv2x.o diff --git a/drivers/pinctrl/hisilicon/pinctrl-hi3798mv2x.c b/drivers/pinctrl/hisilicon/pinctrl-hi3798mv2x.c new file mode 100644 index 0000000000..1e0a89675a --- /dev/null +++ b/drivers/pinctrl/hisilicon/pinctrl-hi3798mv2x.c @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * IOCONFIG driver for Hi3798MV2x SoCs + * + * Copyright 2024 (r) Yang Xiwen <forbidden405(a)outlook.com> + */ + +#include <dm/device.h> + +#include "pinctrl-histb.h" + +// The sequence is important! +enum hi3798mv2x_ioconfig_pins { + HI3798MV2X_Y19, + HI3798MV2X_W19, + HI3798MV2X_AA20, + HI3798MV2X_Y20, + HI3798MV2X_V19, + HI3798MV2X_Y21, + HI3798MV2X_W20, + HI3798MV2X_W21, + HI3798MV2X_V20, + HI3798MV2X_V21, + HI3798MV2X_U20, + HI3798MV2X_U21, + HI3798MV2X_T18, + HI3798MV2X_T19, + HI3798MV2X_T20, + HI3798MV2X_R20, + HI3798MV2X_R21, + HI3798MV2X_P20, + HI3798MV2X_R19, + HI3798MV2X_K18, + HI3798MV2X_J17, + HI3798MV2X_J18, + HI3798MV2X_H17, + HI3798MV2X_H18, + HI3798MV2X_K20, + HI3798MV2X_K19, + HI3798MV2X_J20, + HI3798MV2X_J19, + HI3798MV2X_H21, + HI3798MV2X_H20, + HI3798MV2X_H19, + HI3798MV2X_G20, + HI3798MV2X_G19, + HI3798MV2X_F21, + HI3798MV2X_F20, + HI3798MV2X_F19, + HI3798MV2X_E20, + HI3798MV2X_E19, + HI3798MV2X_D21, + HI3798MV2X_E18, + HI3798MV2X_C20, + HI3798MV2X_D19, + HI3798MV2X_B21, + HI3798MV2X_B18, + HI3798MV2X_C17, + HI3798MV2X_B17, + HI3798MV2X_A17, + HI3798MV2X_C16, + HI3798MV2X_B16, + HI3798MV2X_B4, + HI3798MV2X_C4, + HI3798MV2X_A3, + HI3798MV2X_B3, + HI3798MV2X_A2, + HI3798MV2X_B2, + HI3798MV2X_A6, + HI3798MV2X_C6, + HI3798MV2X_C5, + HI3798MV2X_C3, + HI3798MV2X_D4, + HI3798MV2X_D3, + HI3798MV2X_B1, + HI3798MV2X_C2, + HI3798MV2X_C1, + HI3798MV2X_A5, + HI3798MV2X_D5, +}; + +/* incomplete (yet) */ +static const struct histb_pin_function_desc hi3798mv2x_pin_funcs[] = { + HISTB_PIN_FUNC(0, "emmc_cdata", ((struct histb_pin_func_setup_entry[]){ + { HI3798MV2X_V19, 0x2 }, { HI3798MV2X_Y21, 0x2 }, { HI3798MV2X_W20, 0x2 }, + { HI3798MV2X_W21, 0x2 }, { HI3798MV2X_V20, 0x2 }, { HI3798MV2X_V21, 0x2 }, + { HI3798MV2X_U20, 0x2 }, { HI3798MV2X_U21, 0x2 }, })), + HISTB_PIN_FUNC(1, "emmc_cclk", + ((struct histb_pin_func_setup_entry[]){ { HI3798MV2X_T18, 0x2 } })), + HISTB_PIN_FUNC(2, "emmc_ccmd", + ((struct histb_pin_func_setup_entry[]){ { HI3798MV2X_T20, 0x2 } })), + HISTB_PIN_FUNC(3, "emmc_rst", + ((struct histb_pin_func_setup_entry[]){ { HI3798MV2X_R20, 0x2 } })), + HISTB_PIN_FUNC(4, "emmc_datastrobe", + ((struct histb_pin_func_setup_entry[]){ { HI3798MV2X_R21, 0x2 } })), +}; + +/* Frequentely used drive strength table */ +#define DRIVE_STRENGTH_TABLE_SAMPLE_A ((const u8[]){ 4, 3, 2, 1, 0 }) +#define DRIVE_STRENGTH_TABLE_SAMPLE_B ((const u8[]){ 18, 17, 16, 15, 13, 12, 11, 10, 9, 8, 7, 6, 4, 3, 2, 1, 0 }) + +static const struct histb_pin_desc hi3798mv2x_pins[] = { + HISTB_PIN(HI3798MV2X_Y19, "Y19", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "GPIO0_0", 0x0 }, { "NF_RDY", 0x1 }, { } }), + HISTB_PIN_FLAG_NOPD), + HISTB_PIN(HI3798MV2X_W19, "W19", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "GPIO0_1", 0x0 }, { "NF_CSN", 0x1 }, { } }), + HISTB_PIN_FLAG_NOPD), + HISTB_PIN(HI3798MV2X_AA20, "AA20", DRIVE_STRENGTH_TABLE_SAMPLE_B, + ((const struct histb_pin_mux_desc[]) + { { "GPIO0_2", 0x0 }, { "NF_DQSN", 0x1 }, { "BOOT_SEL2", 0x2 }, { } }), 0), + HISTB_PIN(HI3798MV2X_Y20, "Y20", DRIVE_STRENGTH_TABLE_SAMPLE_B, + ((const struct histb_pin_mux_desc[]){ { "NF_DQS", 0x1 }, { } }), 0), + HISTB_PIN(HI3798MV2X_V19, "V19", DRIVE_STRENGTH_TABLE_SAMPLE_B, + ((const struct histb_pin_mux_desc[]) + { { "GPIO0_4", 0x0 }, { "NF_DQ7", 0x1 }, { "EMMC_CDATA3", 0x2 }, { } }), 0), + HISTB_PIN(HI3798MV2X_Y21, "Y21", DRIVE_STRENGTH_TABLE_SAMPLE_B, + ((const struct histb_pin_mux_desc[]) + { { "GPIO0_5", 0x0 }, { "NF_DQ6", 0x1 }, { "EMMC_CDATA4", 0x2 }, { } }), 0), + HISTB_PIN(HI3798MV2X_W20, "W20", DRIVE_STRENGTH_TABLE_SAMPLE_B, + ((const struct histb_pin_mux_desc[]) + { { "GPIO0_6", 0x0 }, { "NF_DQ5", 0x1 }, { "EMMC_CDATA0", 0x2 }, { } }), 0), + HISTB_PIN(HI3798MV2X_W21, "W21", DRIVE_STRENGTH_TABLE_SAMPLE_B, + ((const struct histb_pin_mux_desc[]) + { { "GPIO0_7", 0x0 }, { "NF_DQ4", 0x1 }, { "EMMC_CDATA5", 0x2 }, { } }), 0), + HISTB_PIN(HI3798MV2X_V20, "V20", DRIVE_STRENGTH_TABLE_SAMPLE_B, + ((const struct histb_pin_mux_desc[]) + { { "GPIO1_0", 0x0 }, { "NF_DQ3", 0x1 }, { "EMMC_CDATA1", 0x2 }, { } }), 0), + HISTB_PIN(HI3798MV2X_V21, "V21", DRIVE_STRENGTH_TABLE_SAMPLE_B, + ((const struct histb_pin_mux_desc[]) + { { "GPIO1_1", 0x0 }, { "NF_DQ2", 0x1 }, { "EMMC_CDATA6", 0x2 }, { } }), 0), + HISTB_PIN(HI3798MV2X_U20, "U20", DRIVE_STRENGTH_TABLE_SAMPLE_B, + ((const struct histb_pin_mux_desc[]) + { { "GPIO1_2", 0x0 }, { "NF_DQ1", 0x1 }, { "EMMC_CDATA2", 0x2 }, { } }), 0), + HISTB_PIN(HI3798MV2X_U21, "U21", DRIVE_STRENGTH_TABLE_SAMPLE_B, + ((const struct histb_pin_mux_desc[]) + { { "GPIO1_3", 0x0 }, { "NF_DQ0", 0x1 }, { "EMMC_CDATA7", 0x2 }, { } }), 0), + HISTB_PIN(HI3798MV2X_T18, "T18", DRIVE_STRENGTH_TABLE_SAMPLE_B, + ((const struct histb_pin_mux_desc[]) + { { "GPIO1_4", 0x0 }, { "NF_WEN", 0x1 }, { "EMMC_CCLK_OUT", 0x2 }, { } }), 0), + HISTB_PIN(HI3798MV2X_T19, "T19", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]) + { { "GPIO1_5", 0x0 }, { "NF_ALE", 0x1 }, { } }), 0), + HISTB_PIN(HI3798MV2X_T20, "T20", DRIVE_STRENGTH_TABLE_SAMPLE_B, + ((const struct histb_pin_mux_desc[]) + { { "GPIO1_6", 0x0 }, { "NF_CLE", 0x1 }, { "EMMC_CCMD", 0x2 }, { } }), 0), + HISTB_PIN(HI3798MV2X_R20, "R20", DRIVE_STRENGTH_TABLE_SAMPLE_B, + ((const struct histb_pin_mux_desc[]) + { { "GPIO1_7", 0x0 }, { "NF_REC", 0x1 }, { "EMMC_RST", 0x2 }, { } }), 0), + HISTB_PIN(HI3798MV2X_R21, "R21", DRIVE_STRENGTH_TABLE_SAMPLE_B, + ((const struct histb_pin_mux_desc[]) + { { "GPIO2_0", 0x0 }, { "NF_REN", 0x1 }, { "EMMC_DATA_STROBE", 0x2 }, { } }), 0), + HISTB_PIN(HI3798MV2X_P20, "P20", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]) + { { "PMC_CORE0", 0x0 }, { "I2C0_SDA", 0x1 }, { "GPIO2_1", 0x2 }, { } }), 0), + HISTB_PIN(HI3798MV2X_R19, "R19", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]) + { { "PMC_GPU0", 0x0 }, { "I2C0_SCL", 0x1 }, { "GPIO2_2", 0x2 }, { } }), 0), + HISTB_PIN(HI3798MV2X_K18, "K18", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]) { { "GPIO2_3", 0x0 }, { "SATA0_PWREN", 0x1 }, + { "UART3_CTSN", 0x2 }, { "TSI0_D7", 0x3 }, { "TSI3_CLK", 0x4 }, { "SIM1_DATA", 0x5 }, { } }), 0), + HISTB_PIN(HI3798MV2X_J17, "J17", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]) + { { "GPIO2_4", 0x0 }, { "SATA0_LED_N", 0x1 }, { "UART3_RTSN", 0x2 }, { "TSI1_SYNC", 0x3 }, + { "TSI1_D1", 0x4 }, { "TSI0D6", 0x5 }, { "TSI3_VALID", 0x6 }, { "SIM1DET", 0x7 }, { } }), 0), + HISTB_PIN(HI3798MV2X_J18, "J18", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "GPIO2_5", 0x0 }, { "UART3_RXD", 0x1 }, + { "TSI1_D0", 0x2 }, { "TSIO_D5", 0x3 }, { "TSI3_D0", 0x4 }, { "SIM1_RST", 0x5 }, { } }), 0), + HISTB_PIN(HI3798MV2X_H17, "H17", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "GPIO2_6", 0x0 }, { "UART3_TXD", 0x1 }, + { "TSI1_CLK", 0x2 }, { "TSIO_D4", 0x3 }, { "TSI2_VALID", 0x4 }, { "SIM1_CLK", 0x5 }, { } }), 0), + HISTB_PIN(HI3798MV2X_H18, "H18", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "GPIO2_7", 0x0 }, { "I2C2_SDA", 0x1 }, + { "TSI1_VALID", 0x2 }, { "TSIO_D3", 0x3 }, { "TSI2_D0", 0x4 }, { "SIM1_PWREN", 0x5 }, { } }), 0), + HISTB_PIN(HI3798MV2X_K20, "K20", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "JTAG_TRSTN", 0x0 }, { "I2C2_SCL", 0x1 }, + { "SPI0_SD0", 0x2 }, { "SIM0_DATA", 0x3 }, { "GPIO3_0", 0x4 }, { } }), 0), + HISTB_PIN(HI3798MV2X_K19, "K19", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "JTAG_TDI", 0x0 }, { "SPIO_CSN", 0x1 }, + { "SIM0_DET", 0x2 }, { "GPIO3_1", 0x3 }, { "UART2_CTSN", 0x4 }, { } }), 0), + HISTB_PIN(HI3798MV2X_J20, "J20", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "JTAG_TMS", 0x0 }, { "I2S_RX_BCLK", 0x1 }, + { "SPI0_SCLK", 0x2 }, { "SIM0_RST", 0x3 }, { "GPIO3_2", 0x4 }, { "UART2_TXD", 0x5 }, { } }), 0), + HISTB_PIN(HI3798MV2X_J19, "J19", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "JTAG_TCK", 0x0 }, { "I2S_RX_WS", 0x1 }, + { "SPI0_SDI", 0x2 }, { "SIM0_CLK", 0x3 }, { "GPIO3_3", 0x4 }, { "UART2_RXD", 0x5 }, { } }), 0), + HISTB_PIN(HI3798MV2X_H21, "H21", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "JTAG_TDO", 0x0 }, { "I2S_RX_MCLK", 0x1 }, + { "I2S_DOUT3", 0x2 }, { "SIM0_PWREN", 0x3 }, { "GPIO3_4", 0x4 }, { "UART2_RTSN", 0x5 }, { } }), 0), + HISTB_PIN(HI3798MV2X_H20, "H20", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "GPIO3_5", 0x0 }, { "I2S_MCLK", 0x1 }, + { "I2S_DOUT2", 0x2 }, { "SF_WPN_IO2", 0x3 }, { "TSO0_SYNC", 0x4 }, { } }), HISTB_PIN_FLAG_NOPD), + HISTB_PIN(HI3798MV2X_H19, "H19", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "GPIO3_6", 0x0 }, { "I2S_WS", 0x1 }, + { "I2S_DOUT1", 0x2 }, { "TSI1_SYNC", 0x3 }, { "TSI1_D1", 0x4 }, { "SF_SDI_IO1", 0x5 }, + { "TSO0_VALID", 0x6 }, { } }), 0), + HISTB_PIN(HI3798MV2X_G20, "G20", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "GPIO3_7", 0x0 }, { "I2S_DOUT0", 0x1 }, + { "TSI1_D0", 0x3 }, { "SF_CSN", 0x5 }, { "TSO0_CLK", 0x6 }, { } }), HISTB_PIN_FLAG_NOPD), + HISTB_PIN(HI3798MV2X_G19, "G19", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "GPIO4_0", 0x0 }, { "I2S_BCLK", 0x1 }, + { "I2S_WS", 0x2 }, { "TSI1_CLK", 0x3 }, { "SF_HOLDN_IO3", 0x5 }, { "TSO0_D0", 0x6 }, { } }), + HISTB_PIN_FLAG_NOPD), + HISTB_PIN(HI3798MV2X_F21, "F21", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "GPIO4_1", 0x0 }, { "I2S_DIN", 0x1 }, + { "I2S_BCLK", 0x2 }, { "TSI1_VALID", 0x3 }, { "SF_CLK", 0x5 }, { } }), 0), + HISTB_PIN(HI3798MV2X_F20, "F20", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "GPIO4_2", 0x0 }, { "SDIO1_CWPR", 0x1 }, + { "I2S_MCLK", 0x2 }, { "SF_SDO_IO0", 0x4 }, { } }), 0), + HISTB_PIN(HI3798MV2X_F19, "F19", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "GPIO4_3", 0x0 }, { "SDIO1_CARD_POWER_EN", 0x1 }, + { "I2C1_SCL", 0x3 }, { "I2S_RX_BCLK", 0x4 }, { "TSI0_D2", 0x5 }, { "TSI2_CLK", 0x6 }, { } }), 0), + HISTB_PIN(HI3798MV2X_E20, "E20", ((const u8[]){ 18, 16, 14, 12, 5, 4, 2, 1, 0 }), + ((const struct histb_pin_mux_desc[]){ { "GPIO4_4", 0x0 }, { "SDIO1_CDATA1", 0x1 }, + { "I2S_RX_WS", 0x4 }, { "TSI0_D1", 0x5 }, { "I2C1_SDA", 0x6 }, { } }), 0), + HISTB_PIN(HI3798MV2X_E19, "E19", ((const u8[]){ 18, 16, 14, 12, 5, 4, 2, 1, 0 }), + ((const struct histb_pin_mux_desc[]){ { "GPIO4_5", 0x0 }, { "SDIO1_CDATA0", 0x1 }, + { "TSI0_D1", 0x2 }, { "TSI0_SYNC", 0x3 }, { "I2S_RX_MCLK", 0x4 }, { "TSI0_DO", 0x5 }, + { "I2C1_SCL", 0x6 }, { } }), 0), + HISTB_PIN(HI3798MV2X_D21, "D21", DRIVE_STRENGTH_TABLE_SAMPLE_B, + ((const struct histb_pin_mux_desc[]){ { "GPIO4_6", 0x0 }, { "SDIO1_CCLK_OUT", 0x1 }, + { "TSI0_DO", 0x3 }, { "I2S_MCLK", 0x4 }, { "TSI0_CLK", 0x5 }, { "TSI1_VALID", 0x6 }, { } }), 0), + HISTB_PIN(HI3798MV2X_E18, "E18", ((const u8[]){ 18, 16, 14, 12, 5, 4, 2, 1, 0 }), + ((const struct histb_pin_mux_desc[]){ { "GPIO4_7", 0x0 }, { "SDIO1_CCMD", 0x1 }, + { "TSI0_CLK", 0x3 }, { "I2S_WS", 0x4 }, { "TSI0_VALID", 0x5 }, { "TSI1_D0", 0x6 }, { } }), 0), + HISTB_PIN(HI3798MV2X_C20, "C20", ((const u8[]){ 18, 16, 14, 12, 5, 4, 2, 1, 0 }), + ((const struct histb_pin_mux_desc[]){ { "GPIO6_0", 0x0 }, { "SDIO1_CDATA3", 0x1 }, + { "TSI1_CLK", 0x2 }, { "TSI0_VALID", 0x3 }, { "I2S_DOUT0", 0x4 }, { "I2C2_SCL", 0x5 }, + { "TSI0_VALID", 0x6 }, { } }), 0), + HISTB_PIN(HI3798MV2X_D19, "D19", ((const u8[]){ 18, 16, 14, 12, 5, 4, 2, 1, 0 }), + ((const struct histb_pin_mux_desc[]){ { "GPIO6_1", 0x0 }, { "SDIO1_CDATA2", 0x1 }, + { "I2C2_SCL", 0x3 }, { "I2S_BCLK", 0x4 }, { "I2C2_SDA", 0x5 }, { "TSI0_D0", 0x6 }, { } }), 0), + HISTB_PIN(HI3798MV2X_B21, "B21", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "GPIO6_2", 0x0 }, { "SDIO1_CARD_DETECT", 0x1 }, + { "I2C2_SDA", 0x3 }, { "I2S_DIN", 0x4 }, { "TSI0_CLK", 0x6 }, { } }), 0), + HISTB_PIN(HI3798MV2X_B18, "B18", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "JTAG_SEL", 0x0 }, { "GPIO6_3", 0x1 }, { } }), 0), + HISTB_PIN(HI3798MV2X_C17, "C17", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "GPIO6_4", 0x0 }, { "SPDIF_OUT", 0x1 }, { } }), 0), + HISTB_PIN(HI3798MV2X_B17, "B17", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "HDMITX_HOTPLUG", 0x1 }, { "GPIO6_5", 0x2 }, { } }), 0), + HISTB_PIN(HI3798MV2X_A17, "A17", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "HDMITX_SDA", 0x1 }, { "GPIO6_6", 0x2 }, { } }), 0), + HISTB_PIN(HI3798MV2X_C16, "C16", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "HDMITX_SCL", 0x1 }, { "GPIO6_7", 0x2 }, { } }), 0), + HISTB_PIN(HI3798MV2X_B16, "B16", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "HDMITX_CEC", 0x1 }, { "GPIO7_0", 0x2 }, { } }), + HISTB_PIN_FLAG_NOPU | HISTB_PIN_FLAG_NOPD | HISTB_PIN_FLAG_NOSR), + HISTB_PIN(HI3798MV2X_B4, "B4", ((const u8[]){ 18, 16, 14, 12, 10, 8, 6, 4, 0 }), + ((const struct histb_pin_mux_desc[]){ { "GPIO7_4", 0x0 }, { "RGMII_RXCK", 0x1 }, + { "RMII_TXD1", 0x2 }, { "SDIOO_CDATA1", 0x3 }, { } }), HISTB_PIN_FLAG_HAS_SCHMITT), + HISTB_PIN(HI3798MV2X_C4, "C4", ((const u8[]){ 18, 16, 14, 12, 10, 8, 6, 4, 0 }), + ((const struct histb_pin_mux_desc[]){ { "GPIO7_5", 0x0 }, { "RGMII_RXDV", 0x1 }, + { "RMII_TXD0", 0x2 }, { "SDIO0_CDATA0", 0x3 }, { } }), HISTB_PIN_FLAG_HAS_SCHMITT), + HISTB_PIN(HI3798MV2X_A3, "A3", DRIVE_STRENGTH_TABLE_SAMPLE_B, + ((const struct histb_pin_mux_desc[]){ { "GPIO7_6", 0x0 }, { "RGMII_RXD0", 0x1 }, + { "RMII_TXEN", 0x2 }, { "SDIO0_CCLK_OUT", 0x3 }, { } }), 0), + HISTB_PIN(HI3798MV2X_B3, "B3", ((const u8[]){ 18, 16, 14, 12, 10, 8, 6, 4, 0 }), + ((const struct histb_pin_mux_desc[]){ { "GPIO7_7", 0x0 }, { "RGMII_RXD1", 0x1 }, + { "RMII_RXDV", 0x2 }, { "SDIO0_CCMD", 0x3 }, { } }), HISTB_PIN_FLAG_HAS_SCHMITT), + HISTB_PIN(HI3798MV2X_A2, "A2", ((const u8[]){ 18, 16, 14, 12, 10, 8, 6, 4, 0 }), + ((const struct histb_pin_mux_desc[]){ { "GPIO8_0", 0x0 }, { "RGMII_RXD2", 0x1 }, + { "RMII_RXD0", 0x2 }, { "SDIO0_CDATA3", 0x3 }, { } }), HISTB_PIN_FLAG_HAS_SCHMITT), + HISTB_PIN(HI3798MV2X_B2, "B2", ((const u8[]){ 18, 16, 14, 12, 10, 8, 6, 4, 0 }), + ((const struct histb_pin_mux_desc[]){ { "GPIO8_1", 0x0 }, { "RGMII_RXD3", 0x1 }, + { "RMII_RXD1", 0x2 }, { "SDIOO_CDATA2", 0x3 }, { } }), HISTB_PIN_FLAG_HAS_SCHMITT), + HISTB_PIN(HI3798MV2X_A6, "A6", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "GPIO7_1", 0x0 }, { "RGMII_RST", 0x1 }, + { "UART3_TXD", 0x2 }, { "FE_LED_ACT", 0x3 }, { } }), 0), + HISTB_PIN(HI3798MV2X_C6, "C6", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "GPIO7_2", 0x0 }, { "RGMII_MDIO", 0x1 }, + { "UART3_RXD", 0x2 }, { "FE_LED_BASE", 0x3 }, { } }), 0), + HISTB_PIN(HI3798MV2X_C5, "C5", DRIVE_STRENGTH_TABLE_SAMPLE_A, + ((const struct histb_pin_mux_desc[]){ { "GPIO7_3", 0x0 }, { "RGMII_MDCK", 0x1 }, + { "RMII_RST", 0x2 }, { "SDIO0_CARD_DETECT", 0x3 }, { } }), 0), + HISTB_PIN(HI3798MV2X_C3, "C3", ((const u8[]){ 18, 16, 14, 12, 10, 8, 6, 4, 0 }), + ((const struct histb_pin_mux_desc[]){ { "GPIO8_2", 0x0 }, { "RGMII_TXEN", 0x1 }, + { "BOOT_SEL0", 0x2 }, { } }), HISTB_PIN_FLAG_HAS_SCHMITT), + HISTB_PIN(HI3798MV2X_D4, "D4", ((const u8[]){ 18, 16, 14, 12, 10, 8, 6, 4, 0 }), + ((const struct histb_pin_mux_desc[]){ { "GPIO8_3", 0x0 }, { "RGMII_TXCK", 0x1 }, + { "UART3_CTSN", 0x2 }, { } }), HISTB_PIN_FLAG_HAS_SCHMITT), + HISTB_PIN(HI3798MV2X_D3, "D3", ((const u8[]){ 18, 16, 14, 12, 10, 8, 6, 4, 0 }), + ((const struct histb_pin_mux_desc[]){ { "GPIO8_4", 0x0 }, { "RGMII_TXD3", 0x1 }, + { "UART3_RTSN", 0x2 }, { } }), HISTB_PIN_FLAG_HAS_SCHMITT), + HISTB_PIN(HI3798MV2X_B1, "B1", DRIVE_STRENGTH_TABLE_SAMPLE_B, + ((const struct histb_pin_mux_desc[]){ { "GPIO8_5", 0x0 }, { "RGMII_TXD2", 0x1 }, + { "RMII_MDCK", 0x2 }, { "BOOT_SEL1", 0x3 }, { } }), HISTB_PIN_FLAG_HAS_SCHMITT), + HISTB_PIN(HI3798MV2X_C2, "C2", ((const u8[]){ 18, 16, 14, 12, 10, 8, 6, 4, 0 }), + ((const struct histb_pin_mux_desc[]){ { "RGMII_TXD1", 0x1 }, { "RMII_MDI0", 0x2 }, + { "SDIO0_CWPR", 0x3 }, { "GPIO8_6", 0x4 }, { } }), HISTB_PIN_FLAG_HAS_SCHMITT), + HISTB_PIN(HI3798MV2X_C1, "C1", DRIVE_STRENGTH_TABLE_SAMPLE_B, + ((const struct histb_pin_mux_desc[]){ { "RGMII_TXDO", 0x1 }, { "RMII_REFCLK", 0x2 }, + { "SDIO0_CARD_POWER_EN", 0x3 }, { "GPIO8_7", 0x4 }, { } }), HISTB_PIN_FLAG_HAS_SCHMITT), + HISTB_PIN(HI3798MV2X_A5, "A5", ((const u8 *)NULL), + ((const struct histb_pin_mux_desc[]){ { "GPIO9_0", 0x0 }, { "CLKOUT_25M", 0x1 }, { } }), 0), + HISTB_PIN(HI3798MV2X_D5, "D5", ((const u8 *)NULL), + ((const struct histb_pin_mux_desc[]){ { "PMC_CPU0", 0x0 }, { "GPIO9_1", 0x1 }, { } }), + HISTB_PIN_FLAG_NOPU | HISTB_PIN_FLAG_NOPD | HISTB_PIN_FLAG_NOSR), +}; + +static struct histb_pinctrl_priv hi3798mv2x_pinctrl_priv = { + .pins = hi3798mv2x_pins, + .funcs = hi3798mv2x_pin_funcs, + .pin_nums = ARRAY_SIZE(hi3798mv2x_pins), + .func_nums = ARRAY_SIZE(hi3798mv2x_pin_funcs), +}; + +static const struct udevice_id hi3798mv2x_pinctrl_match[] = { + { .compatible = "hisilicon,hi3798mv200-ioconfig", .data = (ulong)&hi3798mv2x_pinctrl_priv }, + { }, +}; + +U_BOOT_DRIVER(hi3798mv2x_pinctrl) = { + .name = "hi3798mv2x_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = hi3798mv2x_pinctrl_match, + .of_to_plat = histb_pinctrl_of_to_plat, + .ops = &histb_pinctrl_ops, +}; diff --git a/drivers/pinctrl/hisilicon/pinctrl-histb.c b/drivers/pinctrl/hisilicon/pinctrl-histb.c new file mode 100644 index 0000000000..d0521c3459 --- /dev/null +++ b/drivers/pinctrl/hisilicon/pinctrl-histb.c @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * IOCONFIG pinctrl driver for HiSTB SoCs + * + * Copyright 2024 (r) Yang Xiwen <forbidden405(a)outlook.com> + */ + +#include <asm/io.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <dm/device-internal.h> +#include <dm/pinctrl.h> +#include <dm/read.h> +#include <linux/bitfield.h> +#include <linux/kernel.h> +#include <linux/types.h> + +#include "pinctrl-histb.h" + +static int histb_pinctrl_get_pins_count(struct udevice *dev) +{ + struct histb_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->pin_nums; +} + +static const char *histb_pinctrl_get_pin_name(struct udevice *dev, unsigned int selector) +{ + struct histb_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->pins[selector].name; +} + +static int histb_pinctrl_get_functions_count(struct udevice *dev) +{ + struct histb_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->func_nums; +} + +static const char *histb_pinctrl_get_function_name(struct udevice *dev, unsigned int selector) +{ + struct histb_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->funcs[selector].name; +} + +static int histb_pinctrl_pinmux_set(struct udevice *dev, unsigned int pin_selector, + unsigned int func_selector) +{ + struct histb_pinctrl_priv *priv = dev_get_priv(dev); + const struct histb_pin_function_desc *func = &priv->funcs[func_selector]; + const struct histb_pin_func_setup_entry *func_setup_tbl = func->cfg_tbl; + int i; + u32 reg; + void __iomem *pin_reg = (u32 *)priv->base + priv->pins[pin_selector].number; + bool found = false; + + for (i = 0; i < func->pins_num; i++) { + if (func_setup_tbl[i].pin_selector == pin_selector) { + reg = readl(pin_reg); + reg &= ~HISTB_PIN_FUNC_MASK; + reg |= func_setup_tbl[i].mask; + writel(reg, pin_reg); + + found = true; + break; + } + } + + if (!found) { + dev_err(dev, "Unable to set pin %d to the given function %d\n", + pin_selector, func_selector); + return -EINVAL; + } + + return 0; +} + +static const struct pinconf_param histb_pinctrl_pinconf_params[] = { + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, 0 }, + { "bias-pullup", PIN_CONFIG_BIAS_PULL_UP, 0 }, + { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, + { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 1 }, + { "slew-rate", PIN_CONFIG_SLEW_RATE, 1 }, +}; + +enum histb_pinctrl_bias_status { + BIAS_PULL_DOWN, + BIAS_PULL_UP, + BIAS_DISABLE, +}; + +static int histb_pinctrl_set_bias(struct udevice *dev, unsigned int selector, + enum histb_pinctrl_bias_status status) +{ + struct histb_pinctrl_priv *priv = dev_get_priv(dev); + void __iomem *pin_reg = (u32 *)priv->base + priv->pins[selector].number; + u32 reg = readl(pin_reg); + + reg &= ~(HISTB_PIN_PULLDOWN | HISTB_PIN_PULLUP); + + switch (status) { + case BIAS_DISABLE: + break; + case BIAS_PULL_DOWN: + reg |= HISTB_PIN_PULLDOWN; + break; + case BIAS_PULL_UP: + reg |= HISTB_PIN_PULLUP; + break; + } + + writel(reg, pin_reg); + + return 0; +} + +static int histb_pinctrl_set_slew_rate(struct udevice *dev, unsigned int pin_selector, + unsigned int argument) +{ + struct histb_pinctrl_priv *priv = dev_get_priv(dev); + void __iomem *pin_reg = (u32 *)priv->base + priv->pins[pin_selector].number; + u32 reg = readl(pin_reg); + + if (likely(argument == 1)) { + reg |= HISTB_PIN_SLEWRATE; + } else if (argument == 0) { + reg &= ~HISTB_PIN_SLEWRATE; + } else { + dev_err(dev, "slew rate argument can be only 0 or 1!\n"); + return -EINVAL; + } + + writel(reg, pin_reg); + + return 0; +} + +static int histb_pinctrl_set_schmitt(struct udevice *dev, unsigned int pin_selector, + unsigned int argument) +{ + struct histb_pinctrl_priv *priv = dev_get_priv(dev); + void __iomem *pin_reg = (u32 *)priv->base + priv->pins[pin_selector].number; + u32 reg = readl(pin_reg); + + if (likely(argument == 0)) { + reg &= ~HISTB_PIN_SCHMITT; + } else if (argument == 1) { + reg |= HISTB_PIN_SCHMITT; + } else { + dev_err(dev, "schmitt argument can be only 0 or 1!\n"); + return -EINVAL; + } + + writel(reg, pin_reg); + + return 0; +} + +static int histb_pinctrl_set_drive_strength(struct udevice *dev, unsigned int pin_selector, + unsigned int argument) +{ + struct histb_pinctrl_priv *priv = dev_get_priv(dev); + const u8 *drv_tbl = priv->pins[pin_selector].drv_tbl; + void __iomem *pin_reg = (u32 *)priv->base + priv->pins[pin_selector].number; + u32 reg = readl(pin_reg); + int i = -1; + + if (unlikely(argument == 0)) { + dev_err(dev, "the minimal drive strength is 1mA!\n"); + return -EINVAL; + } + + if (unlikely(!drv_tbl)) { + dev_err(dev, "pin %u does not support setting drive strength!\n", pin_selector); + return -ENOENT; + } + + // calculate the largest drive-strength that does not exceeds the given value + // if the lowest value is still too large, use that anyway + // TODO: use bsearch()? + while (drv_tbl[++i] > argument) + ; + + if (!drv_tbl[i]) + i--; + + reg &= ~HISTB_PIN_DRV_MASK; + reg |= FIELD_PREP(HISTB_PIN_DRV_MASK, i); + + debug("%s: setting drive strength of pin %s to %d\n", __func__, priv->pins[pin_selector].name, drv_tbl[i]); + writel(reg, pin_reg); + + return 0; +} + +static int histb_pinctrl_pinconf_set(struct udevice *dev, unsigned int pin_selector, + unsigned int param, unsigned int argument) +{ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + return histb_pinctrl_set_bias(dev, pin_selector, BIAS_DISABLE); + case PIN_CONFIG_BIAS_PULL_UP: + return histb_pinctrl_set_bias(dev, pin_selector, BIAS_PULL_UP); + case PIN_CONFIG_BIAS_PULL_DOWN: + return histb_pinctrl_set_bias(dev, pin_selector, BIAS_PULL_DOWN); + case PIN_CONFIG_SLEW_RATE: + return histb_pinctrl_set_slew_rate(dev, pin_selector, argument); + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + return histb_pinctrl_set_schmitt(dev, pin_selector, argument); + case PIN_CONFIG_DRIVE_STRENGTH: + return histb_pinctrl_set_drive_strength(dev, pin_selector, argument); + } + + dev_err(dev, "can't handle given config %d\n", param); + return -EINVAL; +} + +static int histb_pinctrl_get_pin_muxing(struct udevice *dev, unsigned int selector, + char *buf, int size) +{ + struct histb_pinctrl_priv *priv = dev_get_priv(dev); + const struct histb_pin_mux_desc *desc = priv->pins[selector].func_tbl; + u32 reg = readl((u32 *)priv->base + priv->pins[selector].number); + bool found = false; + int current; + + current = FIELD_GET(HISTB_PIN_FUNC_MASK, reg); + + while (desc->name) { + if (desc->bits == current) { + strlcpy(buf, desc->name, size); + found = true; + break; + } + desc++; + } + + if (!found) { + dev_warn(dev, "unknown pinmux selected\n"); + strcpy(buf, "UNKNOWN!"); + } + + return 0; +} + +const struct pinctrl_ops histb_pinctrl_ops = { + .get_pins_count = histb_pinctrl_get_pins_count, + .get_pin_name = histb_pinctrl_get_pin_name, + .get_functions_count = histb_pinctrl_get_functions_count, + .get_function_name = histb_pinctrl_get_function_name, + .pinmux_set = histb_pinctrl_pinmux_set, + .pinconf_num_params = ARRAY_SIZE(histb_pinctrl_pinconf_params), + .pinconf_params = histb_pinctrl_pinconf_params, + .pinconf_set = histb_pinctrl_pinconf_set, + .set_state = pinctrl_generic_set_state, + .get_pin_muxing = histb_pinctrl_get_pin_muxing, +}; + +int histb_pinctrl_of_to_plat(struct udevice *dev) +{ + struct histb_pinctrl_priv *priv = (void *)dev_get_driver_data(dev); + + priv->base = dev_remap_addr(dev); + if (!priv->base) { + dev_err(dev, "failed to remap addr\n"); + return -EINVAL; + } + + dev_set_priv(dev, priv); + + return 0; +} diff --git a/drivers/pinctrl/hisilicon/pinctrl-histb.h b/drivers/pinctrl/hisilicon/pinctrl-histb.h new file mode 100644 index 0000000000..6169534139 --- /dev/null +++ b/drivers/pinctrl/hisilicon/pinctrl-histb.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <dm/pinctrl.h> +#include <linux/bitops.h> + +/* per-register bit definition */ +#define HISTB_PIN_SCHMITT BIT(14) +#define HISTB_PIN_PULLDOWN BIT(13) +#define HISTB_PIN_PULLUP BIT(12) +#define HISTB_PIN_SLEWRATE BIT(8) +#define HISTB_PIN_DRV_MASK GENMASK(7, 4) +#define HISTB_PIN_FUNC_MASK GENMASK(2, 0) + +/** + * @histb_pin_desc flags + * + * @HISTB_PIN_FLAG_NOPU: This pin does not support "bias-pullup" + * @HISTB_PIN_FLAG_NOPD: This pin does not support "bias-pulldown" + * @HISTB_PIN_FLAG_NOSR: This pin does not support "slew-rate" + * @HISTB_PIN_FLAG_HAS_SCHMITT: This pin supports setting schmitt + */ +#define HISTB_PIN_FLAG_NOPU BIT(0) +#define HISTB_PIN_FLAG_NOPD BIT(1) +#define HISTB_PIN_FLAG_NOSR BIT(2) +#define HISTB_PIN_FLAG_HAS_SCHMITT BIT(3) + +/** + * histb_pin_mux_desc - a descriptor for one function of a pin. + * + * @name: the name of the function, in capital + * @bits: the bits pattern for this function + */ +struct histb_pin_mux_desc { + const char *name; + u32 bits; +}; + +/** + * histb_pin_desc - a descriptor for a pin + * + * @number: ID for this pin, also used as offset into device address space + * @name: pin name, e.g. "F17", refer to the datasheet for detail + * @drv_tbl: (Optional) drive strength table, end with 0. The index is used as bits pattern. fill + * NULL if setting drive strength is not supported. + * @func_tbl: pinmux function table, end with { }. + * @flags: pin flags (use HISTB_PIN_FLAG_* constants) + */ +struct histb_pin_desc { + unsigned int number; + const char *name; + const u8 *drv_tbl; + const struct histb_pin_mux_desc *func_tbl; + int flags; +}; + +/** + * HISTB_PIN() - a helper for initializing struct histb_pin_desc + */ +#define HISTB_PIN(_index, _name, _drv_tbl, _func_tbl, _flag) { \ + .number = _index, \ + .name = _name, \ + .drv_tbl = _drv_tbl, \ + .func_tbl = _func_tbl, \ + .flags = _flag, \ +} + +/** + * histb_pin_func_setup_entry - an entry for setting up a function for a pin + * + * @pin_selector: pin ID + * @mask: function bit pattern + */ +struct histb_pin_func_setup_entry { + unsigned int pin_selector; + u8 mask; +}; + +/** + * histb_pin_function_desc - a descriptor for a function + * + * @func_selector: function selector + * @name: function name + * @pins_num: the number of pins engaged in this function + * @cfg_tbl: config table + */ +struct histb_pin_function_desc { + unsigned int func_selector; + const char *name; + unsigned int pins_num; + const struct histb_pin_func_setup_entry *cfg_tbl; +}; + +/** + * HISTB_PIN_FUNC - a helper macro to setup a function + */ +#define HISTB_PIN_FUNC(_id, _name, _cfg) { \ + .func_selector = _id, \ + .name = _name, \ + .pins_num = ARRAY_SIZE(_cfg), \ + .cfg_tbl = _cfg, \ +} + +/** + * histb_pinctrl_priv - private data for the driver + * + * @base: device base address + * @pins: descriptor array for all pins + * @funcs: descriptor array for all functions + * @pin_nums: array size of .pins + * @func_nums: array size of .funcs + */ +struct histb_pinctrl_priv { + void __iomem *base; + const struct histb_pin_desc *pins; + const struct histb_pin_function_desc *funcs; + unsigned int pin_nums; + unsigned int func_nums; +}; + +/** + * histb_pinctrl_of_to_plat - convert device tree node to private data + * + * use this function as .of_to_plat field in the driver + */ +int histb_pinctrl_of_to_plat(struct udevice *dev); + +/** + * histb_pinctrl_ops - HiSTB pinctrl ops + * + * use this struct as .ops field in the driver + */ +extern const struct pinctrl_ops histb_pinctrl_ops; --- base-commit: 050a9b981d6a835133521b599be3ae189ce70f41 change-id: 20240204-pinctrl-3a126ad9286e Best regards, -- Yang Xiwen <forbidden405(a)outlook.com>

3 4

[PATCH] doc/develop/codingstyle.rst: Clarify include section
by Tom Rini 12 Feb '24

12 Feb '24

Rework the section about includes slightly. We should not be using common.h anywhere, so remove that from examples and ask people to send patches removing it when found. Doing this also means we need to reword other parts of this section. Be clearer about using alphabetical ordering. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- doc/develop/codingstyle.rst | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/doc/develop/codingstyle.rst b/doc/develop/codingstyle.rst index b25bfbd271f0..cdf5aedfcbb0 100644 --- a/doc/develop/codingstyle.rst +++ b/doc/develop/codingstyle.rst @@ -108,30 +108,29 @@ expected size, or that particular members appear at the right offset. Include files ------------- -You should follow this ordering in U-Boot. The common.h header (which is going -away at some point) should always be first, followed by other headers in order, -then headers with directories, then local files: +You should follow this ordering in U-Boot. In all cases, they should be listed +in alphabetical order. First comes headers which are located directly in our +top-level include diretory. This excludes the common.h header file which is to +be removed. Second are headers within subdirectories, Finally directory-local +includes should be listed. See this example: .. code-block:: C - #include <common.h> #include <bootstage.h> #include <dm.h> #include <others.h> #include <asm/...> - #include <arm/arch/...> + #include <asm/arch/...> #include <dm/device_compat.h> #include <linux/...> #include "local.h" -Within that order, sort your includes. - -It is important to include common.h first since it provides basic features used -by most files, e.g. CONFIG options. - For files that need to be compiled for the host (e.g. tools), you need to use -``#ifndef USE_HOSTCC`` to avoid including common.h since it includes a lot of -internal U-Boot things. See common/image.c for an example. +``#ifndef USE_HOSTCC`` to avoid including U-Boot specific include files. See +common/image.c for an example. + +If you encounter ccode which still uses <common.h> a patch to remove that and +replace it with any required include files directly is much appreciated. If your file uses driver model, include <dm.h> in the C file. Do not include dm.h in a header file. Try to use forward declarations (e.g. ``struct -- 2.34.1

3 4

Pull request: Please pull u-boot-imx-master-20240212
by Fabio Estevam 12 Feb '24

12 Feb '24

Hi Tom, Please pull from u-boot-imx, thanks. The following changes since commit d7aaaf4223d0a2f9f8c9eed47d7431860b3116d8: Merge tag 'u-boot-dfu-20240209' of https://source.denx.de/u-boot/custodians/u-boot-dfu (2024-02-09 09:00:42 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git tags/u-boot-imx-master-20240212 for you to fetch changes up to fcd377ed6480643b1f79188c7a8fb9280a211b4f: configs: imx93_var_som: Enable AHAB support (2024-02-10 15:16:13 -0300) u-boot-imx-master-20240212 -------------------------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/19583 - Fix the i.MX8MP SPI compatible string. - Let the SPL clock code do the configuration on Data Modul i.MX8M Plus eDM SBC. - Enable secure boot on the imx93_var_som board. ---------------------------------------------------------------- Marek Vasut (2): ARM: imx: Let SPL configure ECSPI1 clock on Data Modul i.MX8M Plus eDM SBC spi: mxc_spi: Add imx6ul-ecspi compatible string Mathieu Othacehe (3): imx93: Use a header for imx9_probe_mu declaration board: imx93_var_som: Probe ELE MU configs: imx93_var_som: Enable AHAB support arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi | 3 +++ arch/arm/include/asm/arch-imx9/mu.h | 13 +++++++++++++ board/freescale/imx93_evk/spl.c | 2 +- board/phytec/phycore_imx93/spl.c | 2 +- board/variscite/imx93_var_som/spl.c | 5 +++-- configs/imx93_var_som_defconfig | 1 + drivers/spi/mxc_spi.c | 1 + 7 files changed, 23 insertions(+), 4 deletions(-) create mode 100644 arch/arm/include/asm/arch-imx9/mu.h

2 1

[PATCH 1/1] efi_driver: provide SBI based runtime system reset
by Heinrich Schuchardt 12 Feb '24

12 Feb '24

On RISC-V systems system the Supervisory Binary Interface provides system reset and poweroff. Use it at EFI runtime. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- lib/efi_driver/Makefile | 1 + lib/efi_driver/efi_reset_riscv.c | 29 +++++++++++++++++++++++++++++ lib/efi_loader/Kconfig | 2 +- 3 files changed, 31 insertions(+), 1 deletion(-) create mode 100644 lib/efi_driver/efi_reset_riscv.c diff --git a/lib/efi_driver/Makefile b/lib/efi_driver/Makefile index f2b6c05cc24..0da20fe91d3 100644 --- a/lib/efi_driver/Makefile +++ b/lib/efi_driver/Makefile @@ -9,3 +9,4 @@ obj-y += efi_uclass.o ifeq ($(CONFIG_PARTITIONS),y) obj-y += efi_block_device.o endif +obj-$(CONFIG_SYSRESET_SBI) += efi_reset_riscv.o diff --git a/lib/efi_driver/efi_reset_riscv.c b/lib/efi_driver/efi_reset_riscv.c new file mode 100644 index 00000000000..89b23522e95 --- /dev/null +++ b/lib/efi_driver/efi_reset_riscv.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include <efi_loader.h> +#include <asm/sbi.h> + +void __efi_runtime EFIAPI efi_reset_system(enum efi_reset_type reset_type, + efi_status_t reset_status, + unsigned long data_size, + void *reset_data) +{ + register unsigned long eid asm("a7") = SBI_EXT_SRST; + register unsigned long fid asm("a6") = SBI_EXT_SRST_RESET; + register unsigned long type asm("a0"); + register unsigned long reason asm("a1") = SBI_SRST_RESET_REASON_NONE; + + switch (reset_type) { + case EFI_RESET_WARM: + type = SBI_SRST_RESET_TYPE_WARM_REBOOT; + break; + case EFI_RESET_SHUTDOWN: + type = SBI_SRST_RESET_TYPE_SHUTDOWN; + break; + default: + type = SBI_SRST_RESET_TYPE_COLD_REBOOT; + break; + } + asm volatile ("ecall\n" + : : "r" (eid), "r" (fid), "r" (type), "r" (reason)); +} diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index db5571de1d9..a7c3e05c13a 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -366,7 +366,7 @@ config EFI_HAVE_RUNTIME_RESET bool default y depends on ARCH_BCM283X || FSL_LAYERSCAPE || PSCI_RESET || \ - SANDBOX || SYSRESET_X86 + SANDBOX || SYSRESET_SBI || SYSRESET_X86 config EFI_GRUB_ARM32_WORKAROUND bool "Workaround for GRUB on 32bit ARM" -- 2.43.0

1 0

[PATCH v2 00/20] rockchip: add support for Theobroma JAGUAR SBC-RK3588-AMR
by Quentin Schulz 12 Feb '24

12 Feb '24

This adds all the necessary bits for adding support for Theobroma's new SBC. JAGUAR is a Single-Board Computer (SBC) based around the rk3588 SoC and is targeting Autonomous Mobile Robots (AMR). It features: * LPDDR4X (up to 16GB) * 1Gbps Ethernet on RJ45 connector (KSZ9031 or KSZ9131) * PCIe 3.0 4-lane on M.2 M-key connector * PCIe 2.1 1-lane on M.2 E-key * USB 2.0 on M.2 E-key * 2x USB3 OTG type-c ports with DP Alt-Mode * USB2 host port * HDMI output * 2x camera connectors, each exposing: * 2-lane MIPI-CSI * 1v2, 1v8, 2v8 power rails * I2C bus * GPIOs * PPS input * CAN * RS485 UART * FAN connector * SD card slot * eMMC (up to 256GB) * RTC backup battery * Companion microcontroller * ISL1208 RTC emulation * AMC6821 PWM emulation * On/off buzzer control * Secure Element * 80-pin Mezzanine connector for daughterboards: * GPIOs * 1Gbps Ethernet * PCIe 2.1 1-lane * 2x 2-lane MIPI-CSI * ADC channel * I2C bus * PWM * UART * SPI * SDIO * CAN * I2S * 1v8, 3v3, 5v0, dc-in (12-24V) power rails While at it, do some code cleanup and factoring out for Rockchip SoCs. This also fixes issues with the SDMMC controller on all RK3588 boards being muxed into JTAG automatically and breaking SD card support. This also binds the MMC controllers from RK3588 in U-Boot proper before relocation so that it's available for env_init(), be there any need for it (there's for Theobroma's RK3588 based products), and match all (except the RK356x family) Rockchip SoCs behavior. Special attention should be brought to the rockchip_early_misc_init_r migration for Pinephone Pro and Pinebook Pro since they now also call rockchip_setup_macaddr() which they didn't until now. This also do a few non-code changes for Ringneck PX30 and Puma RK3399. Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- Changes in v2: - added missing dtb Make target in arch/arm/dts/Makefile - added some Rb - reworded some commit logs - fixed typo in pinebook/pinephone commits missing the -pro suffix - added removal of DDR52 and HS mode for eMMC following discussions from https://lore.kernel.org/u-boot/20240204205312.2342868-1-jonas@kwiboo.se/ - migrated plaintext board/theobroma-systems/jaguar_rk3588/README from earlier version to doc/board/theobroma-systems/jaguar_rk3588.rst in rST format - added commit for migration of plaintext board/theobroma-systems/puma_rk3399/README to doc/board/theobroma-systems/puma_rk3399.rst in rST format - added commit for migration of plaintext board/theobroma-systems/ringneck_px30/README to doc/board/theobroma-systems/ringneck_px30.rst in rST format - updated DTS in MAINTAINERS entry for Puma to match all Puma DTSes - updated product URL in ringneck's MAINTAINERS entry to work around HTTP404 - Link to v1: https://lore.kernel.org/r/20240123-jaguar-v1-0-1eec1c34953c@theobroma-syste… --- Quentin Schulz (20): rockchip: avoid out-of-bounds when computing cpuid rockchip: add weak function symbol called at the beginning of misc_init_r rockchip: google: gru: migrate to rockchip_early_misc_init_r rockchip: pine64: pinebook-pro: migrate to rockchip_early_misc_init_r rockchip: pine64: pinephone-pro: migrate to rockchip_early_misc_init_r rockchip: pine64: rockpro64: migrate to rockchip_early_misc_init_r rockchip: theobroma-systems: puma: migrate to rockchip_early_misc_init_r rockchip: theobroma-systems: ringneck: migrate to rockchip_early_misc_init_r rockchip: merge misc.c into board.c rockchip: transform rockchip_capsule_update_board_setup into a weak function symbol rockchip: rk3588: fix non-working SD controller if booting from other media rockchip: rk3588: add constants for some register address spaces rockchip: migrate hardware.h inclusion into appropriate files rockchip: include asm/io.h directly in asm/arch-rockchip/hardware.h rockchip: rk3588: bind MMC controllers in U-Boot proper pre-reloc board: rockchip: add Theobroma-Systems RK3588 Jaguar SBC rockchip: puma-rk3399: MAINTAINERS: use glob for dtses rockchip: rk3399-puma: migrate README to doc/board in rST format rockchip: ringneck_px30: migrate README to doc/board in rST format rockchip: ringneck_px30: update website link arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3588-jaguar-u-boot.dtsi | 38 + arch/arm/dts/rk3588-jaguar.dts | 803 +++++++++++++++++++++ arch/arm/dts/rk3588s-u-boot.dtsi | 4 +- arch/arm/include/asm/arch-rockchip/cru_rk3588.h | 2 + arch/arm/include/asm/arch-rockchip/grf_rk3588.h | 24 + arch/arm/include/asm/arch-rockchip/hardware.h | 2 + arch/arm/include/asm/arch-rockchip/ioc_rk3588.h | 6 + arch/arm/include/asm/arch-rockchip/misc.h | 14 - arch/arm/mach-rockchip/Makefile | 1 - arch/arm/mach-rockchip/board.c | 139 +++- arch/arm/mach-rockchip/cpu-info.c | 1 - arch/arm/mach-rockchip/misc.c | 135 ---- arch/arm/mach-rockchip/px30/px30.c | 1 - arch/arm/mach-rockchip/rk3036/rk3036.c | 1 - arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 1 - arch/arm/mach-rockchip/rk3066/rk3066.c | 2 +- arch/arm/mach-rockchip/rk3188/rk3188.c | 1 - arch/arm/mach-rockchip/rk322x/rk322x.c | 1 - arch/arm/mach-rockchip/rk3288/rk3288.c | 1 - arch/arm/mach-rockchip/rk3308/rk3308.c | 1 - arch/arm/mach-rockchip/rk3328/rk3328.c | 1 - arch/arm/mach-rockchip/rk3368/rk3368.c | 1 - arch/arm/mach-rockchip/rk3399/rk3399.c | 1 - arch/arm/mach-rockchip/rk3568/rk3568.c | 1 - arch/arm/mach-rockchip/rk3588/Kconfig | 28 + arch/arm/mach-rockchip/rk3588/rk3588.c | 12 +- arch/arm/mach-rockchip/rv1126/rv1126.c | 1 - board/elgin/elgin_rv1108/elgin_rv1108.c | 1 - board/firefly/firefly-rk3308/roc_cc_rk3308.c | 1 - board/google/gru/gru.c | 21 +- .../pinebook-pro-rk3399/pinebook-pro-rk3399.c | 19 +- .../pinephone-pro-rk3399/pinephone-pro-rk3399.c | 18 +- board/pine64/rockpro64_rk3399/rockpro64-rk3399.c | 21 +- board/rockchip/evb_rv1108/evb_rv1108.c | 1 - board/theobroma-systems/jaguar_rk3588/Kconfig | 16 + board/theobroma-systems/jaguar_rk3588/MAINTAINERS | 13 + board/theobroma-systems/jaguar_rk3588/Makefile | 10 + .../jaguar_rk3588/jaguar_rk3588.c | 52 ++ board/theobroma-systems/puma_rk3399/MAINTAINERS | 3 +- board/theobroma-systems/puma_rk3399/README | 90 +-- board/theobroma-systems/puma_rk3399/puma-rk3399.c | 21 +- board/theobroma-systems/ringneck_px30/MAINTAINERS | 3 +- board/theobroma-systems/ringneck_px30/README | 70 +- .../ringneck_px30/ringneck-px30.c | 20 +- board/vamrs/rock960_rk3399/rock960-rk3399.c | 1 - configs/jaguar-rk3588_defconfig | 115 +++ doc/board/index.rst | 1 + doc/board/rockchip/rockchip.rst | 1 + doc/board/theobroma-systems/index.rst | 11 + doc/board/theobroma-systems/jaguar_rk3588.rst | 100 +++ doc/board/theobroma-systems/puma_rk3399.rst | 126 ++++ doc/board/theobroma-systems/ringneck_px30.rst | 95 +++ drivers/clk/rockchip/clk_pll.c | 1 - drivers/clk/rockchip/clk_px30.c | 1 - drivers/clk/rockchip/clk_rk3036.c | 1 - drivers/clk/rockchip/clk_rk3066.c | 1 - drivers/clk/rockchip/clk_rk3128.c | 1 - drivers/clk/rockchip/clk_rk3188.c | 1 - drivers/clk/rockchip/clk_rk322x.c | 1 - drivers/clk/rockchip/clk_rk3288.c | 1 - drivers/clk/rockchip/clk_rk3308.c | 1 - drivers/clk/rockchip/clk_rk3328.c | 1 - drivers/clk/rockchip/clk_rk3368.c | 1 - drivers/clk/rockchip/clk_rk3399.c | 1 - drivers/clk/rockchip/clk_rk3568.c | 1 - drivers/clk/rockchip/clk_rk3588.c | 1 - drivers/clk/rockchip/clk_rv1108.c | 1 - drivers/clk/rockchip/clk_rv1126.c | 1 - drivers/gpio/rk_gpio.c | 1 - drivers/net/gmac_rockchip.c | 1 - drivers/ram/rockchip/dmc-rk3368.c | 2 +- drivers/ram/rockchip/sdram_px30.c | 1 - drivers/ram/rockchip/sdram_rk3066.c | 1 - drivers/ram/rockchip/sdram_rk3188.c | 2 +- drivers/ram/rockchip/sdram_rk322x.c | 1 - drivers/ram/rockchip/sdram_rk3288.c | 2 +- drivers/ram/rockchip/sdram_rk3399.c | 1 - drivers/ram/rockchip/sdram_rv1126.c | 1 - drivers/rng/rockchip_rng.c | 1 - drivers/sysreset/sysreset_rockchip.c | 1 - drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 1 - drivers/video/rockchip/rk3288_hdmi.c | 1 - drivers/video/rockchip/rk3288_mipi.c | 1 - drivers/video/rockchip/rk3288_vop.c | 1 - drivers/video/rockchip/rk3399_hdmi.c | 1 - drivers/video/rockchip/rk3399_mipi.c | 1 - drivers/video/rockchip/rk3399_vop.c | 1 - drivers/video/rockchip/rk_edp.c | 1 - drivers/video/rockchip/rk_hdmi.c | 1 - drivers/video/rockchip/rk_lvds.c | 1 - include/configs/jaguar_rk3588.h | 15 + include/configs/rk3036_common.h | 1 - include/configs/rk3066_common.h | 1 - include/configs/rk3188_common.h | 1 - include/configs/rk322x_common.h | 1 - include/configs/rk3288_common.h | 1 - include/configs/rk3368_common.h | 1 - include/configs/rv1108_common.h | 1 - 99 files changed, 1626 insertions(+), 491 deletions(-) --- base-commit: a4650bf65e4b7d3ef04c90ba8031374428e4a682 change-id: 20240123-jaguar-efd00e57f56c Best regards, -- Quentin Schulz <quentin.schulz(a)theobroma-systems.com>

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[PATCH 0/4] rockchip: Read cpuid and generate MAC address from efuse for RK3328 and RK3399
by Chen-Yu Tsai 12 Feb '24

12 Feb '24

From: Chen-Yu Tsai <wens(a)csie.org> Hi folks, This series enables ROCKCHIP_EFUSE and MISC_INIT_R by default for RK3328 and RK3399 so that the cpuid is read from the efuse and used to generate a serial number and MAC addresses for all boards. This stacks on top of the recent defconfig update series [1] from Jonas. [1] https://lore.kernel.org/u-boot/20240207000301.3270722-1-jonas@kwiboo.se/ Chen-Yu Tsai (4): rockchip: rk3328: Read cpuid and generate MAC address from efuse rockchip: rk3399: Read cpuid and generate MAC address from efuse rockchip: rk3328: regenerate defconfigs rockchip: rk3399: regenerate defconfigs arch/arm/mach-rockchip/Kconfig | 4 ++++ configs/chromebook_bob_defconfig | 2 -- configs/chromebook_kevin_defconfig | 2 -- configs/evb-rk3328_defconfig | 2 -- configs/firefly-rk3399_defconfig | 2 -- configs/nanopi-r2c-plus-rk3328_defconfig | 2 -- configs/nanopi-r2c-rk3328_defconfig | 2 -- configs/nanopi-r2s-rk3328_defconfig | 2 -- configs/nanopi-r4s-rk3399_defconfig | 2 -- configs/orangepi-r1-plus-lts-rk3328_defconfig | 2 -- configs/orangepi-r1-plus-rk3328_defconfig | 2 -- configs/pinebook-pro-rk3399_defconfig | 2 -- configs/pinephone-pro-rk3399_defconfig | 2 -- configs/puma-rk3399_defconfig | 2 -- configs/roc-cc-rk3328_defconfig | 2 -- configs/roc-pc-mezzanine-rk3399_defconfig | 2 -- configs/roc-pc-rk3399_defconfig | 2 -- configs/rock-4c-plus-rk3399_defconfig | 3 --- configs/rock-4se-rk3399_defconfig | 3 --- configs/rock-pi-4-rk3399_defconfig | 3 --- configs/rock-pi-4c-rk3399_defconfig | 3 --- configs/rock-pi-e-rk3328_defconfig | 2 -- configs/rock-pi-n10-rk3399pro_defconfig | 1 - configs/rock64-rk3328_defconfig | 2 -- configs/rock960-rk3399_defconfig | 1 - configs/rockpro64-rk3399_defconfig | 2 -- 26 files changed, 4 insertions(+), 52 deletions(-) -- 2.39.2

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