February 2024 - U-Boot

[PATCH] arm: dts: k3-binman: Make optee optional as requirement
by Michael Trimarchi 26 Feb '24

26 Feb '24

Boards can use the ti_spl_template but avoid to define a tee node to be loaded. This is true form board with 512Mb or less memory. We can limit this in configuation removing the tee node configurations { default = "conf-0"; conf-0 { description = "k3-am62_ccm_m3"; firmware = "atf"; loadables = "dm", "spl"; fdt = "fdt-0"; }; }; Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> --- arch/arm/dts/k3-binman.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/k3-binman.dtsi b/arch/arm/dts/k3-binman.dtsi index 758c8bf6ea..5ef5af315a 100644 --- a/arch/arm/dts/k3-binman.dtsi +++ b/arch/arm/dts/k3-binman.dtsi @@ -293,6 +293,7 @@ keyfile = "custMpk.pem"; }; tee: tee-os { + optional; }; }; @@ -360,6 +361,7 @@ entry = <0x9e800000>; tee-os { filename = "tee-raw.bin"; + optional; }; }; -- 2.40.1

3 2

[PATCH v1 1/1] arch:arm: Agilex5 enablement
by Jit Loon Lim 26 Feb '24

26 Feb '24

This patch is to enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- arch/arm/Kconfig | 9 +- arch/arm/dts/Makefile | 32 +---- .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 11 +- arch/arm/dts/socfpga_agilex5_socdk.dts | 67 +--------- arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 2 +- arch/arm/mach-socfpga/Kconfig | 125 +++++------------- arch/arm/mach-socfpga/Makefile | 99 +------------- arch/arm/mach-socfpga/board.c | 2 - .../include/mach/base_addr_soc64.h | 16 +-- board/intel/agilex5-socdk/MAINTAINERS | 2 + board/intel/agilex5-socdk/Makefile | 2 +- board/intel/agilex5-socdk/socfpga.c | 2 +- configs/socfpga_agilex5_defconfig | 33 ----- include/configs/socfpga_agilex5_socdk.h | 2 +- include/configs/socfpga_soc64_common.h | 40 +----- 15 files changed, 63 insertions(+), 381 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 43d5ad346f..c8d91669da 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -28,7 +28,7 @@ config COUNTER_FREQUENCY ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A default 100000000 if ARCH_ZYNQMP - default 400000000 if ARCH_SOCFPGA && ARM64 + default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5 default 0 help For platforms with ARMv8-A and ARMv7-A which features a system @@ -1088,14 +1088,14 @@ config ARCH_SNAPDRAGON select SPMI imply CMD_DM -config ARCH_SOCFPGA - bool "Altera SOCFPGA family" +bool "Altera SOCFPGA family" select ARCH_EARLY_INIT_R select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 select ARM64 if TARGET_SOCFPGA_SOC64 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select DM select DM_SERIAL + select GICV2 select GPIO_EXTRA_HEADER select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select OF_CONTROL @@ -1109,7 +1109,7 @@ config ARCH_SOCFPGA select SPL_SOCFPGA_SEC_REG if TARGET_SOCFPGA_SOC64 select SPL_SERIAL select SPL_SYSRESET - select SPL_WATCHDOG + select SPL_WATCHDOG if !TARGET_SOCFPGA_AGILEX5 select SUPPORT_SPL select SYS_NS16550 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 @@ -1123,6 +1123,7 @@ config ARCH_SOCFPGA imply DM_SPI imply DM_SPI_FLASH imply FAT_WRITE + imply MTD imply SPL imply SPL_DM imply SPL_DM_SPI diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 90d933a9ae..646f4feaf7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -543,37 +543,7 @@ dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ - socfpga_agilex_n6010.dtb \ - socfpga_agilex_socdk.dtb \ - socfpga_agilex_socdk_nand.dtb \ - socfpga_agilex_socdk_qspi.dtb \ - socfpga_agilex5_socdk.dtb \ - socfpga_agilex5_emu.dtb \ - socfpga_agilex7m_socdk.dtb \ - socfpga_agilex7m_socdk_nand.dtb \ - socfpga_arria5_secu1.dtb \ - socfpga_arria5_socdk.dtb \ - socfpga_arria10_chameleonv3_270_2.dtb \ - socfpga_arria10_chameleonv3_270_3.dtb \ - socfpga_arria10_chameleonv3_480_2.dtb \ - socfpga_arria10_socdk_nand.dtb \ - socfpga_arria10_socdk_qspi.dtb \ - socfpga_arria10_socdk_sdmmc.dtb \ - socfpga_cyclone5_mcvevk.dtb \ - socfpga_cyclone5_is1.dtb \ - socfpga_cyclone5_socdk.dtb \ - socfpga_cyclone5_dbm_soc1.dtb \ - socfpga_cyclone5_de0_nano_soc.dtb \ - socfpga_cyclone5_de1_soc.dtb \ - socfpga_cyclone5_de10_nano.dtb \ - socfpga_cyclone5_sockit.dtb \ - socfpga_cyclone5_socrates.dtb \ - socfpga_cyclone5_sr1500.dtb \ - socfpga_cyclone5_vining_fpga.dtb \ - socfpga_n5x_socdk.dtb \ - socfpga_stratix10_socdk.dtb \ - socfpga_stratix10_socdk_nand.dtb \ - socfpga_stratix10_socdk_qspi.dtb + socfpga_agilex5_socdk.dtb dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi index 5da93576c2..28e1c140c2 100755 --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -2,7 +2,7 @@ /* * U-Boot additions * - * Copyright (C) 2022-2023 Intel Corporation <www.intel.com> + * Copyright (C) 2024 Intel Corporation <www.intel.com> */ #include "socfpga_agilex5-u-boot.dtsi" @@ -14,16 +14,17 @@ }; soc { - freeze_controller: freeze_controller@f9000450 { + freeze_controller: freeze_controller@0x20000450 { compatible = "altr,freeze-bridge-controller"; - reg = <0xf9000450 0x00000010>; + reg = <0x20000450 0x00000010>; status = "disabled"; }; }; memory { - /* 2GB on Simics*/ - reg = <0 0x80000000 0 0x80000000>; + /* 8GB */ + reg = <0 0x80000000 0 0x80000000>, + <8 0x80000000 1 0x80000000>; }; chosen { diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts index b90b869e5a..c5d7352b75 100755 --- a/arch/arm/dts/socfpga_agilex5_socdk.dts +++ b/arch/arm/dts/socfpga_agilex5_socdk.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019-2023 Intel Corporation <www.intel.com> + * Copyright (C) 2024 Intel Corporation <www.intel.com> */ #include "socfpga_agilex5.dtsi" @@ -70,14 +70,6 @@ status = "okay"; }; -&mmc { - status = "okay"; -}; - -&combophy0 { - status = "okay"; -}; - &uart0 { status = "okay"; }; @@ -91,10 +83,6 @@ disable-over-current; }; -&usb31 { - status = "okay"; -}; - &watchdog0 { status = "okay"; }; @@ -139,25 +127,6 @@ status = "okay"; }; -&nand { - status = "okay"; - - flash1: flash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0 0x200000>; - }; - partition@200000 { - label = "root"; - reg = <0x200000 0x3fe00000>; - }; - }; -}; - &qspi { flash0: flash@0 { #address-cells = <1>; @@ -192,37 +161,3 @@ }; }; }; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&emac0_phy0>; - - max-frame-size = <9000>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwxgmac-mdio"; - emac0_phy0: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&emac2_phy0>; - - max-frame-size = <9000>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwxgmac-mdio"; - emac2_phy0: ethernet-phy@1 { - reg = <1>; - }; - }; -}; diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi index ddadde874d..7a5af489c5 100644 --- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi @@ -2,7 +2,7 @@ /* * U-Boot additions * - * Copyright (C) 2020-2023 Intel Corporation <www.intel.com> + * Copyright (C) 2024 Intel Corporation <www.intel.com> */ #if defined(CONFIG_FIT) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 622ac7861c..ba012e226d 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -6,24 +6,6 @@ config ERR_PTR_OFFSET config NR_DRAM_BANKS default 1 -config SOCFPGA_RSU_MULTIBOOT - bool "Enable RSU Multiboot Selection Feature" - depends on TARGET_SOCFPGA_SOC64 && SPI_FLASH - default n - help - Multiboot u-boot proper image (SSBL) selection feature for RSU. - SPL will select the respective SSBL based on the partition it resides - inside RSU QSPI flash layout. - -config SOCFPGA_RSU_MULTIFLASH - bool "Enable RSU Multiflash Feature" - depends on TARGET_SOCFPGA_SOC64 && SPI_FLASH - default n - help - Multiflash selection feature for RSU. - RSU will be able to perform operations on multiple flash on the platform - given multiple flash configuration in programmer tool. - config SOCFPGA_SECURE_VAB_AUTH bool "Enable boot image authentication with Secure Device Manager" depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X || TARGET_SOCFPGA_AGILEX5 @@ -48,6 +30,9 @@ config SPL_SIZE_LIMIT_PROVIDE_STACK config SPL_STACK_R_ADDR default 0x00800000 if TARGET_SOCFPGA_GEN5 +config SPL_SYS_MALLOC_F + default y if TARGET_SOCFPGA_GEN5 + config SPL_SYS_MALLOC_F_LEN default 0x800 if TARGET_SOCFPGA_GEN5 @@ -62,15 +47,6 @@ config TEXT_BASE default 0x01000040 if TARGET_SOCFPGA_ARRIA10 default 0x01000040 if TARGET_SOCFPGA_GEN5 -config ARMV8_PSCI_NR_CPUS - default 4 if TARGET_SOCFPGA_SOC64 - -config ARMV8_SECURE_BASE - default 0x00001000 if TARGET_SOCFPGA_SOC64 && ARMV8_PSCI - -config SYS_HAS_ARMV8_SECURE_BASE - default y if TARGET_SOCFPGA_SOC64 && ARMV8_PSCI - config TARGET_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY @@ -92,39 +68,31 @@ config TARGET_SOCFPGA_AGILEX5 select NCORE_CACHE select SPL_CLK if SPL select TARGET_SOCFPGA_SOC64 +config TARGET_SOCFPGA_AGILEX5_OOBE2 + bool "Enable build that bootable only on Agilex5 OOBE2 DevKit" -config TARGET_SOCFPGA_AGILEX7 - bool - select ARMV8_MULTIENTRY - select ARMV8_SET_SMPEN - select BINMAN if SPL_ATF - select CLK - select FPGA_INTEL_SDM_MAILBOX - select GICV2 - select NCORE_CACHE - select SPL_CLK if SPL - select TARGET_SOCFPGA_SOC64 +config TARGET_SOCFPGA_AGILEX5_NAND2 + bool "Enable build that bootable only on Agilex5 NAND2 DevKit" -config TARGET_SOCFPGA_AGILEX5_EMU - bool "Enable build that bootable only on Agilex5 Emulator" +config TARGET_SOCFPGA_AGILEX5_TSN_AIC0 + bool "Enable build that bootable only on Agilex5 TSN_PHY_AIC0 MuDV" -config TARGET_SOCFPGA_AGILEX5_SIMICS - bool "Enable build that bootable only on Agilex5 Simics platform" +config TARGET_SOCFPGA_AGILEX5_TSN_AIC1 + bool "Enable build that bootable only on Agilex5 TSN_PHY_AIC1 MuDV" +config TARGET_SOCFPGA_AGILEX5_TSN_AIC2 + bool "Enable build that bootable only on Agilex5 TSN_PHY_AIC2 MuDV" config TARGET_SOCFPGA_ARRIA5 bool select TARGET_SOCFPGA_GEN5 config TARGET_SOCFPGA_ARRIA10 bool - select GICV2 select SPL_ALTERA_SDRAM select SPL_BOARD_INIT if SPL select SPL_CACHE if SPL - select SPL_WDT if SPL select CLK select SPL_CLK if SPL - select DESIGNWARE_WATCHDOG select DM_I2C select DM_RESET select SPL_DM_RESET if SPL @@ -133,40 +101,16 @@ config TARGET_SOCFPGA_ARRIA10 select SYSCON select SPL_SYSCON if SPL select ETH_DESIGNWARE_SOCFPGA - select WDT imply FPGA_SOCFPGA + imply SPL_USE_TINY_PRINTF config TARGET_SOCFPGA_CYCLONE5 bool select TARGET_SOCFPGA_GEN5 -config TARGET_SOCFPGA_N5X - bool - select TARGET_SOCFPGA_SOC64 - select ARMV8_MULTIENTRY - select ARMV8_SET_SMPEN - select BINMAN if SPL_ATF - select CLK - select GICV2 - select NCORE_CACHE - select SPL_ALTERA_SDRAM - select SPL_CLK if SPL - -config TARGET_SOCFPGA_AGILEX_N6010 - bool "Intel SOCFPGA n6010 (Agilex)" - select TARGET_SOCFPGA_AGILEX - select BINMAN if !SPL_ATF - -config TARGET_SOCFPGA_N5X_SOCDK - bool "Intel SOCFPGA SoCDK (N5X)" - select TARGET_SOCFPGA_N5X - config TARGET_SOCFPGA_GEN5 bool - select GICV2 - select DESIGNWARE_WATCHDOG select SPL_ALTERA_SDRAM - select SPL_CACHE if SPL imply FPGA_SOCFPGA imply SPL_SIZE_LIMIT_SUBTRACT_GD imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC @@ -181,17 +125,11 @@ config TARGET_SOCFPGA_N5X select BINMAN if SPL_ATF select CLK select FPGA_INTEL_SDM_MAILBOX - select GICV2 select NCORE_CACHE select SPL_ALTERA_SDRAM select SPL_CLK if SPL select TARGET_SOCFPGA_SOC64 -config TARGET_SOCFPGA_AGILEX_N6010 - bool "Intel SOCFPGA n6010 (Agilex)" - select TARGET_SOCFPGA_AGILEX - select BINMAN if !SPL_ATF - config TARGET_SOCFPGA_N5X_SOCDK bool "Intel eASIC SoCDK (N5X)" select TARGET_SOCFPGA_N5X @@ -205,8 +143,25 @@ config TARGET_SOCFPGA_STRATIX10 select ARMV8_SET_SMPEN select BINMAN if SPL_ATF select FPGA_INTEL_SDM_MAILBOX - select FPGA_STRATIX10 - select GICV2 + select TARGET_SOCFPGA_SOC64 + +config ARMV8_PSCI_NR_CPUS + default 4 if TARGET_SOCFPGA_SOC64 + +config ARMV8_SECURE_BASE + default 0x00001000 if TARGET_SOCFPGA_SOC64 && ARMV8_PSCI + +config SYS_HAS_ARMV8_SECURE_BASE + default y if TARGET_SOCFPGA_SOC64 && ARMV8_PSCI + +config TARGET_SOCFPGA_AGILEX5 + bool + select BINMAN if SPL_ATF + select CLK + select FPGA_INTEL_SDM_MAILBOX + select GICV3 + select NCORE_CACHE + select SPL_CLK if SPL select TARGET_SOCFPGA_SOC64 choice @@ -221,10 +176,6 @@ config TARGET_SOCFPGA_AGILEX5_SOCDK bool "Intel SOCFPGA SoCDK (Agilex5)" select TARGET_SOCFPGA_AGILEX5 -config TARGET_SOCFPGA_AGILEX7_SOCDK - bool "Intel SOCFPGA SoCDK (Agilex7)" - select TARGET_SOCFPGA_AGILEX7 - config TARGET_SOCFPGA_ARIES_MCVEVK bool "Aries MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -298,9 +249,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT endchoice config SYS_BOARD - default "agilex7-socdk" if TARGET_SOCFPGA_AGILEX7_SOCDK default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK - default "agilex-n6010" if TARGET_SOCFPGA_AGILEX_N6010 default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK @@ -310,7 +259,6 @@ config SYS_BOARD default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO - default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK default "de10-standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD default "is1" if TARGET_SOCFPGA_IS1 default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK @@ -323,9 +271,7 @@ config SYS_BOARD default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA config SYS_VENDOR - default "intel" if TARGET_SOCFPGA_AGILEX7_SOCDK default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK - default "intel" if TARGET_SOCFPGA_AGILEX_N6010 default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK default "intel" if TARGET_SOCFPGA_N5X_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -348,9 +294,7 @@ config SYS_SOC default "socfpga" config SYS_CONFIG_NAME - default "socfpga_agilex7_socdk" if TARGET_SOCFPGA_AGILEX7_SOCDK default "socfpga_agilex5_socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK - default "socfpga_agilex_n6010" if TARGET_SOCFPGA_AGILEX_N6010 default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -361,7 +305,6 @@ config SYS_CONFIG_NAME default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO - default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK default "socfpga_de10_standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD default "socfpga_is1" if TARGET_SOCFPGA_IS1 default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK @@ -372,4 +315,4 @@ config SYS_CONFIG_NAME default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA -endif \ No newline at end of file +endif diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 575eab86ff..181bb01fdd 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -4,7 +4,7 @@ # Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. # # Copyright (C) 2012-2017 Altera Corporation <www.altera.com> -# Copyright (C) 2017-2023 Intel Corporation <www.intel.com> +# Copyright (C) 2017-2024 Intel Corporation <www.intel.com> obj-y += board.o obj-y += clock_manager.o @@ -35,22 +35,10 @@ obj-y += mailbox_s10.o obj-y += misc_soc64.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o -obj-y += smmu_s10.o obj-y += system_manager_soc64.o obj-y += timer_s10.o obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o -ifndef CONFIG_SPL_BUILD -obj-y += rsu.o -obj-y += rsu_ll_qspi.o -obj-y += rsu_misc.o -obj-y += rsu_s10.o -obj-$(CONFIG_ARMV8_PSCI) += psci.o -obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o -obj-$(CONFIG_ARMV8_PSCI) += smc_fpga_reconfig_s10.o -obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o -obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o -endif endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX @@ -61,72 +49,11 @@ obj-y += misc_soc64.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o -obj-y += smmu_s10.o -obj-y += system_manager_soc64.o -obj-y += timer_s10.o -obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o -obj-y += wrap_handoff_soc64.o -obj-y += wrap_pll_config_soc64.o -ifndef CONFIG_SPL_BUILD -obj-y += rsu.o -obj-y += rsu_ll_qspi.o -obj-y += rsu_misc.o -obj-y += rsu_s10.o -obj-$(CONFIG_ARMV8_PSCI) += psci.o -obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o -obj-$(CONFIG_ARMV8_PSCI) += smc_fpga_reconfig_s10.o -obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o -obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o -endif -endif - -ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 -obj-y += clock_manager_agilex5.o -obj-y += lowlevel_init_agilex5.o -obj-y += mailbox_s10.o -obj-y += misc_soc64.o -obj-y += mmu-arm64_s10.o -obj-y += reset_manager_s10.o -obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o -obj-y += smmu_agilex5.o -obj-y += system_manager_soc64.o -obj-y += timer_s10.o -obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o -obj-y += wrap_handoff_soc64.o -obj-y += wrap_pll_config_soc64.o -ifndef CONFIG_SPL_BUILD -obj-y += rsu.o -obj-y += rsu_ll_qspi.o -obj-y += rsu_misc.o -obj-y += rsu_s10.o -obj-$(CONFIG_ARMV8_PSCI) += psci.o -obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o -obj-$(CONFIG_ARMV8_PSCI) += smc_fpga_reconfig_s10.o -obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o -obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o -endif -endif - -ifdef CONFIG_TARGET_SOCFPGA_AGILEX7 -obj-y += clock_manager_agilex.o -obj-y += lowlevel_init_soc64.o -obj-y += mailbox_s10.o -obj-y += misc_soc64.o -obj-y += mmu-arm64_s10.o -obj-y += reset_manager_s10.o -obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o -obj-y += smmu_s10.o obj-y += system_manager_soc64.o obj-y += timer_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o -ifndef CONFIG_SPL_BUILD -obj-y += rsu.o -obj-y += rsu_ll_qspi.o -obj-y += rsu_misc.o -obj-y += rsu_s10.o -endif endif ifdef CONFIG_TARGET_SOCFPGA_N5X @@ -137,22 +64,11 @@ obj-y += misc_soc64.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o -obj-y += smmu_s10.o obj-y += system_manager_soc64.o obj-y += timer_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o -ifndef CONFIG_SPL_BUILD -obj-y += rsu.o -obj-y += rsu_ll_qspi.o -obj-y += rsu_misc.o -obj-y += rsu_s10.o -obj-$(CONFIG_ARMV8_PSCI) += psci.o -obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o -obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o -obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o -endif endif ifdef CONFIG_SPL_BUILD @@ -172,22 +88,13 @@ obj-y += spl_a10.o endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += spl_s10.o -obj-y += spl_soc64.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += spl_agilex.o -obj-y += spl_soc64.o endif ifdef CONFIG_TARGET_SOCFPGA_N5X obj-y += spl_n5x.o -obj-y += spl_soc64.o -endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 -obj-y += spl_agilex5.o -obj-y += spl_soc64.o -endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX7 -obj-y += spl_agilex7.o obj-y += spl_soc64.o endif else @@ -195,10 +102,6 @@ obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o obj-$(CONFIG_SPL_ATF) += smc_api.o endif -ifdef CONFIG_SOCFPGA_RSU_MULTIBOOT -obj-y += rsu_spl.o -endif - ifdef CONFIG_TARGET_SOCFPGA_GEN5 # QTS-generated config file wrappers CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index a6ace9fd9f..219e3f9d74 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -183,8 +183,6 @@ void board_prep_linux(struct bootm_headers *images) if (use_fit && IS_ENABLED(CONFIG_CADENCE_QSPI)) { if (env_get("linux_qspi_enable")) run_command(env_get("linux_qspi_enable"), 0); - if (env_get("rsu_status")) - run_command(env_get("rsu_status"), 0); } } #endif diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 20de892414..8215238ac7 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2016-2023 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2024 Intel Corporation <www.intel.com> */ #ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_ @@ -32,14 +32,12 @@ #define SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS 0x18000800 #define SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS 0x18000A00 #define SOCFPGA_FW_TBU2NOC_ADDRESS 0x18000C00 -#define SOCFPGA_FIREWALL_L4_PER 0xffd21000 /* TODO */ -#define SOCFPGA_FIREWALL_L4_SYS 0xffd21100 /* TODO */ -#define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200 /* TODO */ -#define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300 /* TODO */ -#define SOCFPGA_FIREWALL_TCU 0xffd21400 /* TODO */ -#define SOCFPGA_FIREWALL_PRIV_MEMORYMAP_PRIV 0xffd24800 /* TODO */ -#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 /* TODO */ -#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 /* TODO */ +#define SOCFPGA_FIREWALL_L4_PER 0x10d21000 +#define SOCFPGA_FIREWALL_L4_SYS 0x10d21100 +#define SOCFPGA_FIREWALL_SOC2FPGA 0x10d21200 +#define SOCFPGA_FIREWALL_LWSOC2FPGA 0x10d21300 +#define SOCFPGA_FIREWALL_TCU 0x10d21400 +#define SOCFPGA_FIREWALL_PRIV_MEMORYMAP_PRIV 0x10d24800 #define GICD_BASE 0x1d000000 #define GICR_BASE 0x1d060000 #else diff --git a/board/intel/agilex5-socdk/MAINTAINERS b/board/intel/agilex5-socdk/MAINTAINERS index e198308c43..b696f788c8 100755 --- a/board/intel/agilex5-socdk/MAINTAINERS +++ b/board/intel/agilex5-socdk/MAINTAINERS @@ -1,5 +1,7 @@ SOCFPGA BOARD M: Tien Fong Chee <tien.fong.chee(a)intel.com> +M: Teik Heng Chong <teik.heng.chong(a)intel.com> +M: Jit Loon Lim <jit.loon.lim(a)intel.com> S: Maintained F: board/intel/agilex5-socdk/ F: include/configs/socfpga_agilex5_socdk.h diff --git a/board/intel/agilex5-socdk/Makefile b/board/intel/agilex5-socdk/Makefile index 52f7de8880..d598d249e5 100755 --- a/board/intel/agilex5-socdk/Makefile +++ b/board/intel/agilex5-socdk/Makefile @@ -1,5 +1,5 @@ # -# Copyright (C) 2022 Intel Corporation <www.intel.com> +# Copyright (C) 2024 Intel Corporation <www.intel.com> # # SPDX-License-Identifier: GPL-2.0 # diff --git a/board/intel/agilex5-socdk/socfpga.c b/board/intel/agilex5-socdk/socfpga.c index ae5c04557c..f1b5fd9a14 100755 --- a/board/intel/agilex5-socdk/socfpga.c +++ b/board/intel/agilex5-socdk/socfpga.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2022 Intel Corporation <www.intel.com> + * Copyright (C) 2024 Intel Corporation <www.intel.com> * */ diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index fd3e1efc65..415c8e4a2b 100755 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -9,7 +9,6 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x04100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk" -CONFIG_TARGET_SOCFPGA_AGILEX5_SIMICS=y CONFIG_TARGET_SOCFPGA_AGILEX5_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex5" CONFIG_SPL_FS_FAT=y @@ -34,35 +33,18 @@ CONFIG_CMD_NVEDIT_SELECT=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y CONFIG_CMD_SF=y -CONFIG_PHY=y -CONFIG_SPL_PHY=y -CONFIG_PHY_CADENCE_COMBOPHY=y -CONFIG_DM_MMC=y -CONFIG_SPL_MMC=y -CONFIG_SPL_DM_MMC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ADMA=y -CONFIG_SPL_MMC_SDHCI_ADMA=y -CONFIG_SYS_MMC_MAX_BLK_COUNT=256 -CONFIG_MMC_SDHCI_CADENCE=y -CONFIG_CMD_FAT=y CONFIG_DOS_PARTITION=y CONFIG_SPL_DOS_PARTITION=y CONFIG_SPL_SYS_DISABLE_DCACHE_OPS=y CONFIG_CMD_MTD=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SPI_FLASH_MTD=y CONFIG_SPL_MTD_SUPPORT=y -CONFIG_MTDIDS_DEFAULT="nand0=10b80000.nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=10b80000.nand.0:2m(u-boot),-(root)" CONFIG_CMD_UBI=y CONFIG_CMD_UBIFS=y CONFIG_MTD_UBI=y @@ -83,31 +65,22 @@ CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_MISC=y -CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_DM_MTD=y -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y -CONFIG_SYS_NAND_U_BOOT_OFFS=0x0 -CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000 CONFIG_SF_DEFAULT_MODE=0x2003 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_UBI_SILENCE_MSG=y -CONFIG_PHY_MARVELL=y CONFIG_DM_ETH=y -CONFIG_DWC_ETH_XGMAC=y CONFIG_RGMII=y CONFIG_DM_RESET=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y -CONFIG_NOP_PHY=y CONFIG_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_DWC3=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_UBIFS_SILENCE_MSG=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y @@ -136,11 +109,5 @@ CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_I3C=y CONFIG_DW_I3C_MASTER=y CONFIG_CMD_I3C=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_CADENCE=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_NAND_FRAMEWORK=y -CONFIG_SPL_NAND_CADENCE=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_TIMER=y -CONFIG_SYS_NAND_ONFI_DETECTION=y diff --git a/include/configs/socfpga_agilex5_socdk.h b/include/configs/socfpga_agilex5_socdk.h index ad2b5632d1..b5b5bd767f 100755 --- a/include/configs/socfpga_agilex5_socdk.h +++ b/include/configs/socfpga_agilex5_socdk.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> + * Copyright (C) 2024 Intel Corporation <www.intel.com> * */ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index c21d8eb891..a4b6999f40 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2017-2023 Intel Corporation <www.intel.com> + * Copyright (C) 2017-2024 Intel Corporation <www.intel.com> * */ @@ -14,35 +14,6 @@ /* * U-Boot general configurations */ -/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */ -#define CPU_RELEASE_ADDR 0xFFD12210 -/* sysmgr.boot_scratch_cold8 bit 17 (1bit) will be used to check whether CPU0 - * is being powered off/on from kernel - */ -#define BOOT_SCRATCH_COLD8 0xFFD12220 - -/* - * sysmgr.boot_scratch_cold6 & 7 (64bit) will be used by master CPU to - * store its VBAR_EL3 value. Other slave CPUs will read from this - * location and update their VBAR_EL3 respectively - */ -#define VBAR_EL3_BASE_ADDR 0xFFD12218 -/* - * Share sysmgr.boot_scratch_cold6 & 7 (64bit) with VBAR_LE3_BASE_ADDR - * Indicate L2 reset is done. HPS should trigger warm reset via RMR_EL3. - */ -#define L2_RESET_DONE_REG 0xFFD12218 - -/* - * sysmgr.boot_scratch_cold8 bit 19 (1bit) will be used to check whether CPU0 - * is being powered off/on from kernel - */ -#define BOOT_SCRATCH_COLD8 0xFFD12220 - -/* Magic word to indicate L2 reset is completed */ -#define L2_RESET_DONE_STATUS 0x1228E5E7 -#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CFG_SYS_MEM_RESERVE_SECURE 0 /* using OCRAM, not DDR */ /* * U-Boot console configurations @@ -62,8 +33,7 @@ /* * U-Boot environment configurations */ - - /* +/* * NAND support */ #ifdef CONFIG_NAND_DENALI @@ -298,12 +268,6 @@ */ #define CFG_SYS_NS16550_CLK 100000000 -/* -======= - * Timer & watchdog configurations - */ -#define COUNTER_FREQUENCY 400000000 - /* * SDMMC configurations */ -- 2.26.2

3 2

[PATCH 1/2] mtd: rawnand: brcmnand: fallback to detected ecc-strengh, ecc-step-size
by Mark Tomlinson 26 Feb '24

26 Feb '24

[Ported to U-Boot from the Linux kernel, commit 78933218f5c, original author Kamal Dasu <kdasu.kdev(a)gmail.com>] The following description is from that patch: If both nand-ecc-strength and nand-ecc-step-size are not specified in device tree node for NAND, raw NAND layer does detect ECC information by reading ONFI extended parameter page for parts using ONFI >= 2.1. In case of non-ONFI NAND parts there could be a nand_id table entry with ECC information. If there is valid device tree entry for nand-ecc-strength and nand-ecc-step-size fields it still shall override the detected values. Signed-off-by: Mark Tomlinson <mark.tomlinson(a)alliedtelesis.co.nz> Cc: Dario Binacchi <dario.binacchi(a)amarulasolutions.com> Cc: Michael Trimarchi <michael(a)amarulasolutions.com> --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index efbf9a3120a..3e5ae93dda2 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -2336,6 +2336,17 @@ static int brcmnand_setup_dev(struct brcmnand_host *host) return -EINVAL; } + if (chip->ecc.mode != NAND_ECC_NONE && + (!chip->ecc.size || !chip->ecc.strength)) { + if (chip->ecc_step_ds && chip->ecc_strength_ds) { + /* use detected parameters */ + chip->ecc.size = chip->ecc_step_ds; + chip->ecc.strength = chip->ecc_strength_ds; + dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n", + chip->ecc.size, chip->ecc.strength); + } + } + switch (chip->ecc.size) { case 512: if (chip->ecc.algo == NAND_ECC_HAMMING) -- 2.43.2

1 1

[PATCH] rockchip: rock64: store env in SPI flash
by Ben Wolsieffer 25 Feb '24

25 Feb '24

Currently, U-Boot attempts to store the environment in MMC 0, which doesn't work when an eMMC is used without an SD card. There is an SPI flash chip on the board, so use that instead which should work in all cases. Additionally, this brings the Rock64 into line with the RockPro64. Signed-off-by: Ben Wolsieffer <benwolsieffer(a)gmail.com> --- configs/rock64-rk3328_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 0297d09876..589e5184ca 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -8,6 +8,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" CONFIG_DM_RESET=y @@ -54,7 +55,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y -CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_NET_RANDOM_ETHADDR=y -- 2.43.2

2 2

Raspberry Pi 3b Plus USB-Ethernet lan78xx_eth address not set
by Sourabh Hegde Ramu 25 Feb '24

25 Feb '24

Hello, I have a Raspberry Pi 3B Plus which I want to integrate with U-boot (v2023.10) . I am using rpi_3_32b_defconfig to generate u-boot.bin. But while booting I am getting below error Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1... In: serial,usbkbd Out: serial,vidconsole Err: serial,vidconsole Net: No ethernet found. starting USB... Bus usb@7e980000: USB DWC2 scanning bus usb@7e980000 for devices... Error: lan78xx_eth address not set. 3 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found Hit any key to stop autoboot: 0 In the "bdinfo", "current eth" is not set U-Boot> bdinfo boot_params = 0x00000100 DRAM bank = 0x00000000 -> start = 0x00000000 -> size = 0x3b400000 flashstart = 0x00000000 flashsize = 0x00000000 flashoffset = 0x00000000 baudrate = 115200 bps relocaddr = 0x3b360000 reloc off = 0x3b358000 Build = 32-bit current eth = unknown eth-1addr = (not set) IP addr = <NULL> I also enabled LAN75xx in menuconfig and re-compiled u-boot. But still the same error. However on Raspberry Pi 3B, I don't see this error and "current eth" is set to "smsc95xx_eth" and "ethaddr" is also available. Can anyone please let me know the issue with Raspberry Pi 3b plus? Thanks in advance.

3 5

[GIT PULL] Please pull u-boot-imx-master-20240224
by Fabio Estevam 25 Feb '24

25 Feb '24

Hi Tom, Please pull from u-boot-imx, thanks. The following changes since commit bb9d6c7f4f6a598e8856b2e19e58c7de078a0d6e: Merge tag 'u-boot-amlogic-fixes-20240223' of https://source.denx.de/u-boot/custodians/u-boot-amlogic (2024-02-23 12:54:03 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git tags/u-boot-imx-master-20240224 for you to fetch changes up to 7c76b1b91bf67cd09fdf5dbd71590f9e580590fa: opos6uldev: Convert to watchdog driver model (2024-02-24 16:29:24 -0300) u-boot-imx-master-20240224 -------------------------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/19725 - Enable the thermal driver for the imx8m phycore boards. - Convert imx53-qsb to watchdog driver to fix the 'reset' command. - Remove multiline string from imx6dl-sielaff. - Add SPI boot support for imxrt1050-evk. - Convert opos6uldev to watchdog driver to fix the 'reset' command. ---------------------------------------------------------------- Benjamin Hahn (3): phycore-imx8mp_defconfig: Enable CONFIG_IMX_TMU phycore-imx8mm_defconfig: Enable CONFIG_IMX_TMU imx8mm-phygate-tauri-l_defconfig: Enable CONFIG_IMX_TMU Fabio Estevam (1): imx53-qsb: Convert to watchdog driver model Frieder Schrempf (1): board: imx6dl-sielaff: spl.c: Remove multiline string Jesse Taube (2): imx: imxrt1050-evk: Add support for SPI flash booting imx: imxrt1050-evk: Add documentation for SPI boot Mathieu Othacehe (4): arm: dts: imx93: Add USB support. arm: dts: imx93-var-som-symphony: Add USB support. configs: imx93_var_som: Add USB support. configs: imx93_var_som: Add fastboot support. Sébastien Szymanski (1): opos6uldev: Convert to watchdog driver model arch/arm/dts/imx53-qsb-u-boot.dtsi | 13 ++++ arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi | 10 +++ arch/arm/dts/imx93-var-som-symphony.dts | 18 +++++ arch/arm/dts/imx93.dtsi | 58 ++++++++++++++ arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 4 + arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 31 ++++++++ arch/arm/dts/imxrt1170-evk-u-boot.dtsi | 4 + arch/arm/mach-imx/imxrt/Kconfig | 1 + board/freescale/imxrt1050-evk/MAINTAINERS | 1 + board/freescale/imxrt1050-evk/imximage-nor.cfg | 41 ++++++++++ board/freescale/imxrt1050-evk/imximage.cfg | 10 ++- board/freescale/imxrt1050-evk/imxrt1050-evk.c | 7 +- board/sielaff/imx6dl-sielaff/spl.c | 4 +- configs/imx8mm-phygate-tauri-l_defconfig | 1 + configs/imx93_var_som_defconfig | 15 ++++ configs/imxrt1050-evk_defconfig | 8 +- configs/imxrt1050-evk_fspi_defconfig | 100 +++++++++++++++++++++++++ configs/mx53loco_defconfig | 3 + configs/opos6uldev_defconfig | 3 + configs/phycore-imx8mm_defconfig | 1 + configs/phycore-imx8mp_defconfig | 1 + doc/board/nxp/imxrt1050-evk.rst | 30 ++++++++ include/configs/imxrt1050-evk.h | 6 ++ 23 files changed, 362 insertions(+), 8 deletions(-) create mode 100644 arch/arm/dts/imx53-qsb-u-boot.dtsi create mode 100644 board/freescale/imxrt1050-evk/imximage-nor.cfg create mode 100644 configs/imxrt1050-evk_fspi_defconfig

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[PATCH 1/1] arm: separate .data and .text sections of EFI binaries
by Heinrich Schuchardt 25 Feb '24

25 Feb '24

EFI binaries should not contain sections that are both writable and executable. Separate the RX .text section from the RW .data section. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- arch/arm/lib/crt0_arm_efi.S | 35 +++++++++++++++++++++++++++-------- arch/arm/lib/elf_arm_efi.lds | 33 ++++++++++++++++++++++----------- 2 files changed, 49 insertions(+), 19 deletions(-) diff --git a/arch/arm/lib/crt0_arm_efi.S b/arch/arm/lib/crt0_arm_efi.S index f6deca9a14..ba9fada500 100644 --- a/arch/arm/lib/crt0_arm_efi.S +++ b/arch/arm/lib/crt0_arm_efi.S @@ -23,7 +23,7 @@ pe_header: .long IMAGE_NT_SIGNATURE /* 'PE' */ coff_header: .short IMAGE_FILE_MACHINE_THUMB /* Mixed ARM/Thumb */ - .short 2 /* nr_sections */ + .short 3 /* nr_sections */ .long 0 /* TimeDateStamp */ .long 0 /* PointerToSymbolTable */ .long 0 /* NumberOfSymbols */ @@ -107,16 +107,35 @@ section_table: .byte 0 .byte 0 .byte 0 /* end of 0 padding of section name */ - .long _edata - _start /* VirtualSize */ + .long _etext - _start /* VirtualSize */ .long _start - image_base /* VirtualAddress */ - .long _edata - _start /* SizeOfRawData */ + .long _etext - _start /* SizeOfRawData */ .long _start - image_base /* PointerToRawData */ + .long 0 /* PointerToRelocations */ + .long 0 /* PointerToLineNumbers */ + .short 0 /* NumberOfRelocations */ + .short 0 /* NumberOfLineNumbers */ + /* Characteristics (section flags) */ + .long (IMAGE_SCN_MEM_READ | \ + IMAGE_SCN_MEM_EXECUTE | \ + IMAGE_SCN_CNT_CODE) - .long 0 /* PointerToRelocations (0 for executables) */ - .long 0 /* PointerToLineNumbers (0 for executables) */ - .short 0 /* NumberOfRelocations (0 for executables) */ - .short 0 /* NumberOfLineNumbers (0 for executables) */ - .long 0xe0500020 /* Characteristics (section flags) */ + .ascii ".data" + .byte 0 + .byte 0 + .byte 0 /* end of 0 padding of section name */ + .long _data_size /* VirtualSize */ + .long _data - image_base /* VirtualAddress */ + .long _data_size /* SizeOfRawData */ + .long _data - image_base /* PointerToRawData */ + .long 0 /* PointerToRelocations */ + .long 0 /* PointerToLineNumbers */ + .short 0 /* NumberOfRelocations */ + .short 0 /* NumberOfLineNumbers */ + /* Characteristics (section flags) */ + .long (IMAGE_SCN_MEM_WRITE | \ + IMAGE_SCN_MEM_READ | \ + IMAGE_SCN_CNT_INITIALIZED_DATA) .align 12 _start: diff --git a/arch/arm/lib/elf_arm_efi.lds b/arch/arm/lib/elf_arm_efi.lds index 767ebda635..75341df5dd 100644 --- a/arch/arm/lib/elf_arm_efi.lds +++ b/arch/arm/lib/elf_arm_efi.lds @@ -7,6 +7,12 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) + +PHDRS +{ + data PT_LOAD FLAGS(3); /* SHF_WRITE | SHF_ALLOC */ +} + ENTRY(_start) SECTIONS { @@ -18,11 +24,17 @@ SECTIONS *(.gnu.linkonce.t.*) *(.srodata) *(.rodata*) + . = ALIGN(16); + *(.dynamic); . = ALIGN(512); } + .rela.dyn : { *(.rela.dyn) } + .rela.plt : { *(.rela.plt) } + .rela.got : { *(.rela.got) } + .rela.data : { *(.rela.data) *(.rela.data*) } _etext = .; _text_size = . - _text; - .dynamic : { *(.dynamic) } + . = ALIGN(4096); .data : { _data = .; *(.sdata) @@ -47,20 +59,19 @@ SECTIONS . = ALIGN(512); _bss_end = .; _edata = .; - } - .rel.dyn : { *(.rel.dyn) } - .rel.plt : { *(.rel.plt) } - .rel.got : { *(.rel.got) } - .rel.data : { *(.rel.data) *(.rel.data*) } - _data_size = . - _etext; + } :data + _data_size = _edata - _data; + . = ALIGN(4096); + .dynsym : { *(.dynsym) } + . = ALIGN(4096); + .dynstr : { *(.dynstr) } + . = ALIGN(4096); + .note.gnu.build-id : { *(.note.gnu.build-id) } /DISCARD/ : { *(.rel.reloc) *(.eh_frame) *(.note.GNU-stack) - *(.dynsym) - *(.dynstr) - *(.note.gnu.build-id) - *(.comment) } + .comment 0 : { *(.comment) } } -- 2.43.0

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[PATCH 1/1] opos6uldev: Convert to watchdog driver model
by Sébastien Szymanski 24 Feb '24

24 Feb '24

Commit 68dcbdd594d4 ("ARM: imx: Add weak default reset_cpu()") caused the 'reset' command in U-Boot to not cause a board reset. Fix it by switching to the watchdog driver model via sysreset, which is the preferred method for implementing the watchdog reset. Signed-off-by: Sébastien Szymanski <sebastien.szymanski(a)armadeus.com> --- arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi | 10 ++++++++++ configs/opos6uldev_defconfig | 3 +++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi b/arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi index ebfb95dcdf4b..e65eeb8d8ceb 100644 --- a/arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi +++ b/arch/arm/dts/imx6ul-opos6ul-u-boot.dtsi @@ -9,6 +9,12 @@ soc { bootph-pre-ram; }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; }; &aips2 { @@ -26,3 +32,7 @@ &usdhc1 { bootph-pre-ram; }; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index ac4170d2e49a..e1884df9dd23 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -102,6 +102,8 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y @@ -123,4 +125,5 @@ CONFIG_SPLASH_SOURCE=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y +CONFIG_IMX_WATCHDOG=y # CONFIG_EFI_LOADER is not set -- 2.43.0

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[PATCH] imx53-qsb: Convert to watchdog driver model
by Fabio Estevam 24 Feb '24

24 Feb '24

Commit 68dcbdd594d4 ("ARM: imx: Add weak default reset_cpu()") caused the 'reset' command in U-Boot to not cause a board reset. Fix it by switching to the watchdog driver model via sysreset, which is the preferred method for implementing the watchdog reset. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- arch/arm/dts/imx53-qsb-u-boot.dtsi | 14 ++++++++++++++ configs/mx53loco_defconfig | 3 +++ 2 files changed, 17 insertions(+) create mode 100644 arch/arm/dts/imx53-qsb-u-boot.dtsi diff --git a/arch/arm/dts/imx53-qsb-u-boot.dtsi b/arch/arm/dts/imx53-qsb-u-boot.dtsi new file mode 100644 index 000000000000..593ab7caa635 --- /dev/null +++ b/arch/arm/dts/imx53-qsb-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; +}; + +&wdog1 { + bootph-pre-ram; +}; + diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig index d4de8df7b49d..e2d3bc0b094e 100644 --- a/configs/mx53loco_defconfig +++ b/configs/mx53loco_defconfig @@ -60,6 +60,8 @@ CONFIG_POWER_FSL=y CONFIG_POWER_I2C=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_USB=y CONFIG_USB_EHCI_MX5=y CONFIG_USB_STORAGE=y @@ -67,3 +69,4 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_IMX_WATCHDOG=y -- 2.34.1

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[PATCH 0/3] Enable IMX_TMU driver for PHYTEC boards
by Benjamin Hahn 24 Feb '24

24 Feb '24

Enable IMX_TMU driver to prevent the system from booting when it is too hot. Signed-off-by: Benjamin Hahn <B.Hahn(a)phytec.de> --- Benjamin Hahn (3): phycore-imx8mp_defconfig: Enable CONFIG_IMX_TMU phycore-imx8mm_defconfig: Enable CONFIG_IMX_TMU imx8mm-phygate-tauri-l_defconfig: Enable CONFIG_IMX_TMU configs/imx8mm-phygate-tauri-l_defconfig | 1 + configs/phycore-imx8mm_defconfig | 1 + configs/phycore-imx8mp_defconfig | 1 + 3 files changed, 3 insertions(+) --- base-commit: 3e6f2a94bfc25f1782ce2d45db27f47ec781feb1 change-id: 20240220-thermal-support-3e4f6f09ff5c Best regards, -- Benjamin Hahn <B.Hahn(a)phytec.de>

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