February 2024 - U-Boot

[PATCH] arm64: zynqmp: Remove snps,enable_guctl1_ipd_quirk property
by Michal Simek 01 Mar '24

01 Mar '24

Remove undocumented DT property. Suggested solution was to apply quirk via glue logic driver that's why make no sense to have it listed in DT. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- For more information please take a look at: https://lore.kernel.org/r/1708023665-1441674-1-git-send-email-radhey.shyam.… https://lore.kernel.org/r/1708717523-4006664-1-git-send-email-radhey.shyam.… --- arch/arm/dts/zynqmp.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index b50b83b7723f..daae23c12b79 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -1008,7 +1008,6 @@ /* iommus = <&smmu 0x860>; */ snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; - snps,enable_guctl1_ipd_quirk; snps,resume-hs-terminations; /* dma-coherent; */ }; @@ -1040,7 +1039,6 @@ /* iommus = <&smmu 0x861>; */ snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; - snps,enable_guctl1_ipd_quirk; snps,resume-hs-terminations; /* dma-coherent; */ }; -- 2.36.1

2 2

[RFC PATCH 0/4] Cleanup J721E EVM and SK
by Neha Malcom Francis 01 Mar '24

01 Mar '24

This series does primarily three things: 1. Split out the common J721E defconfig for both EVM and SK 2. Cleanup k3-j721e-binman.dtsi to be SoC specific binman nodes and -u-boot.dtsi files of the respective boards can pick and edit according to their board. This is based on the discussion [1] 3. Move J721E EVM and SK to using OF_UPSTREAM This series depends on series [2] and patch [3] which implement OF_UPSTREAM. Hopefully we get an idea of whether this is what we want to see across all K3 SoCs by the next release. [1] https://lore.kernel.org/u-boot/20240123205255.i7eynu6vdpoxwybf@irregular/ [2] https://lore.kernel.org/u-boot/20240222093607.3085545-1-sumit.garg@linaro.o… [3] https://lore.kernel.org/u-boot/20240205-am62px-wip-rebasing-v3-11-04cbb42ea… Boot logs: https://gist.github.com/nehamalcom/3b578dfa1ef83b59f3c309557606ed63 Neha Malcom Francis (4): configs: j721e_sk: Move to separate defconfig for J721E SK board tools: binman: control.py: Delete template nodes after parsing arm: dts: k3-j721e: Separate boot binary build arm: dts: k3-j721e: Move to OF_UPSTREAM arch/arm/dts/Makefile | 4 +- arch/arm/dts/k3-j721e-binman.dtsi | 178 +- .../k3-j721e-common-proc-board-u-boot.dtsi | 138 + arch/arm/dts/k3-j721e-common-proc-board.dts | 976 ------ arch/arm/dts/k3-j721e-main.dtsi | 2741 ----------------- arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 681 ---- arch/arm/dts/k3-j721e-sk-u-boot.dtsi | 104 + arch/arm/dts/k3-j721e-sk.dts | 1074 ------- arch/arm/dts/k3-j721e-som-p0.dtsi | 446 --- arch/arm/dts/k3-j721e-thermal.dtsi | 75 - arch/arm/dts/k3-j721e.dtsi | 176 -- board/ti/j721e/MAINTAINERS | 2 + configs/j721e_evm_a72_defconfig | 5 +- configs/j721e_evm_r5_defconfig | 2 +- configs/j721e_sk_a72_defconfig | 4 + configs/j721e_sk_r5_defconfig | 5 + tools/binman/control.py | 6 +- 17 files changed, 305 insertions(+), 6312 deletions(-) delete mode 100644 arch/arm/dts/k3-j721e-common-proc-board.dts delete mode 100644 arch/arm/dts/k3-j721e-main.dtsi delete mode 100644 arch/arm/dts/k3-j721e-mcu-wakeup.dtsi delete mode 100644 arch/arm/dts/k3-j721e-sk.dts delete mode 100644 arch/arm/dts/k3-j721e-som-p0.dtsi delete mode 100644 arch/arm/dts/k3-j721e-thermal.dtsi delete mode 100644 arch/arm/dts/k3-j721e.dtsi create mode 100644 configs/j721e_sk_a72_defconfig create mode 100644 configs/j721e_sk_r5_defconfig -- 2.34.1

3 8

[PATCH] board: rockchip: add Rockchip Toybrick TB-RK3588X board
by Elon Zhang 01 Mar '24

01 Mar '24

TB-RK3588X board is a Rockchip Toybrick RK3588 based development board. Specification: Rockchip Rk3588 SoC 4x ARM Cortex-A76, 4x ARM Cortex-A55 8/16GB Memory LPDDR4x Mali G610MC4 GPU 2× MIPI-CSI0 Connector 1x 2Lanes PCIe3.0 Connector 1x SATA3.0 Connector 32GB eMMC Module 2x USB 2.0, 2x USB 3.0 1x HDMI Output, 1x HDMI Input 2x Ethernet Port Functions work normally: [1] USB2.0 Host [2] Ethernet0 with PHY RTL8211F More information can be obtained from the following websites: [1] https://t.rock-chips.com/en/wiki/EN/tb-rk3588x_en/index.html [2] http://t.rock-chips.com/ Kernel commits: 8ffe365f8dc7 ("arm64: dts: rockchip: Add devicetree support for TB-RK3588X board") 7140387ff49d ("dt-bindings: arm: rockchip: Add Toybrick TB-RK3588X") Signed-off-by: Elon Zhang <zhangzj(a)rock-chips.com> --- arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi | 12 + arch/arm/dts/rk3588-toybrick-x0.dts | 672 ++++++++++++++++++ arch/arm/mach-rockchip/rk3588/Kconfig | 25 + board/rockchip/toybrick_rk3588/Kconfig | 15 + board/rockchip/toybrick_rk3588/MAINTAINERS | 8 + board/rockchip/toybrick_rk3588/Makefile | 6 + .../toybrick_rk3588/toybrick-rk3588.c | 39 + configs/toybrick-rk3588_defconfig | 82 +++ doc/board/rockchip/rockchip.rst | 1 + include/configs/toybrick_rk3588.h | 15 + 10 files changed, 875 insertions(+) create mode 100644 arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588-toybrick-x0.dts create mode 100644 board/rockchip/toybrick_rk3588/Kconfig create mode 100644 board/rockchip/toybrick_rk3588/MAINTAINERS create mode 100644 board/rockchip/toybrick_rk3588/Makefile create mode 100644 board/rockchip/toybrick_rk3588/toybrick-rk3588.c create mode 100644 configs/toybrick-rk3588_defconfig create mode 100644 include/configs/toybrick_rk3588.h diff --git a/arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi b/arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi new file mode 100644 index 0000000000..1aeb5410e4 --- /dev/null +++ b/arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#include "rk3588-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci; + }; +}; diff --git a/arch/arm/dts/rk3588-toybrick-x0.dts b/arch/arm/dts/rk3588-toybrick-x0.dts new file mode 100644 index 0000000000..f3f7c1d35e --- /dev/null +++ b/arch/arm/dts/rk3588-toybrick-x0.dts @@ -0,0 +1,672 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3588.dtsi" + +/ { + model = "Rockchip Toybrick TB-RK3588X Board"; + compatible = "rockchip,rk3588-toybrick-x0", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-vol-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <17000>; + }; + + button-vol-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <417000>; + }; + + button-menu { + label = "Menu"; + linux,code = <KEY_MENU>; + press-threshold-microvolt = <890000>; + }; + + button-escape { + label = "Escape"; + linux,code = <KEY_ESC>; + press-threshold-microvolt = <1235000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc12v_dcin>; + pwms = <&pwm2 0 25000 0>; + }; + + pcie20_avdd0v85: pcie20-avdd0v85-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-rxid"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + pinctrl-names = "default"; + rx_delay = <0x00>; + tx_delay = <0x43>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index a2193fbd41..ff6c12903d 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -155,6 +155,30 @@ config TARGET_TURINGRK1_RK3588 Gigabit Ethernet Size: 69.6mm x 45mm (260-pin SO-DIMM connector) +config TARGET_TOYBRICK_RK3588 + bool "Toybrick TB-RK3588X board" + select BOARD_LATE_INIT + help + Rockchip Toybrick TB-RK3588X is a Rockchip RK3588 based development board. + TB-RK3588X adopts core board and mainboard design. The core board is connected + with the mainboard through the MXM314Pin standard interface, which can form + a complete industry development board. + + Specifications: + + Rockchip RK3588 SoC + 4x ARM Cortex-A76, 4x ARM Cortex-A55 + 8/16GB Memory LPDDR4x + Mali G610MC4 GPU + 2× MIPI-CSI0 Connector + 1x 2Lanes PCIe3.0 Connector + 1x SATA3.0 Connector + 32GB eMMC Module + 2x USB2.0, 2x USB3.0 + 1x HDMI Output, 1x HDMI Input + 2x Ethernet Port + + config ROCKCHIP_BOOT_MODE_REG default 0xfd588080 @@ -174,5 +198,6 @@ source board/turing/turing-rk1-rk3588/Kconfig source board/rockchip/evb_rk3588/Kconfig source board/radxa/rock5a-rk3588s/Kconfig source board/radxa/rock5b-rk3588/Kconfig +source board/rockchip/toybrick_rk3588/Kconfig endif diff --git a/board/rockchip/toybrick_rk3588/Kconfig b/board/rockchip/toybrick_rk3588/Kconfig new file mode 100644 index 0000000000..e3949f247b --- /dev/null +++ b/board/rockchip/toybrick_rk3588/Kconfig @@ -0,0 +1,15 @@ +if TARGET_TOYBRICK_RK3588 + +config SYS_BOARD + default "toybrick_rk3588" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "toybrick_rk3588" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/toybrick_rk3588/MAINTAINERS b/board/rockchip/toybrick_rk3588/MAINTAINERS new file mode 100644 index 0000000000..cd4401c24f --- /dev/null +++ b/board/rockchip/toybrick_rk3588/MAINTAINERS @@ -0,0 +1,8 @@ +TOYBRICK-RK3588 +M: Elon Zhang <zhangzj(a)rock-chips.com> +S: Maintained +F: board/rockchip/toybrick_rk3588 +F: include/configs/toybrick_rk3588.h +F: configs/toybrick-rk3588_defconfig +F: arch/arm/dts/rk3588-toybrick-x0.dts +F: arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi diff --git a/board/rockchip/toybrick_rk3588/Makefile b/board/rockchip/toybrick_rk3588/Makefile new file mode 100644 index 0000000000..75d4d9438f --- /dev/null +++ b/board/rockchip/toybrick_rk3588/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2024 Rockchip Electronics Co,. Ltd. +# + +obj-y += toybrick-rk3588.o diff --git a/board/rockchip/toybrick_rk3588/toybrick-rk3588.c b/board/rockchip/toybrick_rk3588/toybrick-rk3588.c new file mode 100644 index 0000000000..dfbfba22c6 --- /dev/null +++ b/board/rockchip/toybrick_rk3588/toybrick-rk3588.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 Rockchip Electronics Co,. Ltd. + */ + +#include <fdtdec.h> +#include <fdt_support.h> + +#ifdef CONFIG_OF_BOARD_SETUP +static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob) +{ + struct fdt_memory gap1 = { + .start = 0x3fc000000, + .end = 0x3fc4fffff, + }; + struct fdt_memory gap2 = { + .start = 0x3fff00000, + .end = 0x3ffffffff, + }; + unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; + unsigned int ret; + + /* + * Inject the reserved-memory nodes into the DTS + */ + ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0, + NULL, flags); + if (ret) + return ret; + + return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0, + NULL, flags); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return rk3588_add_reserved_memory_fdt_nodes(blob); +} +#endif diff --git a/configs/toybrick-rk3588_defconfig b/configs/toybrick-rk3588_defconfig new file mode 100644 index 0000000000..0b6016955d --- /dev/null +++ b/configs/toybrick-rk3588_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_ENV_SIZE=0x1f000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588-toybrick-x0" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_TOYBRICK_RK3588=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-toybrick-x0.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index e23ca4231c..d5b6ee956e 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -120,6 +120,7 @@ List of mainline supported Rockchip boards: - Turing Machines RK1 (turing-rk1-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) - Radxa ROCK 5B (rock5b-rk3588) + - Rockchip Toybrick TB-RK3588X (toybrick-rk3588) - Xunlong Orange Pi 5 (orangepi-5-rk3588s) - Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588) diff --git a/include/configs/toybrick_rk3588.h b/include/configs/toybrick_rk3588.h new file mode 100644 index 0000000000..faa2e6c19c --- /dev/null +++ b/include/configs/toybrick_rk3588.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#ifndef __TOYBRICK_RK3588_H +#define __TOYBRICK_RK3588_H + +#include <configs/rk3588_common.h> + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif -- 2.34.1

2 2

[PATCH v8 0/8] Handoff bloblist from previous boot stage
by Raymond Mao 29 Feb '24

29 Feb '24

This patch set adds/adapts a few bloblist APIs and implements Arm arch custom function to retrieve the bloblist (aka. Transfer List) from previous loader via boot arguments when BLOBLIST option is enabled and all boot arguments are compliant to the register conventions defined in the Firmware Handoff spec v0.9. If an arch wishes to have different behaviors for loading bloblist from the previous boot stage, it is required to implement the custom function xferlist_from_boot_arg(). V5: Drop [PATCH v4 8/9] fdt: update the document and Kconfig description. V6: Drop [PATCH v5 8/8] fdt: get FDT from bloblist. V7: Fixed CI pipeline failures. V8: Refine asm code. Raymond Mao (8): bloblist: add API to check the register conventions bloblist: check bloblist with specified buffer size bloblist: refactor of bloblist_reloc() arm: armv7: save boot arguments arm: armv8: save boot arguments arm: Get bloblist from boot arguments bloblist: Load the bloblist from the previous loader dts: OF_HAS_PRIOR_STAGE should depend on !BLOBLIST arch/arm/cpu/armv7/start.S | 29 +++++++++++++ arch/arm/cpu/armv8/start.S | 23 +++++++++++ arch/arm/lib/Makefile | 2 + arch/arm/lib/xferlist.c | 25 +++++++++++ arch/arm/lib/xferlist.h | 19 +++++++++ common/bloblist.c | 85 ++++++++++++++++++++++++++++---------- common/board_f.c | 9 ++-- dts/Kconfig | 1 + include/bloblist.h | 47 +++++++++++++++++---- test/bloblist.c | 8 ++-- 10 files changed, 208 insertions(+), 40 deletions(-) create mode 100644 arch/arm/lib/xferlist.c create mode 100644 arch/arm/lib/xferlist.h -- 2.25.1

3 11

[PATCH] mtd: spinand: Add support for XTX XT26xxxDxxxxx
by Bruce Suen 29 Feb '24

29 Feb '24

Add Support XTX Technology XT26G01DXXXXX, XT26G11DXXXXX, XT26Q01DXXXXX, XT26G02DXXXXX, XT26G12DXXXXX, XT26Q02DXXXXX, XT26G04DXXXXX, and XT26Q04DXXXXX SPI NAND. These are 3V/1.8V 1G/2G/4Gbit serial SLC NAND flash device with on-die ECC(8bit strength per 512bytes). Datasheet Links: - http://www.xtxtech.com/download/?AId=458 - http://www.xtxtech.com/download/?AId=495 Signed-off-by: Bruce Suen <bruce_suen(a)163.com> --- drivers/mtd/nand/spi/Makefile | 1 + drivers/mtd/nand/spi/core.c | 1 + drivers/mtd/nand/spi/xtx.c | 180 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 1 + 4 files changed, 183 insertions(+) create mode 100644 drivers/mtd/nand/spi/xtx.c diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile index 3051de4f7e..e46cfed446 100644 --- a/drivers/mtd/nand/spi/Makefile +++ b/drivers/mtd/nand/spi/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o +spinand-objs += xtx.o obj-$(CONFIG_MTD_SPI_NAND) += spinand.o diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 597b088ca7..0b4c067425 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -828,6 +828,7 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = { &paragon_spinand_manufacturer, &toshiba_spinand_manufacturer, &winbond_spinand_manufacturer, + &xtx_spinand_manufacturer, }; static int spinand_manufacturer_match(struct spinand_device *spinand, diff --git a/drivers/mtd/nand/spi/xtx.c b/drivers/mtd/nand/spi/xtx.c new file mode 100644 index 0000000000..602861c77b --- /dev/null +++ b/drivers/mtd/nand/spi/xtx.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Stefan Roese <sr(a)denx.de> + * + * Derived from drivers/mtd/nand/spi/micron.c + * Copyright (c) 2016-2017 Micron Technology, Inc. + */ + +#ifndef __UBOOT__ +#include <linux/device.h> +#include <linux/kernel.h> +#endif +#include <linux/bitfield.h> +#include <linux/mtd/spinand.h> + +#define SPINAND_MFR_XTX 0x0B + +#define XT26XXXD_STATUS_ECC3_ECC2_MASK GENMASK(7, 6) +#define XT26XXXD_STATUS_ECC_NO_DETECTED (0) +#define XT26XXXD_STATUS_ECC_1_7_CORRECTED (1) +#define XT26XXXD_STATUS_ECC_8_CORRECTED (3) +#define XT26XXXD_STATUS_ECC_UNCOR_ERROR (2) + +static SPINAND_OP_VARIANTS(read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + +static SPINAND_OP_VARIANTS(write_cache_variants, + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), + SPINAND_PROG_LOAD(true, 0, NULL, 0)); + +static SPINAND_OP_VARIANTS(update_cache_variants, + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + +static int xt26xxxd_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = mtd->oobsize / 2; + region->length = mtd->oobsize / 2; + + return 0; +} + +static int xt26xxxd_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = 2; + region->length = mtd->oobsize / 2 - 2; + + return 0; +} + +static const struct mtd_ooblayout_ops xt26xxxd_ooblayout = { + .ecc = xt26xxxd_ooblayout_ecc, + .rfree = xt26xxxd_ooblayout_free, +}; + +static int xt26xxxd_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + switch (FIELD_GET(STATUS_ECC_MASK, status)) { + case XT26XXXD_STATUS_ECC_NO_DETECTED: + return 0; + case XT26XXXD_STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; + case XT26XXXD_STATUS_ECC_1_7_CORRECTED: + return 4 + FIELD_GET(XT26XXXD_STATUS_ECC3_ECC2_MASK, status); + case XT26XXXD_STATUS_ECC_8_CORRECTED: + return 8; + default: + break; + } + + return -EINVAL; +} + +static const struct spinand_info xtx_spinand_table[] = { + SPINAND_INFO("XT26G01D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x31), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26G11D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x34), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26Q01D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x51), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26G02D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x32), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26G12D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x35), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26Q02D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26G04D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x33), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26Q04D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x53), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), +}; + +static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = { +}; + +const struct spinand_manufacturer xtx_spinand_manufacturer = { + .id = SPINAND_MFR_XTX, + .name = "XTX", + .chips = xtx_spinand_table, + .nchips = ARRAY_SIZE(xtx_spinand_table), + .ops = &xtx_spinand_manuf_ops, +}; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index e8d6feb970..bf7696a981 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -251,6 +251,7 @@ extern const struct spinand_manufacturer micron_spinand_manufacturer; extern const struct spinand_manufacturer paragon_spinand_manufacturer; extern const struct spinand_manufacturer toshiba_spinand_manufacturer; extern const struct spinand_manufacturer winbond_spinand_manufacturer; +extern const struct spinand_manufacturer xtx_spinand_manufacturer; /** * struct spinand_op_variants - SPI NAND operation variants -- 2.34.1

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[PATCH v2 00/16] rockchip: add support for SARADCv2 and RK806 PMIC and regulators
by Quentin Schulz 29 Feb '24

29 Feb '24

The RK3588 has a new IP for SARADC compared to older SoCs of the same vendor but most of the boilerplate is shared, so rockchip-saradc.c driver is adapted instead of creating a new one. Because the SARADC requires a vref-supply which is commonly coming from a regulator of the RK806 PMIC, support for the RK806 PMIC and regulators are also added in this patch series. Finally, RK806 PMIC is the first one to actually support SPI as communication layer between the SoC and the PMIC (but supports I2C as well according to the datasheet). This adds support for RK806 over SPI though there should be no reason for RK806 over I2C to not work. Note that the DT now uses a different prefix for the buck and ldo node names and the RK806 is the first one to use nldo and pldo and while they both are LDOs, they have overlapping indices which makes it impossible to simply reuse the rk8xx_ldo driver and need to define new ones (though some callbacks can be reused, as is done in this patch series). The SARADC was tested by toggling the BIOS button connected over channel 0 on RK3588 Jaguar and using the adc or button commands to watch over the value. The PMIC was tested with the pmic command for reading the CHIP_VERS registers and writing to the WDT_REG (0x73). The regulators were tested by using a modified DT for RK3588 Jaguar and playing with the regulator command to enable/disable some buck/nldo/pldo and modify their output voltage. This has a light dependency on https://lore.kernel.org/u-boot/20240221-jaguar-v3-0-1f256a82201b@theobroma-… because of: - remove of asm/io.h include in favor of asm/arch-rockchip/hardware.h (both should be included if applied before the dependency) - Jaguar defconfig modified in this patch series is added in the aforementioned patch series, Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- Changes in v2: - fixed incorrect bitmasking when selecting channel - added optional controller reset to match downstream U-Boot and both downstream and upstream Linux kernel logic, - Link to v1: https://lore.kernel.org/r/20240221-rk3588-saradc-v1-0-c39a5601d1cc@theobrom… --- Quentin Schulz (15): rockchip: spi: rk_spi: do not write bytes when in read-only mode regulator: rk8xx: remove unused functions regulator: rk8xx: add indirection level for some ldo callbacks power: rk8xx: add support for RK806 pmic: reword help text rockchip: adc: rockchip-saradc: use union for preparing for v2 rockchip: adc: rockchip-saradc: factor out channel_data callback rockchip: adc: rockchip-saradc: factor out start_channel callback rockchip: adc: rockchip-saradc: factor out stop callback rockchip: adc: rockchip-saradc: add support for RK3588 power: pmic: rk8xx: fix duplicate prompt rockchip: jaguar-rk3588: enable SARADC and derivatives adc: add missing depends on ADC for controller drivers button: add missing ADC dependency for BUTTON_ADC rockchip: boot_mode: fix rockchip_dnl_key_pressed requiring ADC support William Wu (1): regulator: rk8xx: fix SWITCH enable on RK809 arch/arm/mach-rockchip/boot_mode.c | 4 + cmd/pmic.c | 4 +- configs/jaguar-rk3588_defconfig | 11 +- drivers/adc/Kconfig | 4 + drivers/adc/rockchip-saradc.c | 202 +++++++++++-- drivers/button/Kconfig | 1 + drivers/power/pmic/Kconfig | 2 +- drivers/power/pmic/rk8xx.c | 85 ++++++ drivers/power/regulator/rk8xx.c | 595 ++++++++++++++++++++++++++++++++++--- drivers/spi/rk_spi.c | 20 +- include/power/rk8xx_pmic.h | 21 +- 11 files changed, 874 insertions(+), 75 deletions(-) --- base-commit: dcf1b0a056cc81dc268d449c6e689fe80ca688ae change-id: 20240212-rk3588-saradc-ab0a9bda9306 Best regards, -- Quentin Schulz <quentin.schulz(a)theobroma-systems.com>

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[PATCH 0/3] mux: Drop usage of "u-boot,mux-autoprobe"
by Roger Quadros 29 Feb '24

29 Feb '24

Hi, MUX driver should autoprobe if the device tree has "idle-states" property. Drop using the custom "u-boot,mux-autoprobe" property in TI device trees. cheers, -roger Roger Quadros (3): mux: autoprobe if "idle-states" present in device tree arm: dts: k3-u-boot: Drop usage of "u-boot,mux-autoprobe" arm: dts: k3-u-boot: Add missing "bootph-all" property to MUX nodes. arch/arm/dts/k3-am642-sk-u-boot.dtsi | 2 +- arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi | 2 -- arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 4 ++-- arch/arm/dts/k3-j721e-sk-u-boot.dtsi | 4 ++-- drivers/mux/mux-uclass.c | 3 ++- 5 files changed, 7 insertions(+), 8 deletions(-) base-commit: 28760ce8640ff6266bd1c1c568a4a231576f3919 -- 2.34.1

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[NEXT] Pull request efi-next-2024-02-28
by Heinrich Schuchardt 29 Feb '24

29 Feb '24

Dear Tom, The following changes for the *next* branch since commit d49fa3defa50c6d3f04acbb52fd486c13c14ab6a: Prepare v2024.04-rc3 (2024-02-26 21:23:36 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-efi.git tags/efi-next-2024-02-28 for you to fetch changes up to 97da9aea78ab71e92778649bf9d1071f30e260f0: arm: separate .data and .text sections of EFI binaries (2024-02-28 14:39:27 +0100) Gitlab CI showed no issues: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/19761 ---------------------------------------------------------------- Pull request efi-next-2024-02-28 * set IMAGE_DLLCHARACTERISTICS_NX_COMPAT in EFI binaries * provide SBI based runtime system reset * page align EFI binary section on ARMv7 * separate .data and .text sections of EFI binaries on ARMv7 ---------------------------------------------------------------- Heinrich Schuchardt (4): efi_loader: set IMAGE_DLLCHARACTERISTICS_NX_COMPAT efi_driver: provide SBI based runtime system reset arm: page align EFI binary section arm: separate .data and .text sections of EFI binaries arch/arm/lib/crt0_aarch64_efi.S | 4 ++++ arch/arm/lib/crt0_arm_efi.S | 48 +++++++++++++++++++++++++++++++--------- arch/arm/lib/elf_arm_efi.lds | 28 +++++++++++++++++------ arch/riscv/lib/crt0_riscv_efi.S | 4 ++++ include/asm-generic/pe.h | 3 +++ lib/efi_driver/Makefile | 1 + lib/efi_driver/efi_reset_riscv.c | 29 ++++++++++++++++++++++++ lib/efi_loader/Kconfig | 2 +- 8 files changed, 100 insertions(+), 19 deletions(-) create mode 100644 lib/efi_driver/efi_reset_riscv.c

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[PATCH v3 0/8] Add i2c and reset support for Renesas RZ/G2L
by Paul Barker 28 Feb '24

28 Feb '24

This patch series extends the support for the Renesas RZ/G2L SMARC EVK board (based on the R9A07G044L2 SoC) to include the following new features: * I2C bus support, including automatic deblocking if SDA is stuck low due to another device on the board. * Basic PMIC support, with the ability to read, write & dump PMIC registers. * Support for requesting system reset (SYSRESET_COLD or SYSRESET_POWER) via the PMIC. Along the way we fix the CPG driver to confirm all clock & reset changes before returning, and update the device tree to align with Linux 6.7. This series has been tested on RZ/G2L hardware, and the full u-boot GitLab CI pipeline has been executed in our internal GitLab instance. Changes from v2: * Split the addition of RZ/G2L PMIC support into two patches: one to add the PMIC driver and one to modify the defconfig. * Collected Marek's Reviewed-by tags. Changes from v1: * Rebased on U-Boot v2024.04-rc2 and re-tested. * Sync with Linux v6.7 instead of v6.6. * Add raa215300_bind() as a stub in patch 4. * Split up the addition of sysreset support into 3 patches: patch 5 adds the driver, patch 6 binds it with the pmic driver and patch 7 enables sysreset for the RZ/G2L. Paul Barker (8): clk: renesas: Confirm all clock & reset changes on RZ/G2L arm: dts: rzg2l: Sync with Linux v6.7 i2c: rzg2l: Add I2C driver for RZ/G2L family pmic: Add Renesas RAA215300 PMIC driver board: rzg2l: Enable access to Renesas RAA215300 PMIC sysreset: Support reset via Renesas RAA215300 PMIC pmic: raa215300: Bind sysreset driver board: rzg2l: Support reset via Renesas RAA215300 PMIC arch/arm/dts/r9a07g044.dtsi | 16 +- arch/arm/dts/r9a07g044l2-smarc.dts | 21 + arch/arm/dts/rz-smarc-common.dtsi | 18 +- arch/arm/dts/rzg2l-smarc-pinfunction.dtsi | 20 + arch/arm/dts/rzg2l-smarc-som.dtsi | 22 +- arch/arm/dts/rzg2l-smarc.dtsi | 43 +- arch/arm/mach-rmobile/Kconfig | 1 + board/renesas/rzg2l/rzg2l.c | 8 - configs/renesas_rzg2l_smarc_defconfig | 7 + drivers/clk/renesas/rzg2l-cpg.c | 17 +- drivers/i2c/Kconfig | 7 + drivers/i2c/Makefile | 1 + drivers/i2c/rz_riic.c | 624 ++++++++++++++++++++++ drivers/power/pmic/Kconfig | 9 + drivers/power/pmic/Makefile | 1 + drivers/power/pmic/raa215300.c | 50 ++ drivers/sysreset/Kconfig | 6 + drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_raa215300.c | 58 ++ 19 files changed, 896 insertions(+), 34 deletions(-) create mode 100644 drivers/i2c/rz_riic.c create mode 100644 drivers/power/pmic/raa215300.c create mode 100644 drivers/sysreset/sysreset_raa215300.c base-commit: d49fa3defa50c6d3f04acbb52fd486c13c14ab6a -- 2.44.0

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[PATCH] mtd: spi-nor: ids: Enable Octal read for IS25LX512M flash
by Tejas Bhumkar 28 Feb '24

28 Feb '24

The addition of the "SPI_NOR_OCTAL_READ" flag enables the use of 7Ch 4-byte octal output fast read command for IS25LX512M flash. Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar(a)amd.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 4e83b8c94c..8786b6f862 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -241,7 +241,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256, SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, { INFO("is25lx512", 0x9d5a1a, 0, 64 * 1024, 1024, - SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_TB) }, + SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_TB) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */ -- 2.37.6

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