December 2024 - U-Boot

[PATCH] net: rswitch: Simplify code using clrsetbits_le32()
by Marek Vasut 19 Dec '24

19 Dec '24

Use clrsetbits_le32() to make this complicated construct simpler. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> Cc: Ramon Fried <rfried.dev(a)gmail.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: u-boot(a)lists.denx.de --- drivers/net/rswitch.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c index 259d584ac98..9ebe1e97bd1 100644 --- a/drivers/net/rswitch.c +++ b/drivers/net/rswitch.c @@ -426,9 +426,9 @@ static int rswitch_mii_read_c45(struct mii_dev *miidev, int phyad, int devad, in rswitch_etha_change_mode(priv, EAMC_OPC_CONFIG); /* Enable Station Management clock */ - reg = readl(etha->addr + MPIC); - reg &= ~MPIC_PSMCS_MASK & ~MPIC_PSMHT_MASK; - writel(reg | MPIC_MDC_CLK_SET, etha->addr + MPIC); + clrsetbits_le32(etha->addr + MPIC, + MPIC_PSMCS_MASK | MPIC_PSMHT_MASK, + MPIC_MDC_CLK_SET); /* Set Station Management Mode : Clause 45 */ setbits_le32(etha->addr + MPSM, MPSM_MFF_C45); @@ -458,9 +458,9 @@ int rswitch_mii_write_c45(struct mii_dev *miidev, int phyad, int devad, int rega rswitch_etha_change_mode(priv, EAMC_OPC_CONFIG); /* Enable Station Management clock */ - reg = readl(etha->addr + MPIC); - reg &= ~MPIC_PSMCS_MASK & ~MPIC_PSMHT_MASK; - writel(reg | MPIC_MDC_CLK_SET, etha->addr + MPIC); + clrsetbits_le32(etha->addr + MPIC, + MPIC_PSMCS_MASK | MPIC_PSMHT_MASK, + MPIC_MDC_CLK_SET); /* Set Station Management Mode : Clause 45 */ setbits_le32(etha->addr + MPSM, MPSM_MFF_C45); -- 2.45.2

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[PATCH v5 0/8] Add Starfive JH7110 Cadence USB driver
by Minda Chen 19 Dec '24

19 Dec '24

Add Starfive JH7110 Cadence USB driver and related PHY driver. So the codes can be used in visionfive2 and star64 7110 board. The driver is almost the same with kernel driver. Test with Star64 JH7110 board USB 3.0 + USB 2.0 host. The code can work. - Star64 using USB 3.0 and USB 2.0 host must add below board dts setting. (Vbus bin setting. If usb host in Other JH7110 board vbus pin is not GPIO, don't require to set this) 1. usb pin setting usb_pins: usb0-0 { driver-vbus-pin { pinmux = <GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE)>; bias-disable; input-disable; input-schmitt-disable; slew-rate = <0>; }; }; 2. related dts node setting(USB 3.0 host) &pcie0 { status = "disabled"; }; &pciephy0 { starfive,sys-syscon = <&sys_syscon>; starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>; status = "okay"; }; &usb0 { pinctrl-names = "default"; pinctrl-0 = <&usb_pins>; dr_mode = "host"; status = "okay"; }; &usb_cdns3 { phys = <&usbphy0>, <&pciephy0>; phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy"; }; - If other board is USB 2.0 host, Just set dr mode is OKay. &usb0 { dr_mode = "host"; status = "okay"; }; - previous version v1: https://patchwork.ozlabs.org/project/uboot/cover/20240504150358.19600-1-min… v2: https://patchwork.ozlabs.org/project/uboot/cover/20240704055014.55117-1-min… v3: https://patchwork.ozlabs.org/project/uboot/cover/20240719013822.101374-1-mi… v4: https://patchwork.ozlabs.org/project/uboot/cover/20240829013058.6178-1-mind… - patch description. patch1: Add set phy mode function in cdns3 core driver which is used by Starfive JH7110. patch2-3: USB and PCIe 2.0 (usb 3.0) PHY drivier patch4: Cadence USB wrapper driver. patch5: Add JH7110 USB default overcurrent pin. patch6-7 dts, config update. patch8: MAINTAINERS update - change: v5: - patch 2-4 format changed. - For pareparing enable OF_UPSTREAM, patch4 get the dr mode from parent device dts node not the cdns core device dts. - patch2 add a common usb syscon setting headfile. - delete v4 patch8 and the star64 dts setting can be setting int star64 board dts configuration if the OF_UPSTREAM is enable. v4: - patch 2 Add usb split setting, default set USB 2.0 only. - patch 5 move to spl stage. - Add a new patch 8 for star64 board usb host, vbus pin setting and usb 3.0 v3: - patch 1 Move the added code to cdns3_drd_update_mode(). - patch 1-4 correct the code format.(follow Rogers's comments.) - patch 3 using regmap_field. v2: - patch 1 Move the added code to cdns3_core_init_role(). Must set PHY mode before calling cdns3 role start function. - patch 1-4 correct the code format.(follow Marek's comments.) - patch 2 Add set 125M clock in PHY init function. - Add new patch5. Minda Chen (8): usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode() phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver usb: cdns: starfive: Add cdns USB driver spl: starfive: visionfive2: Disable USB overcurrent pin by default. configs: starfive: Add visionfive2 cadence USB configuration dts: starfive: Add JH7110 Cadence USB dts node MAINTAINERS: Update Starfive visionfive2 maintain files. .../dts/jh7110-starfive-visionfive-2.dtsi | 5 + arch/riscv/dts/jh7110.dtsi | 53 ++++ arch/riscv/include/asm/arch-jh7110/gpio.h | 5 + board/starfive/visionfive2/MAINTAINERS | 2 + board/starfive/visionfive2/spl.c | 3 + configs/starfive_visionfive2_defconfig | 10 + drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/starfive/Kconfig | 21 ++ drivers/phy/starfive/Makefile | 7 + drivers/phy/starfive/phy-jh7110-pcie.c | 239 ++++++++++++++++++ drivers/phy/starfive/phy-jh7110-usb-syscon.h | 9 + drivers/phy/starfive/phy-jh7110-usb2.c | 162 ++++++++++++ drivers/usb/cdns3/Kconfig | 7 + drivers/usb/cdns3/Makefile | 2 + drivers/usb/cdns3/cdns3-starfive.c | 183 ++++++++++++++ drivers/usb/cdns3/core.c | 3 + drivers/usb/cdns3/drd.c | 14 + 18 files changed, 727 insertions(+) create mode 100644 drivers/phy/starfive/Kconfig create mode 100644 drivers/phy/starfive/Makefile create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c create mode 100644 drivers/phy/starfive/phy-jh7110-usb-syscon.h create mode 100644 drivers/phy/starfive/phy-jh7110-usb2.c create mode 100644 drivers/usb/cdns3/cdns3-starfive.c base-commit: c530f6079c70219e01022142b404bf8a6b572366 -- 2.17.1

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imx8mp / Can't support legacy image
by Elmar Psilog 19 Dec '24

19 Dec '24

After switching to a new RAM I am suddenly facing an issue that Uboot/SPL stops with: U-Boot SPL 2021.04-00020-g2b6bb90793 (Jan 25 2022 - 11:47:36 +0100) Normal Boot WDT: Started with servicing (180s timeout) Trying to boot from BOOTROM image offset 0x0, pagesize 0x200, ivt offset 0x0 Can't support legacy image SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### We running a imx8mp board where emmc is preflashed with an Uboot and environment. Originally the board was equipped with 1GB RAM. We switched to 2GB RAM of another supplier. The board still boots fine. That was important, as no new preflashed emmcs are needed. Of course (once booted) we reflash an uboot that recognizes full 2GB RAM and have adapted training data. Now we switched to another supplier and have this issue above. So far I can see RAM init was successful (no errors here), so I am wondering what might be the reason for this fail? All I found points to some ATF stuff, but there is no change?!? What does the RAM deal with this? Additional weird: When booting the uboot with 2GB support (which is 2023.04) via uuu it seems not to read the environment and reports: Loading Environment from nowhere... OK .. although all parameters handling ENV (position, content, settings) keep same in this newer uboot. Ok, there is a mix of newer uboot and environment that is saved with old uboot but that shouldn't be a problem? For us this is a pain, as we have a lot of boards already soldered with this preflashed emmc that doesn't boot new RAMs and has to be handled with UUU. I would feel better to understand the problem here... And one important question for the future: How likely it is that switch of RAM needs new training data? Or isn't that more a board specific thing (if parameters like size keeps same)? Thanks for any hints, and Merry Christmas next!

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[PATCH v3 0/3] mtd: nand: raw: Collected improvements
by Alexander Dahl 19 Dec '24

19 Dec '24

Hello everyone, while working on NAND flash support for a custom board based on the at91 SAM9X60 SoC I stumbled over some issues in the raw nand subsystem. Some trivial patches of previous iterations of this series were already applied. Patch 1 introduces a new subcommand for the new atmel nand controller driver. Patch 2 introduces a new subcommand for the nand command to override ONFI timing mode. Both are are for debugging purposes only and thus optional, and need to be enabled through menu. Both helped me a lot when investigating issues. Patch 3 is a fix carried over from at91bootstrap for faster at91 SoCs with certain raw NAND chips. Series is based on post v2024.04 master now. Greets Alex v3: - 4 patches removed, applied to master - other 2 patches from v2 unchanged, still under test - added new third patch with a fix for atmel nand timings (forgot to send that with v2) v2: Link: https://lore.kernel.org/u-boot/20240320090214.40465-1-ada@thorsis.com/ - rebased on recent next - collected tags - improved patch 4 after feedback from Mihai - added new patch 5 with another help text fix - added new patch 6 with a new debug command - reworded cover letter v1: Link: https://lore.kernel.org/u-boot/20240307091014.39796-1-ada@thorsis.com/ See per patch changes in patches for more detailed changes. Alexander Dahl (3): mtd: nand: raw: atmel: Introduce optional debug commands cmd: nand: Add new optional sub-command 'onfi' mtd: nand: raw: atmel: Fix pulse read timing for certain NAND flashes cmd/Kconfig | 10 + cmd/nand.c | 61 ++++ drivers/mtd/nand/raw/Kconfig | 9 + drivers/mtd/nand/raw/atmel/nand-controller.c | 308 ++++++++++++++++++- drivers/mtd/nand/raw/nand_base.c | 2 +- include/linux/mtd/rawnand.h | 1 + 6 files changed, 386 insertions(+), 5 deletions(-) base-commit: b03b49046af5dfca599d2ce8f0aafed89b97aa91 -- 2.39.2

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[PATCH v2] mtd: spi-nor: Fix the spi_nor_read() when config SPI_STACKED_PARALLEL is enabled
by Venkatesh Yadav Abbarapu 19 Dec '24

19 Dec '24

Update the spi_nor_read() function only for parallel configuration when config SPI_STACKED_PARALLEL is enabled and keep the default code as is. For parallel configurations fix the read issue for 4byte address width by passing the entire length to the read function, split the memory of 16MB size banks only when the address width is 3byte. Also update the size when the configuration is stacked. Fixes: 5d40b3d384 ("mtd: spi-nor: Add parallel and stacked memories support") Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- Changes in v2: - Update the nor read for parallel configuration and for other case keep the code as is. - Fixed the commit description. - Tested the changes with s25fl128s flash Zynq> sf probe 0 0 0 SF: Detected s25fl128s with page size 256 Bytes, erase size 64 KiB, total 16 MiB Zynq> time sf erase 0x0 0x1000000;mw.b 0x8000 aabbccdd 0x1000000;time sf write 0x8000 0x0 0x1000000;mw.b 0x8008000 0x0 0x1000000;time sf read 0x8008000 0x0 0x1000000;cmp.b 0x8000 0x8008000 0x1000000 SF: 16777216 bytes @ 0x0 Erased: OK time: 32.464 seconds device 0 whole chip SF: 16777216 bytes @ 0x0 Written: OK time: 15.515 seconds device 0 whole chip SF: 16777216 bytes @ 0x0 Read: OK time: 1.557 seconds Total of 16777216 byte(s) were the same --- drivers/mtd/spi/spi-nor-core.c | 50 ++++++++++++++++++++++------------ 1 file changed, 33 insertions(+), 17 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index ec841fb13b..8d7087b5c9 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1140,7 +1140,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) nor->spi->flags &= ~SPI_XFER_U_PAGE; } #ifdef CONFIG_SPI_FLASH_BAR - ret = write_bar(nor, addr); + ret = write_bar(nor, offset); if (ret < 0) goto erase_err; #endif @@ -1152,7 +1152,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { ret = spi_nor_erase_chip(nor); } else { - ret = spi_nor_erase_sector(nor, addr); + ret = spi_nor_erase_sector(nor, offset); } if (ret < 0) goto erase_err; @@ -1578,8 +1578,8 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, struct spi_nor *nor = mtd_to_spi_nor(mtd); int ret; loff_t offset = from; - u32 read_len = 0; u32 rem_bank_len = 0; + u32 stack_shift = 0; u8 bank; bool is_ofst_odd = false; @@ -1593,18 +1593,23 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, } while (len) { - bank = (u32)from / SZ_16M; - if (nor->flags & SNOR_F_HAS_PARALLEL) - bank /= 2; - - rem_bank_len = SZ_16M * (bank + 1); - if (nor->flags & SNOR_F_HAS_PARALLEL) - rem_bank_len *= 2; - rem_bank_len -= from; - + size_t read_len = len; offset = from; + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + if (nor->addr_width == 3) { + bank = (u32)from / SZ_16M; + if (nor->flags & SNOR_F_HAS_PARALLEL) + bank /= 2; + + rem_bank_len = SZ_16M * (bank + 1); + if (nor->flags & SNOR_F_HAS_PARALLEL) + rem_bank_len *= 2; + rem_bank_len -= from; + } + if (nor->flags & SNOR_F_HAS_STACKED) { + stack_shift = 1; if (offset >= (mtd->size / 2)) { offset = offset - (mtd->size / 2); nor->spi->flags |= SPI_XFER_U_PAGE; @@ -1613,20 +1618,31 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, } } + if (nor->addr_width == 4) + rem_bank_len = (mtd->size >> stack_shift) - offset; + if (nor->flags & SNOR_F_HAS_PARALLEL) offset /= 2; + } #ifdef CONFIG_SPI_FLASH_BAR + u32 remain_len; + ret = write_bar(nor, offset); if (ret < 0) return log_ret(ret); -#endif - - if (len < rem_bank_len) + remain_len = (SZ_16M * (nor->bank_curr + 1)) - offset; + if (len < remain_len) read_len = len; else - read_len = rem_bank_len; - + read_len = remain_len; +#endif + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + if (len < rem_bank_len) + read_len = len; + else + read_len = rem_bank_len; + } if (read_len == 0) return -EIO; -- 2.34.1

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[PATCH] powerpc: Support using upstream devicetrees
by J. Neuschäfer via B4 Relay 19 Dec '24

19 Dec '24

From: "J. Neuschäfer" <j.ne(a)posteo.net> For new PowerPC developments, it will be useful to borrow devicetrees from Linux. This patch makes it possible. Signed-off-by: J. Neuschäfer <j.ne(a)posteo.net> --- This may seem hypothetical, but I'm working on a new U-Boot port for a PowerPC board. --- dts/upstream/src/powerpc/Makefile | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/dts/upstream/src/powerpc/Makefile b/dts/upstream/src/powerpc/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..721ec5cb229e2a8ae57e90c9407f86054fcb7ad9 --- /dev/null +++ b/dts/upstream/src/powerpc/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ + +include $(srctree)/scripts/Makefile.dts + +# Add any required device tree compiler flags here +DTC_FLAGS += --- base-commit: 98dd010b311e68b8398428cadf56a6381f7de202 change-id: 20241129-upstream-dts-9a1eb4524b53 Best regards, -- J. Neuschäfer <j.ne(a)posteo.net>

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[PATCH] phy: don't spam console if phys property is absent in device node
by Roger Quadros 19 Dec '24

19 Dec '24

In generic_phy_get_bulk(), if 'phys' property is absent in the device node then it is not an error condition. Change print message verbosity to debug to avoid spamming console in such cases. Signed-off-by: Roger Quadros <rogerq(a)kernel.org> --- drivers/phy/phy-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c index 777d952b041..714be123856 100644 --- a/drivers/phy/phy-uclass.c +++ b/drivers/phy/phy-uclass.c @@ -415,7 +415,7 @@ int generic_phy_get_bulk(struct udevice *dev, struct phy_bulk *bulk) if (!dev_read_prop(dev, "phys", NULL)) { phydev = dev->parent; if (!dev_read_prop(phydev, "phys", NULL)) { - pr_err("%s : no phys property\n", __func__); + pr_debug("%s : no phys property\n", __func__); return 0; } } --- base-commit: 3073246d1be682071d8b3d07d06c2484907aed60 change-id: 20241203-nophys-0b539d183a16 Best regards, -- Roger Quadros <rogerq(a)kernel.org>

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[PATCH v2] verdin-am62: fix FASTBOOT_BUF_ADDR and FASTBOOT_BUF_SIZE
by Hiago De Franco 19 Dec '24

19 Dec '24

From: Hiago De Franco <hiago.franco(a)toradex.com> The current value of CONFIG_FASTBOOT_BUF_ADDR is incorrect for hardware with 512MB and 1GB of RAM. The RAM address ranges for these devices are: - 512MB: - Start: 0x80000000 - End: 0xA0000000 - 1GB: - Start: 0x80000000 - End: 0xC0000000 The current buffer address makes fastboot downloads work only on hardware with 2GB of RAM. To fix this issue: 1. Lower CONFIG_FASTBOOT_BUF_ADDR to 0x88200000. This makes the buffer to be equal ot CONFIG_SYS_LOAD_ADDR, which is a safe address to download files using fastboot. 2. Reduce the size of the download buffer to 128MB, avoiding overlaps with RAMDISK_ADDR_R. This is a good enough value for individual downloads. These changes make fastboot downloads work with 512MB and 1GB devices. Fixes: defe30a78b76 ("verdin-am62: add DFU, USB and UUU fastboot support") Signed-off-by: Hiago De Franco <hiago.franco(a)toradex.com> --- configs/verdin-am62_a53_defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig index 49fb9790e295..fc9ffa0f392b 100644 --- a/configs/verdin-am62_a53_defconfig +++ b/configs/verdin-am62_a53_defconfig @@ -122,8 +122,8 @@ CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 -CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 +CONFIG_FASTBOOT_BUF_ADDR=0x88200000 +CONFIG_FASTBOOT_BUF_SIZE=0x8000000 CONFIG_FASTBOOT_UUU_SUPPORT=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_GPIO_HOG=y -- 2.39.5

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[PATCH v2 0/7] efi: Start to chip away at the EFI workaround
by Simon Glass 19 Dec '24

19 Dec '24

At present there is a function, efi_set_bootdev(), which is used in various places to tell the EFI loader which device a file came from. With bootstd, this information is available in the bootflow. This little series provides a way for bootstd to provide the bootflow to the EFI loader, so that it is able to select the correct paths. For now only the EFI bootmeth is updated. Changes in v2: - Adjust argument ordering for efi_run_image() - Use efi_loader tag instead of efi - Drop unnecessary path removal - Fix 'require' typo - Move calculation of dev-name into a separate function - Add new patch to support PXE booting Simon Glass (7): efi_loader: Refactor device and image paths into a function efi_loader: Make efi_run_image() static efi_loader: Update efi_run_image() to accept image and device path efi_loader: Add a version of efi_binary_run() with more parameters efi_loader: Move the fallback code from efi_run_image() efi_loader: Pass in the required parameters from EFI bootmeth bootmeth_efi: Support PXE booting boot/bootmeth_efi.c | 64 +--------- include/efi_loader.h | 10 ++ lib/efi_loader/efi_bootbin.c | 239 ++++++++++++++++++++++++++--------- 3 files changed, 189 insertions(+), 124 deletions(-) -- 2.34.1

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[PATCH v1 0/1] SoCFPGA: Add watchdog mode setting for Agilex 5
by muhammad.hazim.izzat.zamri＠intel.com 19 Dec '24

19 Dec '24

From: Muhammad Hazim Izzat Zamri <muhammad.hazim.izzat.zamri(a)intel.com> This patch is to introduce another watchdog mode setting in Agilex 5 as additional watchdog4 has been introduced. This is to enable the debug mode when the CPU is paused by the user. This patch has been tested on Agilex 5 devkit with QSPI boot (UBI/UBIFS) and RAM boot (TFTP & ARM DS debugger). Muhammad Hazim Izzat Zamri (1): arm: socfpga:agilex5: Fix system manager watchdog mode setting arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1

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