November 2024 - U-Boot

[PATCH] mtd: spi-nor-core: Fixup SNOR_F_IO_MODE_EN_VOLATILE for MT35X
by Prasanth Babu Mantena 25 Nov '24

25 Nov '24

From: Vaishnav Achath <vaishnav.a(a)ti.com> MT35XU512ABA has only BFPT and 4-Byte Address Instruction Table in SFDP. commit bebdc237507c ("mtd: spi-nor: Parse SFDP SCCR Map") added checks in spi_nor_octal_dtr_enable() to bail out if the 22nd DWORD in SCCR does not indicate DTR Octal Mode Enable, since MT35XU512ABA device supports octal DTR mode, add this property in SFDP fixup. Signed-off-by: Vaishnav Achath <vaishnav.a(a)ti.com> Signed-off-by: Prasanth Babu Mantena <p-mantena(a)ti.com> --- Test results : https://gist.github.com/PrasanthBabuMantena/678cbd7a230a4e2d19e22d20dfeb1235 drivers/mtd/spi/spi-nor-core.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index ec841fb13bd..6364d91fac0 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -4109,6 +4109,12 @@ static void mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor, params->rdsr_dummy = 8; params->rdsr_addr_nbytes = 0; + /* + * SCCR Map 22nd DWORD does not indicate DTR Octal Mode Enable + * for MT35XU512ABA but is actually supported by device. + */ + nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE; + /* * The BFPT quad enable field is set to a reserved value so the quad * enable function is ignored by spi_nor_parse_bfpt(). Make sure we -- 2.34.1

2 1

[PATCH v2] toradex: tdx-cfg-block: rework modules pid4 handling
by Vitor Soares 25 Nov '24

25 Nov '24

From: Vitor Soares <vitor.soares(a)toradex.com> The module pid4 currently corresponds to the index of the toradex_module array. If a new pid4 is introduced that does not follow the sequence of the previous entries, it will create a gap in the array. To address this, embed pid4 within the toradex_som structure and implement a function to retrieve the index corresponding to pid4. Signed-off-by: Vitor Soares <vitor.soares(a)toradex.com> --- v1->v2: - Fix incorrect PID4 print when creating config block in interactive mode. board/toradex/common/tdx-cfg-block.c | 207 ++++++++++++++------------- board/toradex/common/tdx-cfg-block.h | 2 + board/toradex/common/tdx-common.c | 4 +- 3 files changed, 116 insertions(+), 97 deletions(-) diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index a6e3c6afae80..0fb49fcdfbf6 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -70,97 +70,95 @@ struct toradex_hw tdx_car_hw_tag; #define TARGET_IS_ENABLED(x) IS_ENABLED(CONFIG_TARGET_ ## x) const struct toradex_som toradex_modules[] = { - [0] = { "UNKNOWN MODULE", 0 }, - [1] = { "Colibri PXA270 312MHz", 0 }, - [2] = { "Colibri PXA270 520MHz", 0 }, - [3] = { "Colibri PXA320 806MHz", 0 }, - [4] = { "Colibri PXA300 208MHz", 0 }, - [5] = { "Colibri PXA310 624MHz", 0 }, - [6] = { "Colibri PXA320IT 806MHz", 0 }, - [7] = { "Colibri PXA300 208MHz XT", 0 }, - [8] = { "Colibri PXA270 312MHz", 0 }, - [9] = { "Colibri PXA270 520MHz", 0 }, - [10] = { "Colibri VF50 128MB", TARGET_IS_ENABLED(COLIBRI_VF) }, - [11] = { "Colibri VF61 256MB", TARGET_IS_ENABLED(COLIBRI_VF) }, - [12] = { "Colibri VF61 256MB IT", TARGET_IS_ENABLED(COLIBRI_VF) }, - [13] = { "Colibri VF50 128MB IT", TARGET_IS_ENABLED(COLIBRI_VF) }, - [14] = { "Colibri iMX6S 256MB", TARGET_IS_ENABLED(COLIBRI_IMX6) }, - [15] = { "Colibri iMX6DL 512MB", TARGET_IS_ENABLED(COLIBRI_IMX6) }, - [16] = { "Colibri iMX6S 256MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) }, - [17] = { "Colibri iMX6DL 512MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) }, - [18] = { "UNKNOWN MODULE", 0 }, - [19] = { "UNKNOWN MODULE", 0 }, - [20] = { "Colibri T20 256MB", TARGET_IS_ENABLED(COLIBRI_T20) }, - [21] = { "Colibri T20 512MB", TARGET_IS_ENABLED(COLIBRI_T20) }, - [22] = { "Colibri T20 512MB IT", TARGET_IS_ENABLED(COLIBRI_T20) }, - [23] = { "Colibri T30 1GB", TARGET_IS_ENABLED(COLIBRI_T30) }, - [24] = { "Colibri T20 256MB IT", TARGET_IS_ENABLED(COLIBRI_T20) }, - [25] = { "Apalis T30 2GB", TARGET_IS_ENABLED(APALIS_T30) }, - [26] = { "Apalis T30 1GB", TARGET_IS_ENABLED(APALIS_T30) }, - [27] = { "Apalis iMX6Q 1GB", TARGET_IS_ENABLED(APALIS_IMX6) }, - [28] = { "Apalis iMX6Q 2GB IT", TARGET_IS_ENABLED(APALIS_IMX6) }, - [29] = { "Apalis iMX6D 512MB", TARGET_IS_ENABLED(APALIS_IMX6) }, - [30] = { "Colibri T30 1GB IT", TARGET_IS_ENABLED(COLIBRI_T30) }, - [31] = { "Apalis T30 1GB IT", TARGET_IS_ENABLED(APALIS_T30) }, - [32] = { "Colibri iMX7S 256MB", TARGET_IS_ENABLED(COLIBRI_IMX7) }, - [33] = { "Colibri iMX7D 512MB", TARGET_IS_ENABLED(COLIBRI_IMX7) }, - [34] = { "Apalis TK1 2GB", TARGET_IS_ENABLED(APALIS_TK1) }, - [35] = { "Apalis iMX6D 1GB IT", TARGET_IS_ENABLED(APALIS_IMX6) }, - [36] = { "Colibri iMX6ULL 256MB", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) }, - [37] = { "Apalis iMX8QM 4GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) }, - [38] = { "Colibri iMX8QXP 2GB WB IT", TARGET_IS_ENABLED(COLIBRI_IMX8X) }, - [39] = { "Colibri iMX7D 1GB", TARGET_IS_ENABLED(COLIBRI_IMX7) }, - [40] = { "Colibri iMX6ULL 512MB WB IT", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) }, - [41] = { "Colibri iMX7D 512MB EPDC", TARGET_IS_ENABLED(COLIBRI_IMX7) }, - [42] = { "Apalis TK1 4GB", TARGET_IS_ENABLED(APALIS_TK1) }, - [43] = { "Colibri T20 512MB IT SETEK", TARGET_IS_ENABLED(COLIBRI_T20) }, - [44] = { "Colibri iMX6ULL 512MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) }, - [45] = { "Colibri iMX6ULL 512MB WB", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) }, - [46] = { "Apalis iMX8QXP 2GB WB IT", 0 }, - [47] = { "Apalis iMX8QM 4GB IT", TARGET_IS_ENABLED(APALIS_IMX8) }, - [48] = { "Apalis iMX8QP 2GB WB", TARGET_IS_ENABLED(APALIS_IMX8) }, - [49] = { "Apalis iMX8QP 2GB", TARGET_IS_ENABLED(APALIS_IMX8) }, - [50] = { "Colibri iMX8QXP 2GB IT", TARGET_IS_ENABLED(COLIBRI_IMX8X) }, - [51] = { "Colibri iMX8DX 1GB WB", TARGET_IS_ENABLED(COLIBRI_IMX8X) }, - [52] = { "Colibri iMX8DX 1GB", TARGET_IS_ENABLED(COLIBRI_IMX8X) }, - [53] = { "Apalis iMX8QXP 2GB ECC IT", 0 }, - [54] = { "Apalis iMX8DXP 1GB", TARGET_IS_ENABLED(APALIS_IMX8) }, - [55] = { "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, - [56] = { "Verdin iMX8M Nano Quad 1GB WB", 0 }, - [57] = { "Verdin iMX8M Mini DualLite 1GB", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, - [58] = { "Verdin iMX8M Plus Quad 4GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, - [59] = { "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, - [60] = { "Verdin iMX8M Mini DualLite 1GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, - [61] = { "Verdin iMX8M Plus Quad 2GB", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, - [62] = { "Colibri iMX6ULL 1GB IT", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) }, - [63] = { "Verdin iMX8M Plus Quad 4GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, - [64] = { "Verdin iMX8M Plus Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, - [65] = { "Verdin iMX8M Plus QuadLite 1GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, - [66] = { "Verdin iMX8M Plus Quad 8GB WB", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, - [67] = { "Apalis iMX8QM 8GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) }, - [68] = { "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, - [69] = { "Verdin AM62 Quad 1GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, - [70] = { "Verdin iMX8M Plus Quad 8GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, - [71] = { "Verdin AM62 Solo 512MB", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, - [72] = { "Verdin AM62 Solo 512MB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, - [73] = { "Verdin AM62 Dual 1GB ET", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, - [74] = { "Verdin AM62 Dual 1GB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, - [75] = { "Verdin AM62 Dual 1GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, - [76] = { "Verdin AM62 Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, - [77] = { "Colibri iMX6S 256MB", TARGET_IS_ENABLED(COLIBRI_IMX6) }, - [78] = { "Colibri iMX6S 256MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) }, - [79] = { "Colibri iMX6DL 512MB", TARGET_IS_ENABLED(COLIBRI_IMX6) }, - [80] = { "Colibri iMX6DL 512MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) }, - [81] = { "Colibri iMX7D 512MB", TARGET_IS_ENABLED(COLIBRI_IMX7) }, - [82] = { "Apalis iMX6D 512MB", TARGET_IS_ENABLED(APALIS_IMX6) }, - [83] = { "Apalis iMX6Q 1GB", TARGET_IS_ENABLED(APALIS_IMX6) }, - [84] = { "Apalis iMX6D 1GB IT", TARGET_IS_ENABLED(APALIS_IMX6) }, - [85] = { "Apalis iMX6Q 2GB IT", TARGET_IS_ENABLED(APALIS_IMX6) }, - [86] = { "Verdin iMX8M Mini DualLite 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, - [87] = { "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, - [88] = { "Aquila AM69 Octa 32GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, - [89] = { "Verdin iMX95 Hexa 16GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX95) }, - [90] = { "Verdin iMX8M Mini Quad 4GB WB ET", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + { 0, "UNKNOWN MODULE", 0 }, + { COLIBRI_PXA270_V1_312MHZ, "Colibri PXA270 312MHz", 0 }, + { COLIBRI_PXA270_V1_520MHZ, "Colibri PXA270 520MHz", 0 }, + { COLIBRI_PXA320, "Colibri PXA320 806MHz", 0 }, + { COLIBRI_PXA300, "Colibri PXA300 208MHz", 0 }, + { COLIBRI_PXA310, "Colibri PXA310 624MHz", 0 }, + { COLIBRI_PXA320_IT, "Colibri PXA320IT 806MHz", 0 }, + { COLIBRI_PXA300_XT, "Colibri PXA300 208MHz XT", 0 }, + { COLIBRI_PXA270_312MHZ, "Colibri PXA270 312MHz", 0 }, + { COLIBRI_PXA270_520MHZ, "Colibri PXA270 520MHz", 0 }, + { COLIBRI_VF50, "Colibri VF50 128MB", TARGET_IS_ENABLED(COLIBRI_VF) }, + { COLIBRI_VF61, "Colibri VF61 256MB", TARGET_IS_ENABLED(COLIBRI_VF) }, + { COLIBRI_VF61_IT, "Colibri VF61 256MB IT", TARGET_IS_ENABLED(COLIBRI_VF) }, + { COLIBRI_VF50_IT, "Colibri VF50 128MB IT", TARGET_IS_ENABLED(COLIBRI_VF) }, + { COLIBRI_IMX6S, "Colibri iMX6S 256MB", TARGET_IS_ENABLED(COLIBRI_IMX6) }, + { COLIBRI_IMX6DL, "Colibri iMX6DL 512MB", TARGET_IS_ENABLED(COLIBRI_IMX6) }, + { COLIBRI_IMX6S_IT, "Colibri iMX6S 256MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) }, + { COLIBRI_IMX6DL_IT, "Colibri iMX6DL 512MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) }, + { COLIBRI_T20_256MB, "Colibri T20 256MB", TARGET_IS_ENABLED(COLIBRI_T20) }, + { COLIBRI_T20_512MB, "Colibri T20 512MB", TARGET_IS_ENABLED(COLIBRI_T20) }, + { COLIBRI_T20_512MB_IT, "Colibri T20 512MB IT", TARGET_IS_ENABLED(COLIBRI_T20) }, + { COLIBRI_T30, "Colibri T30 1GB", TARGET_IS_ENABLED(COLIBRI_T30) }, + { COLIBRI_T20_256MB_IT, "Colibri T20 256MB IT", TARGET_IS_ENABLED(COLIBRI_T20) }, + { APALIS_T30_2GB, "Apalis T30 2GB", TARGET_IS_ENABLED(APALIS_T30) }, + { APALIS_T30_1GB, "Apalis T30 1GB", TARGET_IS_ENABLED(APALIS_T30) }, + { APALIS_IMX6Q, "Apalis iMX6Q 1GB", TARGET_IS_ENABLED(APALIS_IMX6) }, + { APALIS_IMX6Q_IT, "Apalis iMX6Q 2GB IT", TARGET_IS_ENABLED(APALIS_IMX6) }, + { APALIS_IMX6D, "Apalis iMX6D 512MB", TARGET_IS_ENABLED(APALIS_IMX6) }, + { COLIBRI_T30_IT, "Colibri T30 1GB IT", TARGET_IS_ENABLED(COLIBRI_T30) }, + { APALIS_T30_IT, "Apalis T30 1GB IT", TARGET_IS_ENABLED(APALIS_T30) }, + { COLIBRI_IMX7S, "Colibri iMX7S 256MB", TARGET_IS_ENABLED(COLIBRI_IMX7) }, + { COLIBRI_IMX7D, "Colibri iMX7D 512MB", TARGET_IS_ENABLED(COLIBRI_IMX7) }, + { APALIS_TK1_2GB, "Apalis TK1 2GB", TARGET_IS_ENABLED(APALIS_TK1) }, + { APALIS_IMX6D_IT, "Apalis iMX6D 1GB IT", TARGET_IS_ENABLED(APALIS_IMX6) }, + { COLIBRI_IMX6ULL, "Colibri iMX6ULL 256MB", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) }, + { APALIS_IMX8QM_WIFI_BT_IT, "Apalis iMX8QM 4GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) }, + { COLIBRI_IMX8QXP_WIFI_BT_IT, "Colibri iMX8QXP 2GB WB IT", TARGET_IS_ENABLED(COLIBRI_IMX8X) }, + { COLIBRI_IMX7D_EMMC, "Colibri iMX7D 1GB", TARGET_IS_ENABLED(COLIBRI_IMX7) }, + { COLIBRI_IMX6ULL_WIFI_BT_IT, "Colibri iMX6ULL 512MB WB IT", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) }, + { COLIBRI_IMX7D_EPDC, "Colibri iMX7D 512MB EPDC", TARGET_IS_ENABLED(COLIBRI_IMX7) }, + { APALIS_TK1_4GB, "Apalis TK1 4GB", TARGET_IS_ENABLED(APALIS_TK1) }, + { COLIBRI_T20_512MB_IT_SETEK, "Colibri T20 512MB IT SETEK", TARGET_IS_ENABLED(COLIBRI_T20) }, + { COLIBRI_IMX6ULL_IT, "Colibri iMX6ULL 512MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) }, + { COLIBRI_IMX6ULL_WIFI_BT, "Colibri iMX6ULL 512MB WB", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) }, + { APALIS_IMX8QXP_WIFI_BT_IT, "Apalis iMX8QXP 2GB WB IT", 0 }, + { APALIS_IMX8QM_IT, "Apalis iMX8QM 4GB IT", TARGET_IS_ENABLED(APALIS_IMX8) }, + { APALIS_IMX8QP_WIFI_BT, "Apalis iMX8QP 2GB WB", TARGET_IS_ENABLED(APALIS_IMX8) }, + { APALIS_IMX8QP, "Apalis iMX8QP 2GB", TARGET_IS_ENABLED(APALIS_IMX8) }, + { COLIBRI_IMX8QXP_IT, "Colibri iMX8QXP 2GB IT", TARGET_IS_ENABLED(COLIBRI_IMX8X) }, + { COLIBRI_IMX8DX_WIFI_BT, "Colibri iMX8DX 1GB WB", TARGET_IS_ENABLED(COLIBRI_IMX8X) }, + { COLIBRI_IMX8DX, "Colibri iMX8DX 1GB", TARGET_IS_ENABLED(COLIBRI_IMX8X) }, + { APALIS_IMX8QXP, "Apalis iMX8QXP 2GB ECC IT", 0 }, + { APALIS_IMX8DXP, "Apalis iMX8DXP 1GB", TARGET_IS_ENABLED(APALIS_IMX8) }, + { VERDIN_IMX8MMQ_WIFI_BT_IT, "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + { VERDIN_IMX8MNQ_WIFI_BT, "Verdin iMX8M Nano Quad 1GB WB", 0 }, + { VERDIN_IMX8MMDL, "Verdin iMX8M Mini DualLite 1GB", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + { VERDIN_IMX8MPQ_WIFI_BT_IT, "Verdin iMX8M Plus Quad 4GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, + { VERDIN_IMX8MMQ_IT, "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + { VERDIN_IMX8MMDL_WIFI_BT_IT, "Verdin iMX8M Mini DualLite 1GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + { VERDIN_IMX8MPQ, "Verdin iMX8M Plus Quad 2GB", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, + { COLIBRI_IMX6ULL_IT_EMMC, "Colibri iMX6ULL 1GB IT", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) }, + { VERDIN_IMX8MPQ_IT, "Verdin iMX8M Plus Quad 4GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, + { VERDIN_IMX8MPQ_2GB_WIFI_BT_IT, "Verdin iMX8M Plus Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, + { VERDIN_IMX8MPQL_IT, "Verdin iMX8M Plus QuadLite 1GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, + { VERDIN_IMX8MPQ_8GB_WIFI_BT, "Verdin iMX8M Plus Quad 8GB WB", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, + { APALIS_IMX8QM_8GB_WIFI_BT_IT, "Apalis iMX8QM 8GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) }, + { VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN, "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + { VERDIN_AM62Q_WIFI_BT_IT, "Verdin AM62 Quad 1GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, + { VERDIN_IMX8MPQ_8GB_WIFI_BT_IT, "Verdin iMX8M Plus Quad 8GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, + { VERDIN_AM62S_512MB, "Verdin AM62 Solo 512MB", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, + { VERDIN_AM62S_512MB_WIFI_BT_IT, "Verdin AM62 Solo 512MB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, + { VERDIN_AM62D_1G_ET, "Verdin AM62 Dual 1GB ET", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, + { VERDIN_AM62D_1G_IT, "Verdin AM62 Dual 1GB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, + { VERDIN_AM62D_1G_WIFI_BT_IT, "Verdin AM62 Dual 1GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, + { VERDIN_AM62Q_2G_WIFI_BT_IT, "Verdin AM62 Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, + { COLIBRI_IMX6S_NOWINCE, "Colibri iMX6S 256MB", TARGET_IS_ENABLED(COLIBRI_IMX6) }, + { COLIBRI_IMX6S_IT_NOWINCE, "Colibri iMX6S 256MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) }, + { COLIBRI_IMX6DL_NOWINCE, "Colibri iMX6DL 512MB", TARGET_IS_ENABLED(COLIBRI_IMX6) }, + { COLIBRI_IMX6DL_IT_NOWINCE, "Colibri iMX6DL 512MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) }, + { COLIBRI_IMX7D_NOWINCE, "Colibri iMX7D 512MB", TARGET_IS_ENABLED(COLIBRI_IMX7) }, + { APALIS_IMX6D_NOWINCE, "Apalis iMX6D 512MB", TARGET_IS_ENABLED(APALIS_IMX6) }, + { APALIS_IMX6Q_NOWINCE, "Apalis iMX6Q 1GB", TARGET_IS_ENABLED(APALIS_IMX6) }, + { APALIS_IMX6D_IT_NOWINCE, "Apalis iMX6D 1GB IT", TARGET_IS_ENABLED(APALIS_IMX6) }, + { APALIS_IMX6Q_IT_NOWINCE, "Apalis iMX6Q 2GB IT", TARGET_IS_ENABLED(APALIS_IMX6) }, + { VERDIN_IMX8MMDL_2G_IT, "Verdin iMX8M Mini DualLite 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + { VERDIN_IMX8MMQ_2G_IT_NO_CAN, "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + { AQUILA_AM69O_32G_WIFI_BT_IT, "Aquila AM69 Octa 32GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { VERDIN_IMX95H_16G_WIFI_BT_IT, "Verdin iMX95 Hexa 16GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX95) }, + { VERDIN_IMX8MMQ_4G_WIFI_BT_ET, "Verdin iMX8M Mini Quad 4GB WB ET", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, }; struct pid4list { @@ -188,6 +186,20 @@ const u32 toradex_ouis[] = { [1] = 0x8c06cbUL, }; +int get_toradex_modules_idx(int pid4) +{ + int i, index = 0; + + for (i = 1; i < ARRAY_SIZE(toradex_modules); i++) { + if (pid4 == toradex_modules[i].pid4) { + index = i; + break; + } + } + + return index; +} + const char * const get_toradex_carrier_boards(int pid4) { int i, index = 0; @@ -361,7 +373,7 @@ static int write_tdx_cfg_block_to_eeprom(unsigned char *config_block) int read_tdx_cfg_block(void) { - int ret = 0; + int idx, ret = 0; u8 *config_block = NULL; struct toradex_tag *tag; size_t size = TDX_CFG_BLOCK_MAX_SIZE; @@ -430,7 +442,8 @@ int read_tdx_cfg_block(void) } /* Cap product id to avoid issues with a yet unknown one */ - if (tdx_hw_tag.prodid >= ARRAY_SIZE(toradex_modules)) + idx = get_toradex_modules_idx(tdx_hw_tag.prodid); + if (!toradex_modules[idx].pid4) tdx_hw_tag.prodid = 0; out: @@ -456,19 +469,21 @@ static int get_cfgblock_interactive(void) int len = 0; int ret = 0; unsigned int prodid; - int i; + int i, idx; printf("Enabled modules:\n"); for (i = 0; i < ARRAY_SIZE(toradex_modules); i++) { if (toradex_modules[i].is_enabled) - printf(" %04d %s\n", i, toradex_modules[i].name); + printf(" %04d %s\n", toradex_modules[i].pid4, + toradex_modules[i].name); } sprintf(message, "Enter the module ID: "); len = cli_readline(message); prodid = dectoul(console_buffer, NULL); - if (prodid >= ARRAY_SIZE(toradex_modules) || !toradex_modules[prodid].is_enabled) { + idx = get_toradex_modules_idx(prodid); + if (!toradex_modules[idx].pid4 || !toradex_modules[idx].is_enabled) { printf("Parsing module id failed\n"); return -1; } diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 0d6dd1c3a721..937e84c3199b 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -21,6 +21,7 @@ struct toradex_eth_addr { } __attribute__((__packed__)); struct toradex_som { + int pid4; const char *name; int is_enabled; }; @@ -139,6 +140,7 @@ extern u32 tdx_car_serial; int read_tdx_cfg_block(void); int read_tdx_cfg_block_carrier(void); +int get_toradex_modules_idx(int pid4); const char * const get_toradex_carrier_boards(int pid4); const char * const get_toradex_display_adapters(int pid4); int try_migrate_tdx_cfg_block_carrier(void); diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index a6b45cdab810..dd2d4b27cea7 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -194,10 +194,12 @@ static int tdx_get_str(struct udevice *dev, int id, size_t size, char *val) switch (id) { case SYSINFO_ID_BOARD_MODEL: + int idx = get_toradex_modules_idx(tdx_hw_tag.prodid); + snprintf(val, size, "Toradex %04d %s %s", tdx_hw_tag.prodid, - toradex_modules[tdx_hw_tag.prodid].name, + toradex_modules[idx].name, tdx_board_rev_str); ret = 0; -- 2.34.1

2 2

[PATCH] mtd: spi-nor: Add support for Macronix flash part
by Venkatesh Yadav Abbarapu 25 Nov '24

25 Nov '24

Added support for Macronix OSPI flash parts MX25UM51345G and MX66UM2G45G, with initial testing conducted on the Tenzing-se1 board using STR mode for basic erase, write, and readback operations. Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar(a)amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> Reviewed-by: Dragan Simic <dsimic(a)manjaro.org> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 91ae49c948..a130845d41 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -275,6 +275,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) }, + { INFO("mx25um51345g", 0xc2813a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_4B_OPCODES) }, + { INFO("mx66um2g45g", 0xc2803c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_4B_OPCODES) }, { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_READ) }, { INFO("mx66lm1g45g", 0xc2853b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25lm51245g", 0xc2853a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, -- 2.25.1

3 3

[PATCH] fs: fat: Handle 'FAT sector size mismatch'
by Varadarajan Narayanan 25 Nov '24

25 Nov '24

Do FAT read and write based on the device sector size instead of the size recorded in the FAT meta data. This helps to overcome the 'FAT sector size mismatch' error and enables U-Boot to read/write those partitions. Signed-off-by: Varadarajan Narayanan <quic_varada(a)quicinc.com> --- fs/fat/fat.c | 227 ++++++++++++++++++++++++++++++++++++++++++--- fs/fat/fat_write.c | 19 ---- 2 files changed, 214 insertions(+), 32 deletions(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index e2570e8167..f4bad99335 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -44,24 +44,223 @@ static void downcase(char *str, size_t len) static struct blk_desc *cur_dev; static struct disk_partition cur_part_info; +int fat_sect_size; #define DOS_BOOT_MAGIC_OFFSET 0x1fe #define DOS_FS_TYPE_OFFSET 0x36 #define DOS_FS32_TYPE_OFFSET 0x52 -static int disk_read(__u32 block, __u32 nr_blocks, void *buf) +inline __u32 sect_to_block(__u32 sect, __u32 *off) { - ulong ret; + *off = 0; + if (fat_sect_size && fat_sect_size < cur_part_info.blksz) { + int div = cur_part_info.blksz / fat_sect_size; + + *off = sect % div; + return sect / div; + } else if (fat_sect_size && (fat_sect_size > cur_part_info.blksz)) { + return sect * (fat_sect_size / cur_part_info.blksz); + } - if (!cur_dev) - return -1; + return sect; +} - ret = blk_dread(cur_dev, cur_part_info.start + block, nr_blocks, buf); +inline __u32 size_to_blocks(__u32 size) +{ + return (size + (cur_part_info.blksz - 1)) / cur_part_info.blksz; +} - if (ret != nr_blocks) - return -1; +static int disk_read(__u32 sect, __u32 nr_sect, void *buf) +{ + int ret; + __u8 *block = NULL; + __u32 rem, size; + __u32 s, n; - return ret; + rem = nr_sect * fat_sect_size; + /* + * block N block N + 1 block N + 2 + * +-+-+--+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | | | | |s|e|c|t|o|r| | |s|e|c|t|o|r| | |s|e|c|t|o|r| | | | | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * . . . | | | | . . . + * ------+---------------+---------------+---------------+------ + * |<--- FAT reads in sectors --->| + * + * | part 1 | part 2 | part 3 | + * + */ + + /* Do part 1 */ + if (fat_sect_size) { + __u32 offset; + + /* Read one block and copy out the leading sectors */ + block = malloc_cache_aligned(cur_dev->blksz); + if (!block) { + printf("Error: allocating block: %lu\n", cur_dev->blksz); + return -1; + } + + s = sect_to_block(sect, &offset); + offset = offset * fat_sect_size; + + ret = blk_dread(cur_dev, cur_part_info.start + s, 1, block); + if (ret != 1) { + ret = -1; + goto exit; + } + + if (rem > (cur_part_info.blksz - offset)) + size = cur_part_info.blksz - offset; + else + size = rem; + + memcpy(buf, block + offset, size); + rem -= size; + buf += size; + s++; + } else { + /* + * fat_sect_size not being set implies, this is the first read + * to partition. The first sector is being read to get the + * FS meta data. The FAT sector size is got from this meta data. + */ + ret = blk_dread(cur_dev, cur_part_info.start + s, 1, buf); + if (ret != 1) + return -1; + } + + /* Do part 2, read directly into the given buffer */ + if (rem > cur_part_info.blksz) { + n = rem / cur_part_info.blksz; + ret = blk_dread(cur_dev, cur_part_info.start + s, n, buf); + if (ret != n) { + ret = -1; + goto exit; + } + buf += n * cur_part_info.blksz; + rem = rem % cur_part_info.blksz; + s += n; + } + + /* Do part 3, read a block and copy the trailing sectors */ + if (rem) { + ret = blk_dread(cur_dev, cur_part_info.start + s, 1, block); + if (ret != 1) { + ret = -1; + goto exit; + } else { + memcpy(buf, block, rem); + } + } +exit: + if (block) + free(block); + + return (ret == -1) ? -1 : nr_sect; +} + +int disk_write(__u32 sect, __u32 nr_sect, void *buf) +{ + int ret; + __u8 *block = NULL; + __u32 rem, size; + __u32 s, n; + + rem = nr_sect * fat_sect_size; + /* + * block N block N + 1 block N + 2 + * +-+-+--+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | | | | |s|e|c|t|o|r| | |s|e|c|t|o|r| | |s|e|c|t|o|r| | | | | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * . . . | | | | . . . + * ------+---------------+---------------+---------------+------ + * |<--- FAT reads in sectors --->| + * + * | part 1 | part 2 | part 3 | + * + */ + + /* Do part 1 */ + if (fat_sect_size) { + __u32 offset; + + /* Read one block and overwrite the leading sectors */ + block = malloc_cache_aligned(cur_dev->blksz); + if (!block) { + printf("Error: allocating block: %lu\n", cur_dev->blksz); + return -1; + } + + s = sect_to_block(sect, &offset); + offset = offset * fat_sect_size; + + ret = blk_dread(cur_dev, cur_part_info.start + s, 1, block); + if (ret != 1) { + ret = -1; + goto exit; + } + + if (rem > (cur_part_info.blksz - offset)) + size = cur_part_info.blksz - offset; + else + size = rem; + + memcpy(block + offset, buf, size); + ret = blk_dwrite(cur_dev, cur_part_info.start + s, 1, block); + if (ret != 1) { + ret = -1; + goto exit; + } + + rem -= size; + buf += size; + s++; + } else { + /* + * fat_sect_size not being set implies, this is the first read + * to partition. The first sector is being read to get the + * FS meta data. The FAT sector size is got from this meta data. + */ + ret = blk_dread(cur_dev, cur_part_info.start + s, 1, buf); + if (ret != 1) + return -1; + } + + /* Do part 2, write directly from the given buffer */ + if (rem > cur_part_info.blksz) { + n = rem / cur_part_info.blksz; + ret = blk_dwrite(cur_dev, cur_part_info.start + s, n, buf); + if (ret != n) { + ret = -1; + goto exit; + } + buf += n * cur_part_info.blksz; + rem = rem % cur_part_info.blksz; + s += n; + } + + /* Do part 3, read a block and copy the trailing sectors */ + if (rem) { + ret = blk_dread(cur_dev, cur_part_info.start + s, 1, block); + if (ret != 1) { + ret = -1; + goto exit; + } else { + memcpy(block, buf, rem); + } + ret = blk_dwrite(cur_dev, cur_part_info.start + s, 1, block); + if (ret != 1) { + ret = -1; + goto exit; + } + } +exit: + if (block) + free(block); + + return (ret == -1) ? -1 : nr_sect; } int fat_set_blk_dev(struct blk_desc *dev_desc, struct disk_partition *info) @@ -575,6 +774,8 @@ read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) return -1; } + fat_sect_size = 0; + if (disk_read(0, 1, block) < 0) { debug("Error: reading block\n"); ret = -1; @@ -645,12 +846,12 @@ static int get_fs_info(fsdata *mydata) mydata->rootdir_sect = mydata->fat_sect + mydata->fatlength * bs.fats; mydata->sect_size = get_unaligned_le16(bs.sector_size); + fat_sect_size = mydata->sect_size; mydata->clust_size = bs.cluster_size; - if (mydata->sect_size != cur_part_info.blksz) { - log_err("FAT sector size mismatch (fs=%u, dev=%lu)\n", - mydata->sect_size, cur_part_info.blksz); - return -1; - } + if (mydata->sect_size != cur_part_info.blksz) + log_info("FAT sector size mismatch (fs=%u, dev=%lu)\n", + mydata->sect_size, cur_part_info.blksz); + if (mydata->clust_size == 0) { log_err("FAT cluster size not set\n"); return -1; diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index ea877ee917..f7a210d790 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -192,25 +192,6 @@ out: } static int total_sector; -static int disk_write(__u32 block, __u32 nr_blocks, void *buf) -{ - ulong ret; - - if (!cur_dev) - return -1; - - if (cur_part_info.start + block + nr_blocks > - cur_part_info.start + total_sector) { - printf("error: overflow occurs\n"); - return -1; - } - - ret = blk_dwrite(cur_dev, cur_part_info.start + block, nr_blocks, buf); - if (nr_blocks && ret == 0) - return -1; - - return ret; -} /* * Write fat buffer into block device -- 2.34.1

3 5

[PATCH v2 0/2] doc: orthographic delights
by Lothar Rubusch 25 Nov '24

25 Nov '24

Fix some typos and wording in various files. As asked by Simon, several patches per file. The commits are extracted from my other patch set. Signed-off-by: Lothar Rubusch <l.rubusch(a)gmail.com> --- v1 -> v2: - dropped entries.rst, since it is generated - prefer British expressions - use term "devicetree" uniformly - fix several typos mentioned --- Lothar Rubusch (3): doc: develop: Fix typos and wording in binman/binman.rst doc: develop: Fix typos and wording in gdb.rst doc/develop/gdb.rst | 10 +- tools/binman/binman.rst | 232 ++++++++++++++++++++-------------------- 2 files changed, 121 insertions(+), 121 deletions(-) -- 2.39.2

3 5

[PATCH] mtd: spi-nor-ids: Add support for W25Q02NW
by Venkatesh Yadav Abbarapu 25 Nov '24

25 Nov '24

Add support for Winbond 256MB flash W25Q02NW which supports 4byte opcodes and also dual and quad read. Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally(a)amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- drivers/mtd/spi/spi-nor-ids.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 91ae49c948..d5258a1fc3 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -569,6 +569,11 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q02nw", 0xef8022, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4B_OPCODES) + }, { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { -- 2.25.1

2 1

[PATCH v5 00/11] Support OF_UPSTREAM for StarFive JH7110
by Hal Feng 25 Nov '24

25 Nov '24

This patchset add OF_UPSTREAM support for StarFive JH7110 based boards. All the JH7110 based boards can use the DT from upstreaming linux kernel. The v1.3b board device tree is set as the default device tree. Support CONFIG_MULTI_DTB_FIT and the SPL selects the correct U-Boot dtb using the EEPROM information. Changes since v4: - Merge patch 2, 3, 5 into patch 1, ensuring git bisect works. - Add a new patch to sort the list of JH7110 imply statements. - Drop the reparent of clock JH7110_AONCLK_APB_FUNC in patch 4, which is unnecessary and will cause errors in gmac0 initialization. Changes since v3: - Add detection for Milk-V Mars CM (lite) boards in patch 13. Changes since v2: - Drop patch 1, because the riscv of_upstream Makefile is created by Conor in commit 239e4705099c. - Drop phy0 rx delay for milkv u-boot dtsi in patch 9. - Add a Fixes tag for patch 13. - In patch 14, the PCB version is only obtained when the product_id is VF7110. Improve the commit messages. Changes since v1: - Drop patch 12. - Modify patch 11 and add three new patches to support CONFIG_MULTI_DTB_FIT. The SPL selects the correct U-Boot dtb using the EEPROM information. History: v4: https://lore.kernel.org/all/20241111020808.38974-1-hal.feng@starfivetech.co… v3: https://lore.kernel.org/all/20241105034328.56439-1-hal.feng@starfivetech.co… v2: https://lore.kernel.org/all/20241028015847.42344-1-hal.feng@starfivetech.co… v1: https://lore.kernel.org/all/20240930155919.111738-1-hal.feng@starfivetech.c… Hal Feng (11): dts: starfive: Switch to using upstream DT riscv: dts: jh7110: Make u-boot device trees adapting to upstream DT pcie: starfive: Make the driver compatible with upstream DT riscv: dts: jh7110: Move common code to the new jh7110-common-u-boot.dtsi riscv: dts: jh7110: Add u-boot device tree for JH7110 based boards board: starfive: spl: Drop the unneeded DT modification code configs: visionfive2: Enable MULTI_DTB_FIT for JH7110 based board DT riscv: dts: jh7110: Support multiple DTBs in a Fit image board: starfive: spl: Fix the wrong use of CONFIG_IS_ENABLED() board: starfive: spl: Support multiple DTBs for JH7110 based boards riscv: cpu: jh7110: Sort the list of imply statements arch/riscv/cpu/jh7110/Kconfig | 19 +- arch/riscv/dts/Makefile | 1 - arch/riscv/dts/jh7110-common-u-boot.dtsi | 198 +++++ arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi | 10 + .../dts/jh7110-pine64-star64-u-boot.dtsi | 6 + .../jh7110-starfive-visionfive-2-u-boot.dtsi | 117 --- ...10-starfive-visionfive-2-v1.2a-u-boot.dtsi | 6 + ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 14 + .../dts/jh7110-starfive-visionfive-2.dts | 11 - .../dts/jh7110-starfive-visionfive-2.dtsi | 380 --------- arch/riscv/dts/jh7110-u-boot.dtsi | 36 +- arch/riscv/dts/jh7110.dtsi | 761 ------------------ board/starfive/visionfive2/spl.c | 391 +-------- configs/starfive_visionfive2_defconfig | 4 +- drivers/clk/starfive/clk-jh7110-pll.c | 6 +- drivers/clk/starfive/clk-jh7110.c | 44 +- drivers/pci/pcie_starfive_jh7110.c | 59 +- .../dt-bindings/clock/starfive,jh7110-crg.h | 258 ------ .../dt-bindings/reset/starfive,jh7110-crg.h | 183 ----- 19 files changed, 369 insertions(+), 2135 deletions(-) create mode 100644 arch/riscv/dts/jh7110-common-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dts delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi delete mode 100644 arch/riscv/dts/jh7110.dtsi delete mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h delete mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h base-commit: 0e6432e19f9c812b4986ca7fd8e6db9fd2c199d3 -- 2.43.2

4 24

[PATCH] spi: Fix missed rename from SPI_ADVANCE to SPI_STACKED_PARALLEL
by Dominik Wernberger 25 Nov '24

25 Nov '24

See https://lore.kernel.org/u-boot/20241026201741.171073-8-marek.vasut+renesas@… Signed-off-by: Dominik Wernberger <dominik.wernberger(a)gmx.de> --- drivers/spi/spi-uclass.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 36b7d383aa..d604975374 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -446,7 +446,7 @@ int _spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, slave = dev_get_parent_priv(dev); bus_data = dev_get_uclass_priv(bus); -#if CONFIG_IS_ENABLED(SPI_ADVANCE) +#if CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL) if ((dev_read_bool(dev, "parallel-memories")) && !slave->multi_cs_cap) { dev_err(dev, "controller doesn't support multi CS\n"); return -EINVAL; @@ -515,7 +515,7 @@ int spi_slave_of_to_plat(struct udevice *dev, struct dm_spi_slave_plat *plat) int mode = 0; int value; -#if CONFIG_IS_ENABLED(SPI_ADVANCE) +#if CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL) int ret; ret = dev_read_u32_array(dev, "reg", plat->cs, SPI_CS_CNT_MAX); -- 2.34.1

3 2

u-boot mailing list issues
by Chris Packham 25 Nov '24

25 Nov '24

Hi, I've noticed a few odd things on the u-boot mailing list lately. A couple of weeks ago I seemed to stop getting new messages. At first I thought this was just gmail deciding to helpfully file messages away for me but they didn't appear anywhere (even in spam). Then I thought maybe I'd been unsubscribed (there were a couple of automated messages around the time the problems started for me that I'd just ignored). But when I went to re-subscribe I got a message saying I was already subscribed. Recently I tried again and this time I was re-subscribed successfully. Just now I got a "Your message to U-Boot awaits moderator approval" after I replied to a thread. Is there something going on with the list or have I just managed to get things into a confused state. Thanks, Chris

2 1

Falcon mode without 'spl export'?
by Yuuta Liang 25 Nov '24

25 Nov '24

Greetings, I am making U-Boot boot my kernel from SD card as fast as possible, hopefully directly from SPL. I found the Falcon mode handy, but there isn't a lot of documents on it, and it seems like I still have to run a special 'spl export' command in regular U-Boot to generate a binary blob. This seems very unpleasant because I do want to build and ship all images on my computer, without the need to 'run a full U-Boot once on the production board on every single firmware upgrade'. Honestly, I am also quite confused why do we need such a command at all, given that I have my kernel and DTB directly accessible from the SD card. Is there any way to get rid of the need of exporting the blob? I do have my kernel and DTB handy. If it is not possible with U-Boot, are there any other solutions that support loading kernel directly from SPL? My SoC is Allwinner V3s. Best regards, Yuuta Liang

1 0