October 2024 - U-Boot

[PATCH] clk: Propagate clk_set_rate() if CLK_SET_PARENT_RATE present
by Sam Protsenko 13 Dec '24

13 Dec '24

Sometimes clocks provided to a consumer might not have .set_rate operation (like gate or mux clocks), but have CLK_SET_PARENT_RATE flag set. In that case it's usually possible to find a parent up the tree which is capable of setting the rate (div, pll, etc). Implement a simple lookup procedure for such cases, to traverse the clock tree until .set_rate capable parent is found, and use that parent to actually change the rate. The search will stop once the first .set_rate capable clock is found, which is usually enough to handle most cases. Signed-off-by: Sam Protsenko <semen.protsenko(a)linaro.org> --- drivers/clk/clk-uclass.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index ed6e60bc4841..755f05f34669 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -571,8 +571,20 @@ ulong clk_set_rate(struct clk *clk, ulong rate) return 0; ops = clk_dev_ops(clk->dev); - if (!ops->set_rate) - return -ENOSYS; + /* Try to find parents which can set rate */ + while (!ops->set_rate) { + struct clk *parent; + + if (!(clk->flags & CLK_SET_RATE_PARENT)) + return -ENOSYS; + + parent = clk_get_parent(clk); + if (IS_ERR_OR_NULL(parent) || !clk_valid(parent)) + return -ENODEV; + + clk = parent; + ops = clk_dev_ops(clk->dev); + } /* get private clock struct used for cache */ clk_get_priv(clk, &clkp); -- 2.39.2

5 16

[PATCH v4 0/8] Inline ECC Series
by Santhosh Kumar K 12 Dec '24

12 Dec '24

Hello, This series is to: Add support for Inline ECC in DDR for AM64X, AM62X, AM62AX, AM62PX, J721S2 and J784S4 devices. (1/8) Enable ECC priming with BIST engine (2/8) Add a function to store base address and size of RAM's banks in a 64-bit device private data (3/8) Setup the ECC region start and range (4/8) Enable ECC 1-bit error, 2-bit error and multiple-bit error interrupts (5/8) Add CONFIG_K3_INLINE_ECC (6/8) Set NR_DRAM_BANKS to 2 (7/8) Pull Redundant DDR functions to a common location and Fixup DDR size when ECC is enabled (8/8) Add ss_cfg reg entry Changes since v3: Pull redundant DDR functions to arch/arm/mach-k3/* v3: https://lore.kernel.org/all/20240523050430.455201-1-s-k6@ti.com/ Changes since v2: Removed 'default n' in Kconfig as that is default setting v2: https://lore.kernel.org/u-boot/20240510084707.1903133-1-s-k6@ti.com/ Changes since v1: Add support for J7* devices. v1: https://lore.kernel.org/u-boot/20240131060213.1128024-1-s-k6@ti.com/ Test Results: https://gist.github.com/santhosh21/25937355aa2c134a64fa76480ac6a4a2 Thanks and Regards, Santhosh. Georgi Vlaev (1): ram: k3-ddrss: Use the DDR controller BIST engine for ECC priming Neha Malcom Francis (2): drivers: ram: Kconfig: Add CONFIG_K3_INLINE_ECC configs: j7*_evm_r5_defconfig: Set NR_DRAM_BANKS to 2 Santhosh Kumar K (5): ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve 'calculations restricted to 32 bits' issue ram: k3-ddrss: Setup ECC region start and range ram: k3-ddrss: Enable ECC interrupts board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC is enabled arm: dts: k3-*-ddr: Add ss_cfg reg entry arch/arm/dts/k3-am62a-ddr.dtsi | 7 +- arch/arm/dts/k3-j721s2-ddr.dtsi | 12 +- arch/arm/dts/k3-j784s4-ddr.dtsi | 24 ++- arch/arm/mach-k3/Makefile | 2 +- arch/arm/mach-k3/include/mach/k3-ddr.h | 15 ++ arch/arm/mach-k3/k3-ddr.c | 88 ++++++++++ board/ti/am62ax/evm.c | 17 +- board/ti/am62px/evm.c | 17 +- board/ti/am62x/evm.c | 62 +------ board/ti/am64x/evm.c | 73 +-------- board/ti/am65x/evm.c | 29 +--- board/ti/j721e/evm.c | 29 +--- board/ti/j721s2/evm.c | 35 ++-- board/ti/j784s4/evm.c | 17 +- configs/j7200_evm_r5_defconfig | 1 + configs/j721e_evm_r5_defconfig | 1 + configs/j721s2_evm_r5_defconfig | 1 + configs/j784s4_evm_r5_defconfig | 1 + drivers/ram/Kconfig | 10 ++ drivers/ram/k3-ddrss/k3-ddrss.c | 214 +++++++++++++++++++++---- 20 files changed, 387 insertions(+), 268 deletions(-) create mode 100644 arch/arm/mach-k3/include/mach/k3-ddr.h create mode 100644 arch/arm/mach-k3/k3-ddr.c -- 2.34.1

5 26

[PATCH 1/6] Revert "spi: zynq_qspi: Add parallel memories support in QSPI driver"
by Marek Vasut 10 Dec '24

10 Dec '24

This reverts commit 1e36d34b52e7a1ebe5a2a5339d6905540f4253aa. This parallel/stacked support breaks basic SPI NOR support, e.g. this no longer works: => sf probe && sf update 0x50000000 0 0x160000 SF: Detected s25fs512s with page size 256 Bytes, erase size 256 KiB, total 64 MiB device 0 offset 0x0, size 0x160000 SPI flash failed in read step Since none of this seems to be in Linux either, revert it all. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- Cc: Andre Przywara <andre.przywara(a)arm.com> Cc: Ashok Reddy Soma <ashok.reddy.soma(a)amd.com> Cc: Jagan Teki <jagan(a)amarulasolutions.com> Cc: Michael Walle <mwalle(a)kernel.org> Cc: Michal Simek <michal.simek(a)amd.com> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Pratyush Yadav <p.yadav(a)ti.com> Cc: Quentin Schulz <quentin.schulz(a)cherry.de> Cc: Sean Anderson <seanga2(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Takahiro Kuwano <Takahiro.Kuwano(a)infineon.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: Tudor Ambarus <tudor.ambarus(a)linaro.org> Cc: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> Cc: u-boot(a)lists.denx.de Cc: uboot-stm32(a)st-md-mailman.stormreply.com --- drivers/spi/zynq_qspi.c | 115 ++++------------------------------------ 1 file changed, 11 insertions(+), 104 deletions(-) diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index f5b3fb5c125..e8bc196ce9e 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -1,8 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2013 - 2022, Xilinx, Inc. + * (C) Copyright 2013 Xilinx, Inc. * (C) Copyright 2015 Jagan Teki <jteki(a)openedev.com> - * (C) Copyright 2023, Advanced Micro Devices, Inc. * * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only) */ @@ -13,12 +12,10 @@ #include <log.h> #include <malloc.h> #include <spi.h> -#include <spi_flash.h> #include <asm/global_data.h> #include <asm/io.h> #include <linux/bitops.h> #include <spi-mem.h> -#include "../mtd/spi/sf_internal.h" DECLARE_GLOBAL_DATA_PTR; @@ -44,21 +41,6 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */ #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */ #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */ -#define ZYNQ_QSPI_FR_QOUT_CODE 0x6B /* read instruction code */ - -#define QSPI_SELECT_LOWER_CS BIT(0) -#define QSPI_SELECT_UPPER_CS BIT(1) - -/* - * QSPI Linear Configuration Register - * - * It is named Linear Configuration but it controls other modes when not in - * linear mode also. - */ -#define ZYNQ_QSPI_LCFG_TWO_MEM_MASK 0x40000000 /* QSPI Enable Bit Mask */ -#define ZYNQ_QSPI_LCFG_SEP_BUS_MASK 0x20000000 /* QSPI Enable Bit Mask */ -#define ZYNQ_QSPI_LCFG_U_PAGE 0x10000000 /* QSPI Upper memory set */ -#define ZYNQ_QSPI_LCFG_DUMMY_SHIFT 8 #define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/ #define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */ @@ -118,11 +100,7 @@ struct zynq_qspi_priv { int bytes_to_transfer; int bytes_to_receive; unsigned int is_inst; - unsigned int is_parallel; - unsigned int is_stacked; - unsigned int u_page; unsigned cs_change:1; - unsigned is_strip:1; }; static int zynq_qspi_of_to_plat(struct udevice *bus) @@ -133,6 +111,7 @@ static int zynq_qspi_of_to_plat(struct udevice *bus) plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob, node, "reg"); + return 0; } @@ -167,9 +146,6 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) /* Disable Interrupts */ writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr); - /* Disable linear mode as the boot loader may have used it */ - writel(0x0, &regs->lqspicfg); - /* Clear the TX and RX threshold reg */ writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, &regs->txftr); writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, &regs->rxftr); @@ -187,12 +163,13 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK | ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK | ZYNQ_QSPI_CR_MSTREN_MASK; - - if (priv->is_stacked) - confr |= 0x10; - writel(confr, &regs->cr); + /* Disable the LQSPI feature */ + confr = readl(&regs->lqspicfg); + confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK; + writel(confr, &regs->lqspicfg); + /* Enable SPI */ writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr); } @@ -203,7 +180,6 @@ static int zynq_qspi_child_pre_probe(struct udevice *bus) struct zynq_qspi_priv *priv = dev_get_priv(bus->parent); priv->max_hz = slave->max_hz; - slave->multi_cs_cap = true; return 0; } @@ -386,8 +362,8 @@ static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size) unsigned len, offset; struct zynq_qspi_regs *regs = priv->regs; static const unsigned offsets[4] = { - ZYNQ_QSPI_TXD_00_01_OFFSET, ZYNQ_QSPI_TXD_00_10_OFFSET, - ZYNQ_QSPI_TXD_00_11_OFFSET, ZYNQ_QSPI_TXD_00_00_OFFSET }; + ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET, + ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET }; while ((fifocount < size) && (priv->bytes_to_transfer > 0)) { @@ -409,11 +385,7 @@ static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size) return; len = priv->bytes_to_transfer; zynq_qspi_write_data(priv, &data, len); - if ((priv->is_parallel || priv->is_stacked) && - !priv->is_inst && (len % 2)) - len++; - offset = (priv->rx_buf) ? - offsets[3] : offsets[len - 1]; + offset = (priv->rx_buf) ? offsets[0] : offsets[len]; writel(data, &regs->cr + (offset / 4)); } } @@ -518,7 +490,6 @@ static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv) */ static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv) { - static u8 current_u_page; u32 data = 0; struct zynq_qspi_regs *regs = priv->regs; @@ -528,34 +499,6 @@ static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv) priv->bytes_to_transfer = priv->len; priv->bytes_to_receive = priv->len; - if (priv->is_parallel) - writel((ZYNQ_QSPI_LCFG_TWO_MEM_MASK | - ZYNQ_QSPI_LCFG_SEP_BUS_MASK | - (1 << ZYNQ_QSPI_LCFG_DUMMY_SHIFT) | - ZYNQ_QSPI_FR_QOUT_CODE), &regs->lqspicfg); - - if (priv->is_inst && priv->is_stacked && current_u_page != priv->u_page) { - if (priv->u_page) { - /* Configure two memories on shared bus - * by enabling upper mem - */ - writel((ZYNQ_QSPI_LCFG_TWO_MEM_MASK | - ZYNQ_QSPI_LCFG_U_PAGE | - (1 << ZYNQ_QSPI_LCFG_DUMMY_SHIFT) | - ZYNQ_QSPI_FR_QOUT_CODE), - &regs->lqspicfg); - } else { - /* Configure two memories on shared bus - * by enabling lower mem - */ - writel((ZYNQ_QSPI_LCFG_TWO_MEM_MASK | - (1 << ZYNQ_QSPI_LCFG_DUMMY_SHIFT) | - ZYNQ_QSPI_FR_QOUT_CODE), - &regs->lqspicfg); - } - current_u_page = priv->u_page; - } - if (priv->len < 4) zynq_qspi_fill_tx_fifo(priv, priv->len); else @@ -655,8 +598,7 @@ static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen, * Assume that the beginning of a transfer with bits to * transmit must contain a device command. */ - if ((dout && flags & SPI_XFER_BEGIN) || - (flags & SPI_XFER_END && !priv->is_strip)) + if (dout && flags & SPI_XFER_BEGIN) priv->is_inst = 1; else priv->is_inst = 0; @@ -666,11 +608,6 @@ static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen, else priv->cs_change = 0; - if (flags & SPI_XFER_U_PAGE) - priv->u_page = 1; - else - priv->u_page = 0; - zynq_qspi_transfer(priv); return 0; @@ -734,35 +671,14 @@ static int zynq_qspi_set_mode(struct udevice *bus, uint mode) return 0; } -bool update_stripe(const struct spi_mem_op *op) -{ - if (op->cmd.opcode == SPINOR_OP_BE_4K || - op->cmd.opcode == SPINOR_OP_CHIP_ERASE || - op->cmd.opcode == SPINOR_OP_SE || - op->cmd.opcode == SPINOR_OP_WREAR || - op->cmd.opcode == SPINOR_OP_WRSR - ) - return false; - - return true; -} - static int zynq_qspi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) { - struct udevice *bus = slave->dev->parent; - struct zynq_qspi_priv *priv = dev_get_priv(bus); int op_len, pos = 0, ret, i; unsigned int flag = 0; const u8 *tx_buf = NULL; u8 *rx_buf = NULL; - if ((slave->flags & QSPI_SELECT_LOWER_CS) && - (slave->flags & QSPI_SELECT_UPPER_CS)) - priv->is_parallel = true; - if (slave->flags & SPI_XFER_STACKED) - priv->is_stacked = true; - if (op->data.nbytes) { if (op->data.dir == SPI_MEM_DATA_IN) rx_buf = op->data.buf.in; @@ -787,9 +703,6 @@ static int zynq_qspi_exec_op(struct spi_slave *slave, if (op->dummy.nbytes) memset(op_buf + pos, 0xff, op->dummy.nbytes); - if (slave->flags & SPI_XFER_U_PAGE) - flag |= SPI_XFER_U_PAGE; - /* 1st transfer: opcode + address + dummy cycles */ /* Make sure to set END bit if no tx or rx data messages follow */ if (!tx_buf && !rx_buf) @@ -800,9 +713,6 @@ static int zynq_qspi_exec_op(struct spi_slave *slave, if (ret) return ret; - if (priv->is_parallel) - priv->is_strip = update_stripe(op); - /* 2nd transfer: rx or tx data path */ if (tx_buf || rx_buf) { ret = zynq_qspi_xfer(slave->dev, op->data.nbytes * 8, tx_buf, @@ -811,9 +721,6 @@ static int zynq_qspi_exec_op(struct spi_slave *slave, return ret; } - priv->is_parallel = false; - priv->is_stacked = false; - slave->flags &= ~SPI_XFER_MASK; spi_release_bus(slave); return 0; -- 2.45.2

9 37

[PATCH] mtd: nand: raw: atmel: remove unnecessary return value
by Marcus Folkesson 10 Dec '24

10 Dec '24

The condition 'ret' is always true as it is never set to other than -EIO. Remove 'ret' and the condition for copy. Signed-off-by: Marcus Folkesson <marcus.folkesson(a)gmail.com> --- drivers/mtd/nand/raw/atmel/nand-controller.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index ee4ec6da58..00d7e177b9 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -568,12 +568,9 @@ static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf, struct mtd_info *mtd = nand_to_mtd(chip); struct atmel_nand *nand = to_atmel_nand(chip); struct atmel_hsmc_nand_controller *nc; - int ret = -EIO; nc = to_hsmc_nand_controller(nand->controller); - - if (ret) - memcpy_toio(nc->sram.virt, buf, mtd->writesize); + memcpy_toio(nc->sram.virt, buf, mtd->writesize); if (oob_required) memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi, @@ -586,12 +583,9 @@ static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf, struct mtd_info *mtd = nand_to_mtd(chip); struct atmel_nand *nand = to_atmel_nand(chip); struct atmel_hsmc_nand_controller *nc; - int ret = -EIO; nc = to_hsmc_nand_controller(nand->controller); - - if (ret) - memcpy_fromio(buf, nc->sram.virt, mtd->writesize); + memcpy_fromio(buf, nc->sram.virt, mtd->writesize); if (oob_required) memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize, -- 2.45.1

3 7

[PATCH v2 0/8] SMBIOS improvements
by Raymond Mao 09 Dec '24

09 Dec '24

Motivations for changes: Current SMBIOS library and command-line tool is not fully matching with the requirements: 1. Missing support for other mandatory types (#7, #9, #16, #17, #19). 2. Only a few platforms support SMBIOS node from the device tree. 3. Values of some fields are hardcoded in the library other than fetching from the device hardware. 4. Embedded data with dynamic length is not supported (E.g. Contained Object Handles in Type #2 and Contained Elements in Type #3) Changes: 1. Refactor the SMBIOS library and command-line tool to better align with the SMBIOS spec. 2. Create an arch-specific driver for all aarch64-based platforms to fetch SMBIOS private data from the device hardware (processor and cache). 3. Create a sysinfo driver to poppulate platform SMBIOS private data. 4. Add generic SMBIOS DTS file for arm64 platforms for those common strings and values which cannot be retrieved from the system registers. Vendors can create their own SMBIOS node using this as an example. For those boards without SMBIOS nodes, this DTS file can be included to have a generic SMBIOS information of the system. 5. Add support for Type #7 (Cache Information) and link its handles to Type #4. Once this patch is acceptted, subsequent patch sets will add other missing types (#9, #16, #17, #19). Tests: To test this with QEMU arm64, please follow the guide on dt_qemu.rst to get a merged DT to run with. ``` qemu-system-arm -machine virt -machine dumpdtb=qemu.dtb cat <(dtc -I dtb qemu.dtb) <(dtc -I dtb ./dts/dt.dtb | grep -v /dts-v1/) \ | dtc - -o merged.dtb qemu-system-arm -machine virt -nographic -bios u-boot.bin -dtb merged.dtb ``` Known issues: It hits the image size limitation on R-CAR board(rcar3_salvator-x). ``` u-boot.img exceeds file size limit: limit: 0x100000 bytes actual: 0x10049d bytes excess: 0x49d bytes ``` This board needs a clean-up to reserve spaces for the changes as SMBIOS is a fundamental feature. Below is the breakdown of the size-growth of the related functions: function old new delta static.smbios_write_type4 252 1052 +800 static.smbios_write_type7 - 764 +764 static.smbios_write_type3 188 488 +300 smbios_get_val_si - 128 +128 static.smbios_write_type2 316 376 +60 sysinfo_get_data - 56 +56 static.smbios_write_type1 380 396 +16 smbios_write_funcs 112 128 +16 ofnode_read_u32 - 12 +12 sysinfo_rcar_ops 40 48 +8 install_smbios_table 468 472 +4 Raymond Mao (8): smbios: Refactor the smbios headfile sysinfo: Add sysinfo API for accessing data area sysinfo: Add sysinfo driver and data structure for smbios smbios: Refactor smbios library armv8: Add arch-specific sysinfo platform driver armv8: Add generic smbios information into the device tree cmd: update smbios cmd configs: Enable sysinfo for QEMU Arm64 arch/arm/cpu/armv8/Makefile | 2 + arch/arm/cpu/armv8/sysinfo.c | 292 +++++++++++++++++++ arch/arm/dts/qemu-arm64.dts | 4 + arch/arm/dts/smbios_generic.dtsi | 82 ++++++ cmd/smbios.c | 346 ++++++++++++++++++++--- configs/qemu_arm64_defconfig | 2 + drivers/misc/Kconfig | 2 +- drivers/sysinfo/smbios.c | 228 +++++++++++++++ drivers/sysinfo/sysinfo-uclass.c | 20 ++ include/smbios.h | 158 ++++++----- include/smbios_def.h | 191 +++++++++++++ include/smbios_plat.h | 79 ++++++ include/sysinfo.h | 125 ++++++++- lib/smbios.c | 462 ++++++++++++++++++++++++++----- test/py/tests/test_smbios.py | 2 +- 15 files changed, 1822 insertions(+), 173 deletions(-) create mode 100644 arch/arm/cpu/armv8/sysinfo.c create mode 100644 arch/arm/dts/smbios_generic.dtsi create mode 100644 include/smbios_def.h create mode 100644 include/smbios_plat.h -- 2.25.1

4 35

[RFC PATCH] zynqmp: Add binman description for SOM
by Michal Simek 09 Dec '24

09 Dec '24

There is necessary to do some steps to compose boot images. These steps were in scripts in layers for a while. That's why introduce description via binman to simplify wiring and remove all scripting around. This should make sure that everybody is up2date with the latest versions. The first step is to create fit image with DTBs with descriptions in configuration node which is written as regular expression to match all SOM versions. Description is there for k24 and k26 in spite of low level psu_init configuration is different. The reason is that it goes to u-boot.itb image which is the same for k24 and k26. u-boot.itb is another image which is generated. It is normally generated via arch/arm/mach-zynqmp/mkimage_fit_atf.sh but this script is supposed to be deprecated. FIT image by purpose is using 64bit addresses to have default option to move images to high DDR (above 4GB). TF-A and TEE are optional components but in the most cases TF-A is present all the time and TEE(OP-TEE) is used by some configurations too. 3rd generated image is boot.bin with updated user field which contains version number. This image can be used with updated Image Selector which supports A/B update mechanisms with rollback protection. 4th image is image.bin which binary file which contains boot.bin and u-boot.itb together and can be programmed via origin Image Selector. This image can be also used for creating one capsule which contains both boot images (in SPL boot flow). Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- Currently I have this for testing purpose only to find missing bits and pieces in binman for cases I want to support. This patch depends on https://lore.kernel.org/r/fbed0251437b61a2f7a85596d7403b5b9c8237c1.17283063… --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynqmp-som-binman.dts | 224 +++++++++++++++++++++++++++ arch/arm/mach-zynqmp/Kconfig | 17 ++ configs/xilinx_zynqmp_kria_defconfig | 2 + 4 files changed, 244 insertions(+) create mode 100644 arch/arm/dts/zynqmp-som-binman.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 65176c8fb836..df340cc30701 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -367,6 +367,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kv-g-revB.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kv-g-revB.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kr-g-revB.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kr-g-revB.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-som-binman.dtb dtb-$(CONFIG_ARCH_VERSAL) += \ versal-mini.dtb \ diff --git a/arch/arm/dts/zynqmp-som-binman.dts b/arch/arm/dts/zynqmp-som-binman.dts new file mode 100644 index 000000000000..7f9333b02023 --- /dev/null +++ b/arch/arm/dts/zynqmp-som-binman.dts @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP SOMs (k24/k26) + * + * (C) Copyright 2024, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek(a)amd.com> + */ + +#include <config.h> + +/dts-v1/; +/ { + binman: binman { + multiple-images; + fit-dtb.blob { + filename = "fit-dtb.blob"; + pad-byte = <0>; + fit { + fit,align = <0x8>; + fit,external-offset = <0x0>; + description = "DTBs for SOMs+CCs"; + fit,fdt-list-val = "zynqmp-smk-k26-revA", "zynqmp-smk-k26-revA-sck-kr-g-revA", "zynqmp-smk-k26-revA-sck-kr-g-revB", "zynqmp-smk-k26-revA-sck-kv-g-revA", "zynqmp-smk-k26-revA-sck-kv-g-revB", "zynqmp-sm-k26-revA-sck-kv-g-revA", "zynqmp-sm-k26-revA-sck-kv-g-revB", "zynqmp-sm-k26-revA-sck-kr-g-revB", "zynqmp-smk-k24-revA-sck-kd-g-revA", "zynqmp-smk-k24-revA-sck-kv-g-revB", "zynqmp-smk-k24-revA-sck-kr-g-revB", "zynqmp-sm-k24-revA-sck-kd-g-revA", "zynqmp-sm-k24-revA-sck-kv-g-revB", "zynqmp-sm-k24-revA-sck-kr-g-revB"; + + images { + @fdt-SEQ { + description = "NAME"; + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + hash-1 { + algo = "md5"; + }; + }; + }; + configurations { + default = "config-1"; + config-1 { + description = "SOM itself"; + fdt = "fdt-1"; + }; + config-2 { + description = "zynqmp-smk-k26-.*-sck-kr-g-revA"; + fdt = "fdt-2"; + }; + config-3 { + description = "zynqmp-smk-k26-.*-sck-kr-g-.*"; + fdt = "fdt-3"; + }; + config-4 { + description = "zynqmp-smk-k26-.*-sck-kv-g-rev[AZ]"; + fdt = "fdt-4"; + }; + config-5 { + description = "zynqmp-smk-k26-.*-sck-kv-g-.*"; + fdt = "fdt-5"; + }; + config-6 { + description = "zynqmp-sm-k26-.*-sck-kv-g-rev[AZ]"; + fdt = "fdt-6"; + }; + config-7 { + description = "zynqmp-sm-k26-.*-sck-kv-g-.*"; + fdt = "fdt-7"; + }; + config-8 { + description = "zynqmp-sm-k26-.*-sck-kr-g-.*"; + fdt = "fdt-8"; + }; + config-9 { + description = "zynqmp-smk-k24-.*-sck-kd-g-.*"; + fdt = "fdt-9"; + }; + config-10 { + description = "zynqmp-smk-k24-.*-sck-kv-g-.*"; + fdt = "fdt-10"; + }; + config-11 { + description = "zynqmp-smk-k24-.*-sck-kr-g-.*"; + fdt = "fdt-11"; + }; + config-12 { + description = "zynqmp-sm-k24-.*-sck-kd-g-.*"; + fdt = "fdt-12"; + }; + config-13 { + description = "zynqmp-sm-k24-.*-sck-kv-g-.*"; + fdt = "fdt-13"; + }; + config-14 { + description = "zynqmp-sm-k24-.*-sck-kr-g-.*"; + fdt = "fdt-14"; + }; + }; + }; + }; + + /* u-boot.itb generation in a static way */ +#define TEXT_BASE_DOWN (CONFIG_TEXT_BASE & 0xffffffff) +#define TEXT_BASE_UP ((CONFIG_TEXT_BASE >> 32) & 0xffffffff) + +#define BL31_BASE_DOWN (CONFIG_BL31_LOAD_ADDR & 0xffffffff) +#define BL31_BASE_UP ((CONFIG_BL31_LOAD_ADDR >> 32) & 0xffffffff) + +#define BL32_BASE_DOWN (CONFIG_BL32_LOAD_ADDR & 0xffffffff) +#define BL32_BASE_UP ((CONFIG_BL32_LOAD_ADDR >> 32) & 0xffffffff) + + itb { + filename = "u-boot.itb"; + pad-byte = <0>; + + fit { + description = "Configuration for Xilinx ZynqMP SoC"; + fit,align = <0x8>; + fit,external-offset = <0x0>; + images { + uboot { + description = "U-Boot (64-bit)"; + type = "firmware"; + os = "u-boot"; + arch = "arm64"; + compression = "none"; + load = <(TEXT_BASE_UP) (TEXT_BASE_DOWN)>; + entry = <(TEXT_BASE_UP) (TEXT_BASE_DOWN)>; + hash { + algo = "md5"; + }; + u-boot-nodtb { + }; + }; + atf { + description = "Trusted Firmware-A"; + type = "firmware"; + os = "arm-trusted-firmware"; + arch = "arm64"; + compression = "none"; + load = <(BL31_BASE_UP) (BL31_BASE_DOWN)>; + entry = <(BL31_BASE_UP) (BL31_BASE_DOWN)>; + hash { + algo = "md5"; + }; + atf-bl31 { + optional; + }; + }; + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <(BL32_BASE_UP) (BL32_BASE_DOWN)>; + entry = <(BL32_BASE_UP) (BL32_BASE_DOWN)>; + tee-os { + optional; + }; + }; + fdt { + description = "Multi DTB fit image"; + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + load = <0x0 0x100000>; + hash { + algo = "md5"; + }; + fdt-blob { + filename = "fit-dtb.blob"; + type = "blob-ext"; + }; + }; + }; + configurations { + default = "config-1"; + config-1 { + description = "Multi DTB with TF-A"; + firmware = "atf"; + loadables = "tee", "uboot", "fdt"; + }; + }; + }; + }; + + /* boot.bin generated with version string inside */ + bootimage { + filename = "boot.bin"; + pad-byte = <0>; + + blob-ext@1 { + offset = <0x0>; + filename = "spl/boot.bin"; + }; + /* Optional version string at offset 0x70 */ + blob-ext@2 { + offset = <0x70>; + filename = "version.bin"; + overlap; + optional; + }; + /* Optional version string at offset 0x94 */ + blob-ext@3 { + offset = <0x94>; + filename = "version.bin"; + overlap; + optional; + }; + }; + + /* Full QSPI image for recovery app */ + image { + filename = "image.bin"; + pad-byte = <0>; + + blob-ext@1 { + offset = <0x0>; + filename = "boot.bin"; + }; + blob-ext@2 { + offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; + filename = "u-boot.itb"; + }; + }; + }; +}; diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index aea13622b68a..a74de68c0181 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -11,6 +11,9 @@ config SYS_VENDOR config SYS_SOC default "zynqmp" +config BINMAN + default y + config SYS_MEM_RSVD_FOR_MMU bool "Reserve memory for MMU Table" help @@ -132,6 +135,20 @@ config SPL_ZYNQMP_RESTORE_JTAG even if no eFuses were burnt. This option restores the interface if possible. +config BL31_LOAD_ADDR + hex "Load address of BL31 image (mostly TF-A)" + default 0xfffe5000 + help + The load address for the BL31 image. This value is used to build the + FIT image header that places BL31 in memory where it will run. + +config BL32_LOAD_ADDR + hex "Load address of BL32 image (mostly secure OS)" + default 0x60000000 + help + The load address for the BL32 image. This value is used to build the + FIT image header that places BL32 in memory where it will run. + config ZYNQ_SDHCI_MAX_FREQ default 200000000 diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index 2eff9f35c0f4..1b4c33d2974e 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_PBSIZE=2073 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_CLOCKS=y CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_BINMAN_SYMBOLS is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_FS_LOAD_KERNEL_NAME="" CONFIG_SPL_FS_LOAD_ARGS_NAME="" @@ -233,6 +234,7 @@ CONFIG_VIDEO_ZYNQMP_DPSUB=y CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y +# CONFIG_BINMAN_FDT is not set CONFIG_PANIC_HANG=y CONFIG_TPM=y CONFIG_SPL_GZIP=y -- 2.43.0

3 8

[PATCH v2 00/18] vbe: Series part D
by Simon Glass 07 Dec '24

07 Dec '24

This includes various patches towards implementing the VBE abrec bootmeth in U-Boot. Changes in v2: - Update this to say VPL instead of TPL - Default this option to off to avoid TPL-code-size increases - Drop the unnecessary interior check for CONFIG_IS_ENABLED(DM_MMC) - Update subject to mention that a newline is added too Simon Glass (18): sandbox: Add missing header file bootstd: Add stub for bootdev_setup_for_sibling_blk() gzip: Correct function comment for gunzip() fdtdec: Support separate BSS for all XPL builds tiny-printf: Correct return values tpl: Support numbered aliases in device tree ram: Support driver model in VPL serial: Support debug UART in TPL armv8: Support not having separate BSS arm: cache: Drop a stale comment arm: Fix up a stale comment in sections.c mmc: Support driver model in TPL mmc: Add more debugging for SPL mmc: Log the error when init fails mmc: rockchip: Log some error returns mmc: rockchip: Allow clocks to be missing rockchip: mmc: Fix a missing colon and newline rockchip: Provided SPL control over efuse presence arch/arm/cpu/armv8/u-boot-spl.lds | 12 ++++++++++++ arch/arm/lib/cache.c | 2 -- arch/arm/lib/sections.c | 2 +- arch/sandbox/include/asm/sections.h | 1 + common/spl/spl_mmc.c | 12 ++++++++++++ drivers/core/Kconfig | 8 ++++++++ drivers/misc/Makefile | 2 +- drivers/mmc/Kconfig | 11 +++++++++++ drivers/mmc/mmc.c | 2 +- drivers/mmc/rockchip_dw_mmc.c | 10 ++++------ drivers/mmc/rockchip_sdhci.c | 11 +++++------ drivers/ram/Kconfig | 9 +++++++++ drivers/serial/Kconfig | 7 +++++++ include/bootdev.h | 8 ++++++++ include/gzip.h | 6 ++++-- lib/fdtdec.c | 2 +- lib/tiny-printf.c | 15 ++++++--------- 17 files changed, 91 insertions(+), 29 deletions(-) -- 2.43.0

4 31

[PATCH v2 00/18] vbe: Series part E
by Simon Glass 07 Dec '24

07 Dec '24

This includes various patches towards implementing the VBE abrec bootmeth in U-Boot. It mostly focuses on SPL tweaks and adjusting what fatures are available in VPL. Changes in v2: - Add field names into the message - Fix 'depends on SPL' to depend on TPL - Depend on TPL/VPL as well - Drop patch 'serial: ns16550: Allow clocks to be missing' Simon Glass (18): image: Add a prototype for fit_image_get_phase() boot: Allow FIT to fall back from best-match option bootstd: Avoid sprintf() in SPL when creating bootdevs boot: Respect the load_op in fit_image_load() malloc: Show amount of used space when memory runs out malloc: Provide a simple malloc for VPL Support setting a maximum size for the VPL image spl: Report a loader failure spl: Allow serial to be disabled in any XPL phase spl: Support a relocated stack in any XPL phase spl: Drop use of uintptr_t spl: Drop a duplicate variable in boot_from_devices() spl: Add some more debugging to load_simple_fit() spl: lib: Allow for decompression in any SPL build boot: Allow use of FIT in TPL and VPL lib: Allow crc8 in TPL and VPL boot: Imply CRC8 with VBE hash: Plumb crc8 into the hash functions boot/Kconfig | 71 ++++++++++++++++++++++++++++++++++- boot/Makefile | 4 +- boot/bootdev-uclass.c | 10 ++++- boot/image-fit.c | 29 ++++++++------ common/hash.c | 8 ++++ common/malloc_simple.c | 3 +- common/spl/Kconfig.vpl | 17 +++++++++ common/spl/spl.c | 15 +++++--- common/spl/spl_atf.c | 36 +++++++++--------- common/spl/spl_fit.c | 12 +++++- common/spl/spl_legacy.c | 8 ++-- configs/sandbox_vpl_defconfig | 3 +- include/image.h | 16 +++++++- include/spl.h | 28 +++++++------- include/u-boot/crc.h | 3 ++ lib/Kconfig | 53 ++++++++++++++++++++++++++ lib/Makefile | 8 ++-- lib/crc8.c | 6 +++ 18 files changed, 262 insertions(+), 68 deletions(-) -- 2.43.0

2 21

[PATCH v2 0/4] Better smartphone support (Qualcomm)
by Caleb Connolly 07 Dec '24

07 Dec '24

Improve support for running U-Boot on [Qualcomm] smartphones, with: * A boot menu which can be entered by holding power during boot * Hang on panic (so errors can be read on the display) * Serial gadget which can be enabled by holding volume down or via boot menu In its current form, U-Boot's boot menu is perfectly adequate, however once an option is picked U-Boot will just drop to the CLI again. On a phone (with no keyboard), dropping to the CLI effectively makes the device unusable until manually rebooted, since there is no way to run any commands... To rectify this, let's revive CONFIG_BOOT_RETRY for the hush parser and make it run the contents of "bootcmd", as well as re-reading the value of the bootretry environment variable. In tandem, this provides for a flexible menu system which we can enter and exit. See qcom-phone.env in patch 1 for more details. Finally, provide some rough-ish documentation to describe how Qualcomm phone support works and outline some debugging steps for when UART and the framebuffer are unavailable. This series depends on CONFIG_REMAP_PHONE_KEYS [1] to enable navigating the boot menu when using upstream DT. [1]: https://lore.kernel.org/u-boot/20240714194948.1271135-1-caleb.connolly@lina… --- Changes in v2: - Fix CONFIG_BUTTON_REMAP_PHONE_KEYS name in qcom-phone.config - Add Tom and Simon to CC - Link to v1: https://lore.kernel.org/r/20240831-qcom-phones-v1-0-08614edd8e35@linaro.org --- Caleb Connolly (4): board/qualcomm: introduce phone config cli_hush: run bootmenu on retry bootretry: check for bootretry variable changes doc: board/qualcomm: describe phone support and bringup board/qualcomm/qcom-phone.config | 12 ++++ board/qualcomm/qcom-phone.env | 49 ++++++++++++++++ boot/bootretry.c | 2 + common/cli_hush.c | 2 +- common/cli_hush_upstream.c | 2 +- doc/board/qualcomm/board.rst | 5 ++ doc/board/qualcomm/index.rst | 1 + doc/board/qualcomm/phones.rst | 122 +++++++++++++++++++++++++++++++++++++++ 8 files changed, 193 insertions(+), 2 deletions(-) --- change-id: 20240831-qcom-phones-c789d14de657 base-commit: 00292c6b39b3f7dcb34e8c3ae6ef276ac862a146 // Caleb (they/them)

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[PATCH] dm: gpio: Return error when pull up/down is requested but set_flags ops is not implmentated
by Zixun LI 06 Dec '24

06 Dec '24

Currently in _dm_gpio_set_flags() when set_flags ops is not implemented direction_output()/_input() is used, but pull up/down is not supported by these ops. Signed-off-by: Zixun LI <admin(a)hifiphile.com> --- We have updated our AT91 BSP to use DM, on field testing few boards went into a failed state due to gpio pullup is not enabled. A floating gpio doesn't always fail and can sometimes be hard to diagostic. --- drivers/gpio/gpio-uclass.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 712119c341..a58513c946 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -661,6 +661,9 @@ static int _dm_gpio_set_flags(struct gpio_desc *desc, ulong flags) if (ops->set_flags) { ret = ops->set_flags(dev, desc->offset, flags); } else { + if (flags & GPIOD_MASK_PULL) + return -EINVAL; + if (flags & GPIOD_IS_OUT) { bool value = flags & GPIOD_IS_OUT_ACTIVE; -- 2.46.2

2 1