September 2023 - U-Boot

[PATCH] fastboot: fix CRC32 chunk size checking
by Wojciech Nizinski 31 Oct '23

31 Oct '23

genimage create android-sparse file with CRC32 chunk at end. When U-Boot's fastboot receives this chunk it returns error message: `Fail Bogus chunk size for chunk type Dont Care` According to reference implementation of Android's sparse file format: <https://android.googlesource.com/platform/system/core/+/refs/heads/main/ libsparse/output_file.cpp#513> the chunk_header.total_sz is CHUNK_HEADER_LEN + 4 (CRC32 size). Signed-off-by: Wojciech Nizinski <niziak(a)spox.org> --- lib/image-sparse.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/image-sparse.c b/lib/image-sparse.c index 8f8a67e158..323aad981c 100644 --- a/lib/image-sparse.c +++ b/lib/image-sparse.c @@ -289,8 +289,8 @@ int write_sparse_image(struct sparse_storage *info, case CHUNK_TYPE_CRC32: if (chunk_header->total_sz != - sparse_header->chunk_hdr_sz) { - info->mssg("Bogus chunk size for chunk type Dont Care", + sparse_header->chunk_hdr_sz + sizeof(uint32_t)) { + info->mssg("Bogus chunk size for chunk type CRC32", response); return -1; } -- 2.39.2

2 2

[PATCH v2 0/2] power: pmic: add TPS65913 support
by Svyatoslav Ryhel 31 Oct '23

31 Oct '23

Existing PALMAS PMIC driver is fully compatible with TI TPS65913 PMIC found in many Tegra 4 devices, like Tegra Note 7 and ASUS TF701T. Add TPS65913 dts compatible with TPS659038 data. Issue with regulators is more general then I though initially. It touches all pmic regulators. Currently device tree entries of regulators are completely ignored and regulators are probed only if they are called by the device which uses it. This results into two issues: regulators which must run under boot-on or always-on mode are ignored and not enabled; dts props like voltage are not applied to the regulator so the regulator may be enabled with random actual voltage, which may have unexpected consequences. Second patch changes this behavior. Post-probe function is introduced which performs probing of each pmics child and if it is a regulator, regulator_autoset function is called, which handles always-on and boot-on regulators, but if none of those props are set, the regulator is disabled. Later disabled regulators can be re-enabled by devices which use them without issues. I have tested this change on multiple devices with different PMICs (LG P895, max77663; TF300T with TPS65911; HTC One X with TPS80031; Tegratab with TPS65913). Without this patch they behave as described in the third paragraph. With patch behavior is correct. --- Changes from v1: - implemented general fix of regulator behavior, which include: - introduction of post-probe into pmic-uclass driver - probing all pmic childs in post-probe - check if device is regulator > autoset if regulator is boot-on or always-on else disable regulator --- Svyatoslav Ryhel (2): power: pmic: support TI TPS65913 PMIC power: pmic: fix regulators behaviour drivers/power/pmic/palmas.c | 1 + drivers/power/pmic/pmic-uclass.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) -- 2.39.2

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[PATCH v2 2/2] mmc: Add quirk to disable PWREN for dw_mmc
by David Hewitt 31 Oct '23

31 Oct '23

This is required for correct booting of the PINE64 PineTab2. If PWREN is pulled high on this device, the SD card cannot be detected. This is required in other PINE64 devices (e.g. Quartz64 Model A) too. See commit ba33172a36f298641f51a5e6b855c3e89e3f5d3e in https://github.com/CounterPillow/u-boot-quartz64 Signed-off-by: David Hewitt <davidmhewitt(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Philipp Tomsich <philipp.tomsich(a)vrull.eu> Cc: Kever Yang <kever.yang(a)rock-chips.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> --- Changes for v2: - Removed an unrelated change drivers/mmc/dw_mmc.c | 3 ++- drivers/mmc/rockchip_dw_mmc.c | 3 +++ include/dwmmc.h | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 5085a3b491..cb1d99132f 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -530,7 +530,8 @@ static int dwmci_init(struct mmc *mmc) if (host->board_init) host->board_init(host); - dwmci_writel(host, DWMCI_PWREN, 1); + if (!(host->quirks & DWMCI_QUIRK_DISABLE_PWREN)) + dwmci_writel(host, DWMCI_PWREN, 1); if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { debug("%s[%d] Fail-reset!!\n", __func__, __LINE__); diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 72c820ee63..af6ac59a46 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -78,6 +78,9 @@ static int rockchip_dwmmc_of_to_plat(struct udevice *dev) else host->dev_index = 1; + if (dev_read_bool(dev, "rockchip,disable-pwren-quirk")) + host->quirks |= DWMCI_QUIRK_DISABLE_PWREN; + priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); if (priv->fifo_depth < 0) diff --git a/include/dwmmc.h b/include/dwmmc.h index 136a95b8cd..98aebb46f1 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -141,6 +141,7 @@ /* quirks */ #define DWMCI_QUIRK_DISABLE_SMU (1 << 0) +#define DWMCI_QUIRK_DISABLE_PWREN (1 << 1) /** * struct dwmci_host - Information about a designware MMC host -- 2.34.1

2 1

[PATCH] addrmap: Fix off by one in addrmap_set_entry()
by Dan Carpenter 30 Oct '23

30 Oct '23

The > comparison needs to be changed to >= to prevent an out of bounds write on th next line. Signed-off-by: Dan Carpenter <dan.carpenter(a)linaro.org> --- lib/addr_map.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/addr_map.c b/lib/addr_map.c index 9b3e0a544e47..86e932e4b561 100644 --- a/lib/addr_map.c +++ b/lib/addr_map.c @@ -59,7 +59,7 @@ void *addrmap_phys_to_virt(phys_addr_t paddr) void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr, phys_size_t size, int idx) { - if (idx > CONFIG_SYS_NUM_ADDR_MAP) + if (idx >= CONFIG_SYS_NUM_ADDR_MAP) return; address_map[idx].vaddr = vaddr; -- 2.39.2

3 5

[PATCH] misc: i2c_eeprom: consider pagesize when writing to eeprom
by Michel Alex 30 Oct '23

30 Oct '23

Calculate the maximum length of the buffer when writing accross the page boundary. If the buffer length exceeds the page boundary, split it. Use this length instead of comparing the length with the pagesize, because the write start address can be somewhere in the middle of a page. Signed-off-by: Alex Michel <alex.michel(a)wiedemann-group.com> --- drivers/misc/i2c_eeprom.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c index bdd7e018cc..f345e34179 100644 --- a/drivers/misc/i2c_eeprom.c +++ b/drivers/misc/i2c_eeprom.c @@ -60,6 +60,17 @@ static int i2c_eeprom_std_read(struct udevice *dev, int offset, u int8_t *buf, return dm_i2c_read(dev, offset, buf, size); } +static int i2c_eeprom_len(unsigned offset, unsigned len, unsigned pagesize) +{ + int page_offset = ((offset) & (pagesize - 1)); + unsigned maxlen = pagesize - page_offset; + + if (len > maxlen) + len = maxlen; + + return len; +} + static int i2c_eeprom_std_write(struct udevice *dev, int offset, const uint8_t *buf, int size) { @@ -67,7 +78,7 @@ static int i2c_eeprom_std_write(struct udevice *dev, int offset, int ret; while (size > 0) { - int write_size = min_t(int, size, priv->pagesize); + int write_size = i2c_eeprom_len(offset, size, priv->pagesize); ret = dm_i2c_write(dev, offset, buf, write_size); if (ret) -- 2.34.1

3 8

[PATCH v2] dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation
by Jonas Karlman 30 Oct '23

30 Oct '23

Nodes with bootph-pre-sram/ram props are bound in multiple phases: 1. At TPL (bootph-pre-sram) or SPL (bootph-pre-ram) phase 2. At U-Boot proper pre-relocation phase 3. At U-Boot proper normal phase However the binding and U-Boot Driver Model documentation indicate that only nodes marked with bootph-all or bootph-some-ram should be bound in the U-Boot proper pre-relocation phase. Change ofnode_pre_reloc to report a node with bootph-pre-ram/sram prop with a pre-reloc status only after U-Boot proper pre-relocation phase. Also update the ofnode_pre_reloc documentation to closer reflect the binding and driver model documentation. This changes behavior of what nodes are bound in the U-Boot proper pre-relocation phase. Change to bootph-all or add bootph-some-ram prop to restore prior behavior. Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - Drop use of !! to convert into bool - Update documentation for ofnode_pre_reloc - Rewrite commit message - Collect r-b tag drivers/core/ofnode.c | 2 +- include/dm/ofnode.h | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 8df16e56af5c..b1e94b2d60df 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -1353,7 +1353,7 @@ bool ofnode_pre_reloc(ofnode node) */ if (ofnode_read_bool(node, "bootph-pre-ram") || ofnode_read_bool(node, "bootph-pre-sram")) - return true; + return gd->flags & GD_FLG_RELOC; if (IS_ENABLED(CONFIG_OF_TAG_MIGRATE)) { /* detect and handle old tags */ diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 0f38b3e736de..13700f8266d7 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -1198,15 +1198,15 @@ int ofnode_read_simple_size_cells(ofnode node); * determine if a node was bound in one of SPL/TPL stages. * * There are 4 settings currently in use - * - bootph-some-ram: U-Boot proper pre-relocation only + * - bootph-some-ram: U-Boot proper pre-relocation phase * - bootph-all: all phases * Existing platforms only use it to indicate nodes needed in * SPL. Should probably be replaced by bootph-pre-ram for new platforms. - * - bootph-pre-ram: SPL and U-Boot pre-relocation - * - bootph-pre-sram: TPL and U-Boot pre-relocation + * - bootph-pre-ram: SPL phase + * - bootph-pre-sram: TPL phase * * @node: node to check - * Return: true if node is needed in SPL/TL, false otherwise + * Return: true if node should be or was bound, false otherwise */ bool ofnode_pre_reloc(ofnode node); -- 2.41.0

5 7

[PATCH 00/14] bloblist: Align to firmware handoff
by Simon Glass 30 Oct '23

30 Oct '23

In moving from v0.8 to v0.9 the Firmware Handoff specification made some changes, including: - Use a packed format for headers to reduce space - Add an explicit alignment field in the header - Renumber all the tags and reduce their size to 24 bits - Drop use of the blob header to specify alignment, in favour of a 'void' blob type This series attempts to align to that specification, including updating the API and tests. It is likely that refinements will be made as other projects implement the spec too. As before the code is dual-licensed, to permit use in projects with a permissive license. Simon Glass (14): bloblist: Update the tag numbering bloblist: Adjust API to align in powers of 2 bloblist: Change the magic value bloblist: Set version to 1 bloblist: Access record hdr_size and tag via a function bloblist: Drop the flags value bloblist: Drop the spare values bloblist: Change the checksum algorithm bloblist: Checksum the entire bloblist bloblist: Handle alignment with a void entry bloblist: Reduce blob-header size bloblist: Reduce bloblist header size bloblist: Add alignment to bloblist_new() bloblist: Update documentation and header comment arch/x86/lib/tables.c | 3 +- common/bloblist.c | 102 ++++++++++++++++++++------------- doc/develop/bloblist.rst | 4 +- include/bloblist.h | 121 +++++++++++++++++++-------------------- test/bloblist.c | 53 +++++++++-------- 5 files changed, 152 insertions(+), 131 deletions(-) -- 2.41.0.487.g6d72f3e995-goog

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[PATCH] mmc: Add SPL_MMC_PWRSEQ to fix link issue when building SPL
by Jonas Karlman 29 Oct '23

29 Oct '23

With MMC_PWRSEQ enabled the following link issue may happen when building SPL and SPL_PWRSEQ is not enabled. aarch64-linux-gnu-ld.bfd: drivers/mmc/meson_gx_mmc.o: in function `meson_mmc_probe': drivers/mmc/meson_gx_mmc.c:295: undefined reference to `pwrseq_set_power' Fix this by adding a SPL_MMC_PWRSEQ Kconfig option used to enable mmc pwrseq support in SPL. Also add depends on DM_GPIO to fix following link issue: aarch64-linux-gnu-ld.bfd: drivers/mmc/mmc-pwrseq.o: in function `mmc_pwrseq_set_power': drivers/mmc/mmc-pwrseq.c:26: undefined reference to `gpio_request_by_name' aarch64-linux-gnu-ld.bfd: drivers/mmc/mmc-pwrseq.c:29: undefined reference to `dm_gpio_set_value' aarch64-linux-gnu-ld.bfd: drivers/mmc/mmc-pwrseq.c:31: undefined reference to `dm_gpio_set_value' Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- drivers/mmc/Kconfig | 10 +++++++++- drivers/mmc/Makefile | 2 +- drivers/mmc/meson_gx_mmc.c | 2 +- drivers/mmc/rockchip_dw_mmc.c | 2 +- include/mmc.h | 4 ++-- 5 files changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index de01b9687bad..a9931d39412d 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -20,11 +20,19 @@ config MMC_WRITE config MMC_PWRSEQ bool "HW reset support for eMMC" - depends on PWRSEQ + depends on PWRSEQ && DM_GPIO help Ths select Hardware reset support aka pwrseq-emmc for eMMC devices. +config SPL_MMC_PWRSEQ + bool "HW reset support for eMMC in SPL" + depends on SPL_PWRSEQ && SPL_DM_GPIO + default y if MMC_PWRSEQ + help + Ths select Hardware reset support aka pwrseq-emmc for eMMC + devices in SPL. + config MMC_BROKEN_CD bool "Poll for broken card detection case" help diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 2c65c4765ab2..0a79dd058bef 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -11,7 +11,7 @@ obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += mmc_bootdev.o endif obj-$(CONFIG_$(SPL_TPL_)MMC_WRITE) += mmc_write.o -obj-$(CONFIG_MMC_PWRSEQ) += mmc-pwrseq.o +obj-$(CONFIG_$(SPL_)MMC_PWRSEQ) += mmc-pwrseq.o obj-$(CONFIG_MMC_SDHCI_ADMA_HELPERS) += sdhci-adma.o ifndef CONFIG_$(SPL_)BLK diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index fcf4f03d1e24..0825c0a2a838 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -288,7 +288,7 @@ static int meson_mmc_probe(struct udevice *dev) mmc_set_clock(mmc, cfg->f_min, MMC_CLK_ENABLE); -#ifdef CONFIG_MMC_PWRSEQ +#if CONFIG_IS_ENABLED(MMC_PWRSEQ) /* Enable power if needed */ ret = mmc_pwrseq_get_power(dev, cfg); if (!ret) { diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 72c820ee6330..ad4529d6afa8 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -145,7 +145,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev) host->fifo_mode = priv->fifo_mode; -#ifdef CONFIG_MMC_PWRSEQ +#if CONFIG_IS_ENABLED(MMC_PWRSEQ) /* Enable power if needed */ ret = mmc_pwrseq_get_power(dev, &plat->cfg); if (!ret) { diff --git a/include/mmc.h b/include/mmc.h index 1022db3ffa7c..9aef31ea5deb 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -590,7 +590,7 @@ struct mmc_config { uint f_max; uint b_max; unsigned char part_type; -#ifdef CONFIG_MMC_PWRSEQ +#if CONFIG_IS_ENABLED(MMC_PWRSEQ) struct udevice *pwr_dev; #endif }; @@ -808,7 +808,7 @@ int mmc_deinit(struct mmc *mmc); */ int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg); -#ifdef CONFIG_MMC_PWRSEQ +#if CONFIG_IS_ENABLED(MMC_PWRSEQ) /** * mmc_pwrseq_get_power() - get a power device from device tree * -- 2.42.0

4 4

[PATCH v1] board: toradex: verdin-imx8mp: enable usb device and fastboot support
by Marcel Ziswiler 28 Oct '23

28 Oct '23

From: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> Enable USB device and fastboot support which may be used to load the Toradex Easy Installer FIT image. While at it also enable USB mass storage aka UMS support. Note that the i.MX 8M Plus recovery mode support is based on the USB boot stage of the BOOTROM and does NOT require USB SDP SPL aka serial downloader support. Signed-off-by: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> --- configs/verdin-imx8mp_defconfig | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index 2df0f4f3443..4c6650c3453 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -79,6 +79,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_READ=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y @@ -108,6 +109,12 @@ CONFIG_BOOTCOUNT_ENV=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y CONFIG_FSL_CAAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_GPIO_HOG=y CONFIG_SPL_GPIO_HOG=y CONFIG_MXC_GPIO=y @@ -138,6 +145,7 @@ CONFIG_DWC_ETH_QOS_IMX=y CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PHY_IMX8MQ_USB=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y @@ -160,14 +168,20 @@ CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y CONFIG_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y CONFIG_USB_EHCI_HCD=y -CONFIG_MXC_USB_OTG_HACTIVE=y +# CONFIG_USB_EHCI_MX7 is not set CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Toradex" +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_IMX_WATCHDOG=y CONFIG_HEXDUMP=y -- 2.36.1

4 3

[RESEND PATCH v2] rockchip: include: asm: fix entering download mode rk3066
by Johan Jonker 27 Oct '23

27 Oct '23

Keep track of the re-entries with help of the lr register. This binary can be re-used and called from various BROM functions. Only when it's called from the part that handles SPI, NAND or EMMC hardware it needs to early return to BROM ones. In download mode when it handles data on USB OTG and UART0 this section must be skipped. Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in support to enter download mode on return to BROM. This binary must check the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's set. It then returns to BROM to the end of the function that reads boot blocks. >From there the BROM code goes into a download mode and waits for data on USB OTG and UART0. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- Note: Normal boot flow is OK. In download mode this binary hangs after return to BROM for unknown reasons. Replace CODE471_OPTION with 30_LPDDR2_300MHz_DD.bin for now. Could Rockchip disclose what further conditions must be met in rk3066 download mode? Changed V2: Move file to rk3066 specific location Replace retry_counter by LR check Add DNL mode return address Restyle Reword --- arch/arm/include/asm/arch-rk3066/boot0.h | 77 +++++++++++++++++++++++- arch/arm/mach-rockchip/Kconfig | 17 +++++- arch/arm/mach-rockchip/rk3066/Kconfig | 6 ++ 3 files changed, 98 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-rk3066/boot0.h b/arch/arm/include/asm/arch-rk3066/boot0.h index 28c0fb9a4c6b..1af4b9c1d7ba 100644 --- a/arch/arm/include/asm/arch-rk3066/boot0.h +++ b/arch/arm/include/asm/arch-rk3066/boot0.h @@ -3,6 +3,81 @@ #ifndef __ASM_ARCH_BOOT0_H__ #define __ASM_ARCH_BOOT0_H__ -#include <asm/arch-rockchip/boot0.h> +#include <asm/arch-rockchip/boot_mode.h> +/* + * Execution starts on the instruction following this 4-byte header + * (containing the magic 'RK30'). This magic constant will be written into + * the final image by the rkimage tool, but we need to reserve space for it here. + */ +#ifdef CONFIG_SPL_BUILD + b 1f /* if overwritten, entry-address is at the next word */ +1: +#endif + +#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM) +/* + * Keep track of the re-entries with help of the lr register. + * This binary can be re-used and called from various BROM functions. + * Only when it's called from the part that handles SPI, NAND or EMMC + * hardware it needs to early return to BROM ones. + * In download mode when it handles data on USB OTG and UART0 + * this section must be skipped. + */ + ldr r3, =CONFIG_ROCKCHIP_BOOT_LR_REG + cmp lr, r3 /* if (LR != CONFIG_ROCKCHIP_BOOT_LR_REG) */ + bne reset /* goto reset; */ +/* + * Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in + * support to enter download mode on return to BROM. This binary must check + * the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's set. + * It then returns to BROM to the end of the function that reads boot blocks. + * From there the BROM code goes into a download mode and waits for data + * on USB OTG and UART0. + */ + ldr r2, =BOOT_BROM_DOWNLOAD + ldr r3, =CONFIG_ROCKCHIP_BOOT_MODE_REG + ldr r0, [r3] /* if (readl(CONFIG_ROCKCHIP_BOOT_MODE_REG) != */ + cmp r0, r2 /* BOOT_BROM_DOWNLOAD) { */ + bne early_return /* goto early_return; */ + /* } else { */ + mov r0, #0 + str r0, [r3] /* writel(0, CONFIG_ROCKCHIP_BOOT_MODE_REG); */ + + ldr r3, =CONFIG_ROCKCHIP_BOOT_RETURN_REG + bx r3 /* return to CONFIG_ROCKCHIP_BOOT_RETURN_REG;*/ + +early_return: + bx lr /* return to LR in BROM */ + +SAVE_SP_ADDR: + .word 0 + + .globl save_boot_params +save_boot_params: + push {r1-r12, lr} + ldr r0, =SAVE_SP_ADDR + str sp, [r0] + b save_boot_params_ret + + .globl back_to_bootrom +back_to_bootrom: + ldr r0, =SAVE_SP_ADDR + ldr sp, [r0] + mov r0, #0 + pop {r1-r12, pc} +#endif + +#if (defined(CONFIG_SPL_BUILD)) +/* U-Boot proper of armv7 does not need this */ + b reset +#endif + +/* + * For armv7, the addr '_start' will be used as vector start address + * and is written to the VBAR register, which needs to aligned to 0x20. + */ + .align(5), 0x0 +_start: + ARM_VECTORS #endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 07b5595dac8c..84a2f0d5ff48 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -402,7 +402,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM config TPL_ROCKCHIP_BACK_TO_BROM bool "TPL returns to bootrom" default y - select ROCKCHIP_BROM_HELPER + select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066 select TPL_BOOTROM_SUPPORT depends on TPL help @@ -448,6 +448,21 @@ config ROCKCHIP_BOOT_MODE_REG The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h) according to the value from this register. +config ROCKCHIP_BOOT_LR_REG + hex "Rockchip boot early return LR address" + depends on TPL_ROCKCHIP_EARLYRETURN_TO_BROM || SPL_ROCKCHIP_EARLYRETURN_TO_BROM + help + With ROCKCHIP_EARLYRETURN_TO_BROM enabled this LR address is + used to keep track of the re-entries. + +config ROCKCHIP_BOOT_RETURN_REG + hex "Rockchip download mode return address" + depends on TPL_ROCKCHIP_EARLYRETURN_TO_BROM || SPL_ROCKCHIP_EARLYRETURN_TO_BROM + help + Rockchip SoC models without built-in support to enter + download mode after early return to BROM code use a SoC + specific return address in BROM. + config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON bool "Disable device boot on power plug-in" depends on PMIC_RK8XX diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig index 95d7fc8a2917..3721f7469a9e 100644 --- a/arch/arm/mach-rockchip/rk3066/Kconfig +++ b/arch/arm/mach-rockchip/rk3066/Kconfig @@ -10,6 +10,12 @@ config TARGET_MK808 config ROCKCHIP_BOOT_MODE_REG default 0x20004040 +config ROCKCHIP_BOOT_LR_REG + default 0x00001058 + +config ROCKCHIP_BOOT_RETURN_REG + default 0x00001100 + config SYS_SOC default "rk3066" -- 2.39.2

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