July 2023 - U-Boot

[PATCH v7 00/23] Migration to using binman for bootloader
by Neha Malcom Francis 17 Jul '23

17 Jul '23

This series aims to eliminate the use of additional custom repositories such as k3-image-gen (K3 Image Generation) repo and core-secdev-k3 (K3 Security Development Tools) that was plumbed into the U-Boot build flow to generate boot images for TI K3 platform devices. And instead, we move towards using binman that aligns better with the community standard build flow. This series uses binman for all K3 platforms supported on U-Boot currently; both HS (High Security, both SE and FS) and GP (General Purpose) devices. Background on using k3-image-gen: * TI K3 devices require a SYSFW (System Firmware) image consisting of a signed system firmware image and board configuration binaries, this is needed to bring up system firmware during U-Boot R5 SPL startup. * Board configuration data contain board-specific information such as resource management, power management and security. Background on using core-secdev-k3: * Contains resources to sign x509 certificates for HS devices Series intends to use binman to take over the packaging and signing for the R5 bootloader images tiboot3.bin (and sysfw.itb, for non-combined boot flow) instead of k3-image-gen. Series also packages the A72/A53 bootloader images (tispl.bin and u-boot.img) using ATF, OPTEE and DM (Device Manager) Changes in v7: - corrected Texas Instruments copyright year - k3-am65-iot2050 image fit@0x180000 filename retained as tispl.bin Changes in v6: - addressed whitespace warnings - added testcase for overwriting symlink functionality - %s/Arm Trusted Firmware/Trusted Firmware-A - %s/tee-pager_v2.bin/tee-raw.bin Changes in v5: - updated all board configurations to latest - changed output binary filenames - fixed multiple certificate generation leading to packaging inconsistency in ti-secure*.py - added patch to overwrite symlink if exists, patch 21/23 ("binman: Overwrite symlink if it already exists") Changes in v4: - added support for iot2050 - documentation fixes - move to using self.Raise in ti-board-config etype - introduced common k3-binman.dtsi (further reduction in code duplication can be targeted, this as first step) Changes in v3: - added support for HS-FS devices - added support for AM68-sk - added back dropped documentation patch - changed prefix for SYSFW and DM files to expected directory name - extended test coverage to 100% - documentation fixes - corrected formatting changes Changes in v2: - removed all external scripts - created ti-board-config etype to support generation of board config binaries - created ti-secure and ti-secure-rom etypes to handle signing instead of using external TI_SECURE_DEV_PKG - updated openssl btool to support x509 certificate generation - dropped Makefile changes to obtain external binary components, moving to using BINMAN_INDIRS to achieve the same CI/CD passes 100% (series based on -next) [1] v1: https://patchwork.ozlabs.org/project/uboot/cover/20230120101903.179959-1-n-… v2: https://patchwork.ozlabs.org/project/uboot/cover/20230404121342.446935-1-n-… v3: https://patchwork.ozlabs.org/project/uboot/cover/20230421123203.1315330-1-n… v4: https://patchwork.ozlabs.org/project/uboot/cover/20230518142713.184164-1-n-… v5: https://patchwork.ozlabs.org/project/uboot/cover/20230707123450.30329-1-n-f… v6: https://patchwork.ozlabs.org/project/uboot/cover/20230712183453.7623-1-n-fr… [1] https://github.com/u-boot/u-boot/pull/363 Andrew Davis (1): binman: Overwrite symlink if it already exists Neha Malcom Francis (20): binman: ti-board-config: Add support for TI board config binaries binman: ti-secure: Add support for TI signing arm: dts: k3: Add support for packaging sysfw.itb and tiboot3.bin j721e: schema: yaml: Add general schema and J721E board config files j721e: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img j7200: yaml: Add J7200 board config files j7200: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img am65x: yaml: Add AM65x board config files am65: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img am64x: yaml: Add board configs for AM64x am64x: dts: binman: Package tiboot3.bin, tispl.bin u-boot.img j721s2: yaml: Add board configs for J721S2 j721s2: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img am62: yaml: Add board configs for AM62 am625: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img am62a: yaml: Add board configs for AM62ax am62a: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img arm: k3-am65x-iot2050: Use binman for tispl.bin for iot2050 k3: tools: config.mk: Update makefile and remove scripts doc: board: ti: Update documentation for binman flow Tom Rini (2): buildman: Create a requirements.txt file CI: Make use of buildman requirements.txt .azure-pipelines.yml | 4 + .gitlab-ci.yml | 4 + arch/arm/dts/k3-am625-r5-sk.dts | 1 + arch/arm/dts/k3-am625-sk-binman.dtsi | 463 +++ arch/arm/dts/k3-am625-sk-u-boot.dtsi | 2 + arch/arm/dts/k3-am62a-sk-binman.dtsi | 466 +++ arch/arm/dts/k3-am62a7-r5-sk.dts | 1 + arch/arm/dts/k3-am62a7-sk.dts | 1 + arch/arm/dts/k3-am642-evm-u-boot.dtsi | 2 + arch/arm/dts/k3-am642-r5-evm.dts | 1 + arch/arm/dts/k3-am642-sk-u-boot.dtsi | 2 + arch/arm/dts/k3-am64x-binman.dtsi | 515 +++ arch/arm/dts/k3-am65-iot2050-boot-image.dtsi | 75 +- arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 1 + .../dts/k3-am654-r5-base-board-u-boot.dtsi | 1 + arch/arm/dts/k3-am65x-binman.dtsi | 518 +++ .../arm/dts/k3-am68-sk-base-board-u-boot.dtsi | 2 + arch/arm/dts/k3-binman.dtsi | 116 + arch/arm/dts/k3-j7200-binman.dtsi | 502 +++ .../k3-j7200-common-proc-board-u-boot.dtsi | 2 + arch/arm/dts/k3-j721e-binman.dtsi | 701 ++++ .../k3-j721e-common-proc-board-u-boot.dtsi | 1 + .../arm/dts/k3-j721e-r5-common-proc-board.dts | 1 + arch/arm/dts/k3-j721e-sk-u-boot.dtsi | 1 + arch/arm/dts/k3-j721s2-binman.dtsi | 546 +++ .../k3-j721s2-common-proc-board-u-boot.dtsi | 2 + .../dts/k3-j721s2-r5-common-proc-board.dts | 1 + arch/arm/mach-k3/config.mk | 103 - board/ti/am62ax/Kconfig | 2 + board/ti/am62ax/board-cfg.yaml | 36 + board/ti/am62ax/pm-cfg.yaml | 12 + board/ti/am62ax/rm-cfg.yaml | 1151 ++++++ board/ti/am62ax/sec-cfg.yaml | 379 ++ board/ti/am62ax/tifs-rm-cfg.yaml | 1011 ++++++ board/ti/am62x/Kconfig | 2 + board/ti/am62x/board-cfg.yaml | 36 + board/ti/am62x/pm-cfg.yaml | 12 + board/ti/am62x/rm-cfg.yaml | 1088 ++++++ board/ti/am62x/sec-cfg.yaml | 379 ++ board/ti/am64x/Kconfig | 2 + board/ti/am64x/board-cfg.yaml | 36 + board/ti/am64x/pm-cfg.yaml | 12 + board/ti/am64x/rm-cfg.yaml | 1400 ++++++++ board/ti/am64x/sec-cfg.yaml | 380 ++ board/ti/am65x/Kconfig | 2 + board/ti/am65x/board-cfg.yaml | 36 + board/ti/am65x/pm-cfg.yaml | 12 + board/ti/am65x/rm-cfg.yaml | 2068 +++++++++++ board/ti/am65x/sec-cfg.yaml | 379 ++ board/ti/common/schema.yaml | 436 +++ board/ti/j721e/Kconfig | 4 + board/ti/j721e/board-cfg.yaml | 36 + board/ti/j721e/board-cfg_j7200.yaml | 36 + board/ti/j721e/pm-cfg.yaml | 12 + board/ti/j721e/pm-cfg_j7200.yaml | 12 + board/ti/j721e/rm-cfg.yaml | 3174 +++++++++++++++++ board/ti/j721e/rm-cfg_j7200.yaml | 2065 +++++++++++ board/ti/j721e/sec-cfg.yaml | 380 ++ board/ti/j721e/sec-cfg_j7200.yaml | 380 ++ board/ti/j721s2/Kconfig | 2 + board/ti/j721s2/board-cfg.yaml | 36 + board/ti/j721s2/pm-cfg.yaml | 12 + board/ti/j721s2/rm-cfg.yaml | 2901 +++++++++++++++ board/ti/j721s2/sec-cfg.yaml | 379 ++ board/ti/keys/custMpk.pem | 51 + board/ti/keys/ti-degenerate-key.pem | 10 + doc/board/ti/am62x_sk.rst | 54 +- doc/board/ti/j7200_evm.rst | 55 +- doc/board/ti/j721e_evm.rst | 58 +- doc/board/ti/k3.rst | 107 +- tools/binman/btool/openssl.py | 244 ++ tools/binman/entries.rst | 113 + tools/binman/etype/ti_board_config.py | 259 ++ tools/binman/etype/ti_secure.py | 78 + tools/binman/etype/ti_secure_rom.py | 249 ++ tools/binman/etype/x509_cert.py | 87 +- tools/binman/ftest.py | 90 +- tools/binman/image.py | 2 + tools/binman/test/277_ti_board_cfg.dts | 14 + .../binman/test/278_ti_board_cfg_combined.dts | 25 + .../binman/test/279_ti_board_cfg_no_type.dts | 11 + tools/binman/test/279_ti_secure.dts | 17 + tools/binman/test/280_ti_secure_rom.dts | 17 + .../test/281_ti_secure_rom_combined.dts | 25 + tools/binman/test/288_ti_secure_rom_a.dts | 19 + tools/binman/test/289_ti_secure_rom_b.dts | 18 + tools/binman/test/yaml/config.yaml | 18 + tools/binman/test/yaml/schema.yaml | 49 + tools/binman/test/yaml/schema_notype.yaml | 38 + tools/buildman/requirements.txt | 2 + tools/k3_fit_atf.sh | 123 - tools/k3_gen_x509_cert.sh | 262 -- 92 files changed, 23770 insertions(+), 660 deletions(-) create mode 100644 arch/arm/dts/k3-am625-sk-binman.dtsi create mode 100644 arch/arm/dts/k3-am62a-sk-binman.dtsi create mode 100644 arch/arm/dts/k3-am64x-binman.dtsi create mode 100644 arch/arm/dts/k3-am65x-binman.dtsi create mode 100644 arch/arm/dts/k3-binman.dtsi create mode 100644 arch/arm/dts/k3-j7200-binman.dtsi create mode 100644 arch/arm/dts/k3-j721e-binman.dtsi create mode 100644 arch/arm/dts/k3-j721s2-binman.dtsi delete mode 100644 arch/arm/mach-k3/config.mk create mode 100644 board/ti/am62ax/board-cfg.yaml create mode 100644 board/ti/am62ax/pm-cfg.yaml create mode 100644 board/ti/am62ax/rm-cfg.yaml create mode 100644 board/ti/am62ax/sec-cfg.yaml create mode 100644 board/ti/am62ax/tifs-rm-cfg.yaml create mode 100644 board/ti/am62x/board-cfg.yaml create mode 100644 board/ti/am62x/pm-cfg.yaml create mode 100644 board/ti/am62x/rm-cfg.yaml create mode 100644 board/ti/am62x/sec-cfg.yaml create mode 100644 board/ti/am64x/board-cfg.yaml create mode 100644 board/ti/am64x/pm-cfg.yaml create mode 100644 board/ti/am64x/rm-cfg.yaml create mode 100644 board/ti/am64x/sec-cfg.yaml create mode 100644 board/ti/am65x/board-cfg.yaml create mode 100644 board/ti/am65x/pm-cfg.yaml create mode 100644 board/ti/am65x/rm-cfg.yaml create mode 100644 board/ti/am65x/sec-cfg.yaml create mode 100644 board/ti/common/schema.yaml create mode 100644 board/ti/j721e/board-cfg.yaml create mode 100644 board/ti/j721e/board-cfg_j7200.yaml create mode 100644 board/ti/j721e/pm-cfg.yaml create mode 100644 board/ti/j721e/pm-cfg_j7200.yaml create mode 100644 board/ti/j721e/rm-cfg.yaml create mode 100644 board/ti/j721e/rm-cfg_j7200.yaml create mode 100644 board/ti/j721e/sec-cfg.yaml create mode 100644 board/ti/j721e/sec-cfg_j7200.yaml create mode 100644 board/ti/j721s2/board-cfg.yaml create mode 100644 board/ti/j721s2/pm-cfg.yaml create mode 100644 board/ti/j721s2/rm-cfg.yaml create mode 100644 board/ti/j721s2/sec-cfg.yaml create mode 100644 board/ti/keys/custMpk.pem create mode 100644 board/ti/keys/ti-degenerate-key.pem create mode 100644 tools/binman/etype/ti_board_config.py create mode 100644 tools/binman/etype/ti_secure.py create mode 100644 tools/binman/etype/ti_secure_rom.py create mode 100644 tools/binman/test/277_ti_board_cfg.dts create mode 100644 tools/binman/test/278_ti_board_cfg_combined.dts create mode 100644 tools/binman/test/279_ti_board_cfg_no_type.dts create mode 100644 tools/binman/test/279_ti_secure.dts create mode 100644 tools/binman/test/280_ti_secure_rom.dts create mode 100644 tools/binman/test/281_ti_secure_rom_combined.dts create mode 100644 tools/binman/test/288_ti_secure_rom_a.dts create mode 100644 tools/binman/test/289_ti_secure_rom_b.dts create mode 100644 tools/binman/test/yaml/config.yaml create mode 100644 tools/binman/test/yaml/schema.yaml create mode 100644 tools/binman/test/yaml/schema_notype.yaml create mode 100644 tools/buildman/requirements.txt delete mode 100755 tools/k3_fit_atf.sh delete mode 100755 tools/k3_gen_x509_cert.sh -- 2.34.1

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[PATCH v3] fpga: add inline stub for fpga_load
by Eugen Hristev 17 Jul '23

17 Jul '23

In case CC_OPTIMIZE_FOR_DEBUG is set, unused code will not be optimized out, hence the reference to fpga_load will be compiled. if DM_FPGA and SPL_FPGA are not set, the build will fail with : aarch64-none-linux-gnu-ld.bfd: common/spl/spl_fit.o: in function `spl_fit_upload_fpga': u-boot/common/spl/spl_fit.c:595: undefined reference to `fpga_load' To solve this, added an inline empty stub in the header if CC_OPTIMIZE_FOR_DEBUG is set such that the build will succeed. Signed-off-by: Eugen Hristev <eugen.hristev(a)collabora.com> --- Changes in v3: - return -ENOSYS Changes in v2: - this is a rework as suggested by Simon of this previous patch : https://patchwork.ozlabs.org/project/uboot/patch/20230619102839.277902-1-eu… include/fpga.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/fpga.h b/include/fpga.h index ed688cc0fa3b..33d0dbbe2ba4 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -60,8 +60,17 @@ int fpga_add(fpga_type devtype, void *desc); int fpga_count(void); const fpga_desc *const fpga_get_desc(int devnum); int fpga_is_partial_data(int devnum, size_t img_len); +#if defined(CONFIG_CC_OPTIMIZE_FOR_DEBUG) +static inline int fpga_load(int devnum, const void *buf, size_t bsize, + bitstream_type bstype, int flags) +{ + return -ENOSYS; +} +#else int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype, int flags); +#endif + int fpga_fsload(int devnum, const void *buf, size_t size, fpga_fs_info *fpga_fsinfo); int fpga_loads(int devnum, const void *buf, size_t size, -- 2.34.1

1 0

[PATCH v2] x86: Update docs link in bootparam header
by Paul Barker 17 Jul '23

17 Jul '23

After Linux commit ff61f0791ce9, x86 documentation was moved to arch/x86 and the link in bootparam.h was broken. Signed-off-by: Paul Barker <paul.barker.ct(a)bp.renesas.com> --- arch/x86/include/asm/bootparam.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h index ea816ca74698..ac4865300f1b 100644 --- a/arch/x86/include/asm/bootparam.h +++ b/arch/x86/include/asm/bootparam.h @@ -62,7 +62,7 @@ struct setup_indirect { /** * struct setup_header - Information needed by Linux to boot * - * See https://www.kernel.org/doc/html/latest/x86/boot.html + * See https://www.kernel.org/doc/html/latest/arch/x86/boot.html */ struct setup_header { __u8 setup_sects; base-commit: 0beb649053b86b2cfd5cf55a0fc68bc2fe91a430 -- 2.34.1

3 2

[PATCH 00/17] Hi,
by Michal Simek 17 Jul '23

17 Jul '23

sending couple of DT patches to be in sync with Linux repository. There are still some changes but we are working on it to get them fully in sync for SystemReady IR certification. Thanks, Michal Harini Katakam (3): arm64: zynqmp: Assign TSU clock frequency for KR260 arm64: zynqmp: Increase reset assert time for TI SGMII PHY arm64: zynqmp: Assign TSU clock frequency for KV and KD boards Manikanta Guntupalli (1): xilinx: dts: Fix open drain warning on Zynq, ZynqMP and Versal Michal Simek (8): arm64: zynqmp: Fix gpio comment about No of gpios arm64: zynqmp: Record compatible string for kv260 rev2 arm64: zynqmp: Cover K24 revB/1 SOM arm64: zynqmp: Fix usb reset over bootmode pins on zcu100 arm64: zynqmp: Sync node name address with reg (mailbox) arm64: zynqmp: Remove interrupt/reg-names for AMS arm64: zynqmp: Rename ams_ps/pl node names arm64: zynqmp: Remove clock-names from pcap node Parth Gajjar (1): arm64: zynqmp: Update MALI 400 interrupt and clock names Piyush Mehta (1): arm64: zynqmp: remove snps,enable_guctl1_resume_quirk quirk for usb Radhey Shyam Pandey (2): arm64: zynqmp: Add L2 cache nodes arm64: zynqmp: add pmu interrupt-affinity Varalaxmi Bingi (1): arm: xilinx: Setting default i2c clock frequency to 400kHz arch/arm/dts/zynq-7000.dtsi | 2 ++ arch/arm/dts/zynq-zc702.dts | 5 ++-- arch/arm/dts/zynqmp-clk-ccf.dtsi | 10 +++---- arch/arm/dts/zynqmp-dlc21-revA.dts | 2 +- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 6 ++--- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 +- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 8 +++--- arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 8 +++--- arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 5 ++-- arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 8 +++--- arch/arm/dts/zynqmp-sm-k24-revA.dts | 5 ++-- arch/arm/dts/zynqmp-sm-k26-revA.dts | 6 ++--- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 4 +-- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 4 +-- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 8 +++--- arch/arm/dts/zynqmp-zcu100-revC.dts | 6 +++-- arch/arm/dts/zynqmp-zcu102-revA.dts | 8 +++--- arch/arm/dts/zynqmp-zcu104-revA.dts | 4 +-- arch/arm/dts/zynqmp-zcu104-revC.dts | 4 +-- arch/arm/dts/zynqmp-zcu106-revA.dts | 8 +++--- arch/arm/dts/zynqmp-zcu111-revA.dts | 8 +++--- arch/arm/dts/zynqmp-zcu208-revA.dts | 10 +++---- arch/arm/dts/zynqmp-zcu216-revA.dts | 10 +++---- arch/arm/dts/zynqmp.dtsi | 33 ++++++++++++++++-------- 28 files changed, 103 insertions(+), 79 deletions(-) -- 2.36.1

1 18

[PATCH] mtd: Add missing MTD dependency for cfi_mtd
by Michal Simek 17 Jul '23

17 Jul '23

cfi_mtd requires add_mtd_device() which is available only when MTD is enabled that's why record this dependency. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- drivers/mtd/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 5fa88dae5f33..c56840c84975 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -128,7 +128,7 @@ config FLASH_SPANSION_S29WS_N config FLASH_CFI_MTD bool "Enable CFI MTD driver" - depends on FLASH_CFI_DRIVER + depends on FLASH_CFI_DRIVER && MTD help This option enables the building of the cfi_mtd driver in the drivers directory. The driver exports CFI flash -- 2.36.1

1 1

[PATCH] mmc: zynq_sdhci: Dll reset only for ZynqMP platform
by Michal Simek 17 Jul '23

17 Jul '23

From: Ashok Reddy Soma <ashok.reddy.soma(a)amd.com> Dll reset is needed only for ZynqMP platforms, add condition in tuning to call arasan_zynqmp_dll_reset() just for ZynqMP platforms. On other platforms like Versal NET, If this condition is not added, we see PLM error messages when dll reset smc is called. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma(a)amd.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- drivers/mmc/zynq_sdhci.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index e779251ce34f..935540d17194 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -422,7 +422,8 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) mdelay(1); - arasan_zynqmp_dll_reset(host, priv->node_id); + if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a")) + arasan_zynqmp_dll_reset(host, priv->node_id); sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); @@ -468,7 +469,9 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) } udelay(1); - arasan_zynqmp_dll_reset(host, priv->node_id); + + if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a")) + arasan_zynqmp_dll_reset(host, priv->node_id); /* Enable only interrupts served by the SD controller */ sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, -- 2.36.1

2 4

[PATCH] mtd: spi-nor: Add support for w25q256jwm
by Venkatesh Yadav Abbarapu 17 Jul '23

17 Jul '23

Add support for Winbond 256M-bit flash w25q256jwm. Performed basic erase/write/readback operations on ZynqMP zc1751+dc1 board. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- drivers/mtd/spi/spi-nor-ids.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3f8b796789..53a743a038 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -446,6 +446,11 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q256jwm", 0xef8019, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K) }, { INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128, -- 2.17.1

2 1

[PATCH v2] xilinx: zynqmp: Extract aes operation into new file
by christian.taedcke-oss＠weidmueller.com 17 Jul '23

17 Jul '23

From: Christian Taedcke <christian.taedcke(a)weidmueller.com> This moves the aes operation that is performed by the pmu into a separate file. This way it can be called not just from the shell command, but also e.g. from board initialization code. Signed-off-by: Christian Taedcke <christian.taedcke(a)weidmueller.com> --- Changes in v2: - convert doxygen comments to kernel-doc - fix typos - fix header license - fix do_zynqmp_aes() return value arch/arm/mach-zynqmp/Makefile | 3 +- arch/arm/mach-zynqmp/aes.c | 58 +++++++++++++++++++ .../arm/mach-zynqmp/include/mach/zynqmp_aes.h | 32 ++++++++++ board/xilinx/zynqmp/cmds.c | 43 +------------- 4 files changed, 94 insertions(+), 42 deletions(-) create mode 100644 arch/arm/mach-zynqmp/aes.c create mode 100644 arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile index bb1830c846..1a76493bef 100644 --- a/arch/arm/mach-zynqmp/Makefile +++ b/arch/arm/mach-zynqmp/Makefile @@ -3,8 +3,7 @@ # (C) Copyright 2014 - 2015 Xilinx, Inc. # Michal Simek <michal.simek(a)xilinx.com> -obj-y += clk.o -obj-y += cpu.o +obj-y += aes.o clk.o cpu.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o diff --git a/arch/arm/mach-zynqmp/aes.c b/arch/arm/mach-zynqmp/aes.c new file mode 100644 index 0000000000..115bca8338 --- /dev/null +++ b/arch/arm/mach-zynqmp/aes.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2018 Xilinx, Inc. + * Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> + * + * Copyright (C) 2023 Weidmueller Interface GmbH & Co. KG <oss(a)weidmueller.com> + * Christian Taedcke <christian.taedcke(a)weidmueller.com> + */ + +#include <common.h> +#include <mach/zynqmp_aes.h> + +#include <asm/arch/sys_proto.h> +#include <cpu_func.h> +#include <memalign.h> +#include <zynqmp_firmware.h> + +int zynqmp_aes_operation(struct zynqmp_aes *aes) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (zynqmp_firmware_version() <= PMUFW_V1_0) + return -ENOENT; + + if (aes->srcaddr && aes->ivaddr && aes->dstaddr) { + flush_dcache_range(aes->srcaddr, + (aes->srcaddr + + roundup(aes->len, ARCH_DMA_MINALIGN))); + flush_dcache_range(aes->ivaddr, + (aes->ivaddr + + roundup(IV_SIZE, ARCH_DMA_MINALIGN))); + flush_dcache_range(aes->dstaddr, + (aes->dstaddr + + roundup(aes->len, ARCH_DMA_MINALIGN))); + } + + if (aes->keysrc == 0) { + if (aes->keyaddr == 0) + return -EINVAL; + + flush_dcache_range(aes->keyaddr, (aes->keyaddr + + roundup(KEY_PTR_LEN, ARCH_DMA_MINALIGN))); + } + + flush_dcache_range((ulong)aes, (ulong)(aes) + + roundup(sizeof(struct zynqmp_aes), ARCH_DMA_MINALIGN)); + + ret = xilinx_pm_request(PM_SECURE_AES, upper_32_bits((ulong)aes), + lower_32_bits((ulong)aes), 0, 0, ret_payload); + if (ret || ret_payload[1]) { + printf("Failed: AES op status:0x%x, errcode:0x%x\n", + ret, ret_payload[1]); + return -EIO; + } + + return 0; +} diff --git a/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h b/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h new file mode 100644 index 0000000000..5bffb6b64c --- /dev/null +++ b/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Weidmueller Interface GmbH & Co. KG <oss(a)weidmueller.com> + * Christian Taedcke <christian.taedcke(a)weidmueller.com> + * + * Declaration of AES operation functionality for ZynqMP. + */ + +#ifndef ZYNQMP_AES_H +#define ZYNQMP_AES_H + +struct zynqmp_aes { + u64 srcaddr; + u64 ivaddr; + u64 keyaddr; + u64 dstaddr; + u64 len; + u64 op; + u64 keysrc; +}; + +/* + * Performs an aes operation using the pmu firmware + * + * @aes The aes operation buffer that must have been allocated using + * ALLOC_CACHE_ALIGN_BUFFER(struct zynqmp_aes, aes, 1). + * + * Return: 0 in case of success, in case of an error any other value + */ +int zynqmp_aes_operation(struct zynqmp_aes *aes); + +#endif /* ZYNQMP_AES_H */ diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c index e20030ecda..dfa25f6d0d 100644 --- a/board/xilinx/zynqmp/cmds.c +++ b/board/xilinx/zynqmp/cmds.c @@ -14,16 +14,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> - -struct aes { - u64 srcaddr; - u64 ivaddr; - u64 keyaddr; - u64 dstaddr; - u64 len; - u64 op; - u64 keysrc; -}; +#include <mach/zynqmp_aes.h> static int do_zynqmp_verify_secure(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -121,9 +112,7 @@ static int do_zynqmp_mmio_write(struct cmd_tbl *cmdtp, int flag, int argc, static int do_zynqmp_aes(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) { - ALLOC_CACHE_ALIGN_BUFFER(struct aes, aes, 1); - int ret; - u32 ret_payload[PAYLOAD_ARG_CNT]; + ALLOC_CACHE_ALIGN_BUFFER(struct zynqmp_aes, aes, 1); if (zynqmp_firmware_version() <= PMUFW_V1_0) { puts("ERR: PMUFW v1.0 or less is detected\n"); @@ -142,40 +131,14 @@ static int do_zynqmp_aes(struct cmd_tbl *cmdtp, int flag, int argc, aes->keysrc = hextoul(argv[6], NULL); aes->dstaddr = hextoul(argv[7], NULL); - if (aes->srcaddr && aes->ivaddr && aes->dstaddr) { - flush_dcache_range(aes->srcaddr, - (aes->srcaddr + - roundup(aes->len, ARCH_DMA_MINALIGN))); - flush_dcache_range(aes->ivaddr, - (aes->ivaddr + - roundup(IV_SIZE, ARCH_DMA_MINALIGN))); - flush_dcache_range(aes->dstaddr, - (aes->dstaddr + - roundup(aes->len, ARCH_DMA_MINALIGN))); - } - if (aes->keysrc == 0) { if (argc < cmdtp->maxargs) return CMD_RET_USAGE; aes->keyaddr = hextoul(argv[8], NULL); - if (aes->keyaddr) - flush_dcache_range(aes->keyaddr, - (aes->keyaddr + - roundup(KEY_PTR_LEN, - ARCH_DMA_MINALIGN))); } - flush_dcache_range((ulong)aes, (ulong)(aes) + - roundup(sizeof(struct aes), ARCH_DMA_MINALIGN)); - - ret = xilinx_pm_request(PM_SECURE_AES, upper_32_bits((ulong)aes), - lower_32_bits((ulong)aes), 0, 0, ret_payload); - if (ret || ret_payload[1]) - printf("Failed: AES op status:0x%x, errcode:0x%x\n", - ret, ret_payload[1]); - - return ret; + return zynqmp_aes_operation(aes); } #ifdef CONFIG_DEFINE_TCM_OCM_MMAP -- 2.34.1

2 1

[PATCH] arm64: zynqmp: Switch to amd.com emails
by Michal Simek 17 Jul '23

17 Jul '23

Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- The same changes have been done in Linux. Link: https://lore.kernel.org/r/108cbbbab29e13d386d38a779fd582f10844a030.16854433… --- arch/arm/dts/avnet-ultra96-rev1.dts | 2 +- arch/arm/dts/versal-mini-emmc0.dts | 4 ++-- arch/arm/dts/versal-mini-emmc1.dts | 4 ++-- arch/arm/dts/versal-mini-ospi.dtsi | 4 ++-- arch/arm/dts/versal-mini-qspi.dtsi | 4 ++-- arch/arm/dts/versal-mini.dts | 2 +- arch/arm/dts/zynq-dlc20-rev1.0.dts | 2 +- arch/arm/dts/zynq-minized.dts | 2 +- arch/arm/dts/zynqmp-a2197-revA.dts | 2 +- arch/arm/dts/zynqmp-clk-ccf.dtsi | 2 +- arch/arm/dts/zynqmp-dlc21-revA.dts | 2 +- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 +- arch/arm/dts/zynqmp-mini-emmc0.dts | 2 +- arch/arm/dts/zynqmp-mini-emmc1.dts | 2 +- arch/arm/dts/zynqmp-mini-nand.dts | 4 ++-- arch/arm/dts/zynqmp-mini-qspi.dts | 4 ++-- arch/arm/dts/zynqmp-mini.dts | 2 +- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-r5.dts | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 2 +- arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 2 +- arch/arm/dts/zynqmp-sm-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-smk-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1232-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1254-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 4 ++-- arch/arm/dts/zynqmp-zcu100-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 2 +- arch/arm/dts/zynqmp-zcu102-rev1.1.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revB.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu106-rev1.0.dts | 2 +- arch/arm/dts/zynqmp-zcu106-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu111-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu1275-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zcu1275-revB.dts | 4 ++-- arch/arm/dts/zynqmp-zcu1285-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +- arch/arm/dts/zynqmp.dtsi | 2 +- arch/arm/mach-tegra/arm64-mmu.c | 2 +- arch/arm/mach-versal/Makefile | 2 +- arch/arm/mach-versal/clk.c | 2 +- arch/arm/mach-versal/cpu.c | 2 +- arch/arm/mach-versal/mp.c | 2 +- arch/arm/mach-zynqmp/Makefile | 2 +- arch/arm/mach-zynqmp/clk.c | 2 +- arch/arm/mach-zynqmp/cpu.c | 2 +- arch/arm/mach-zynqmp/handoff.c | 2 +- arch/arm/mach-zynqmp/include/mach/clk.h | 2 +- arch/arm/mach-zynqmp/include/mach/hardware.h | 2 +- arch/arm/mach-zynqmp/include/mach/sys_proto.h | 2 +- arch/arm/mach-zynqmp/mp.c | 2 +- arch/arm/mach-zynqmp/psu_spl_init.c | 2 +- arch/arm/mach-zynqmp/spl.c | 2 +- arch/microblaze/cpu/spl.c | 2 +- arch/microblaze/cpu/u-boot-spl.lds | 2 +- arch/microblaze/include/asm/spl.h | 2 +- board/xilinx/common/Makefile | 2 +- board/xilinx/common/board.h | 2 +- board/xilinx/common/cpu-info.c | 2 +- board/xilinx/common/fru.h | 2 +- board/xilinx/versal/Makefile | 2 +- board/xilinx/versal/board.c | 2 +- board/xilinx/versal/cmds.c | 2 +- board/xilinx/zynqmp/Makefile | 2 +- board/xilinx/zynqmp/cmds.c | 2 +- board/xilinx/zynqmp/zynqmp.c | 2 +- common/spl/spl_ram.c | 2 +- drivers/ata/sata_ceva.c | 2 +- drivers/clk/clk_versal.c | 2 +- drivers/fpga/versalpl.c | 2 +- drivers/fpga/zynqmppl.c | 4 ++-- drivers/net/xilinx_axi_mrmac.c | 2 +- drivers/net/xilinx_axi_mrmac.h | 2 +- drivers/pinctrl/pinctrl-zynqmp.c | 2 +- drivers/soc/soc_xilinx_zynqmp.c | 2 +- drivers/watchdog/xilinx_tb_wdt.c | 2 +- drivers/watchdog/xilinx_wwdt.c | 2 +- include/configs/xilinx_versal.h | 2 +- include/configs/xilinx_versal_mini.h | 4 ++-- include/configs/xilinx_zynqmp.h | 2 +- include/configs/xilinx_zynqmp_mini.h | 4 ++-- include/configs/xilinx_zynqmp_mini_nand.h | 4 ++-- include/versalpl.h | 2 +- include/zynqmppl.h | 2 +- tools/zynqmp_psu_init_minimize.sh | 2 +- tools/zynqmpimage.c | 2 +- tools/zynqmpimage.h | 2 +- 101 files changed, 116 insertions(+), 116 deletions(-) diff --git a/arch/arm/dts/avnet-ultra96-rev1.dts b/arch/arm/dts/avnet-ultra96-rev1.dts index ddb8febaece1..96a6403efaf3 100644 --- a/arch/arm/dts/avnet-ultra96-rev1.dts +++ b/arch/arm/dts/avnet-ultra96-rev1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018 - 2020, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts index 1863d29d3dac..bd685ddfdb42 100644 --- a/arch/arm/dts/versal-mini-emmc0.dts +++ b/arch/arm/dts/versal-mini-emmc0.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.paladugu(a)xilinx.com> - * Michal Simek <michal.simek(a)xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu(a)amd.com>> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts index 8701c3bb2732..fbdcf5d77f56 100644 --- a/arch/arm/dts/versal-mini-emmc1.dts +++ b/arch/arm/dts/versal-mini-emmc1.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.paladugu(a)xilinx.com> - * Michal Simek <michal.simek(a)xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu(a)amd.com>> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi index 2d04521dd679..19caea7368a0 100644 --- a/arch/arm/dts/versal-mini-ospi.dtsi +++ b/arch/arm/dts/versal-mini-ospi.dtsi @@ -4,8 +4,8 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.paladugu(a)xilinx.com> - * Michal Simek <michal.simek(a)xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu(a)amd.com>> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/versal-mini-qspi.dtsi b/arch/arm/dts/versal-mini-qspi.dtsi index bb8819dd25ff..2fec92ce3ec8 100644 --- a/arch/arm/dts/versal-mini-qspi.dtsi +++ b/arch/arm/dts/versal-mini-qspi.dtsi @@ -4,8 +4,8 @@ * * (C) Copyright 2018-2019, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.paladugu(a)xilinx.com> - * Michal Simek <michal.simek(a)xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu(a)amd.com>> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/versal-mini.dts b/arch/arm/dts/versal-mini.dts index 769eb9e7b294..a213b745bc26 100644 --- a/arch/arm/dts/versal-mini.dts +++ b/arch/arm/dts/versal-mini.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu(a)amd.com>> */ /dts-v1/; diff --git a/arch/arm/dts/zynq-dlc20-rev1.0.dts b/arch/arm/dts/zynq-dlc20-rev1.0.dts index cfe07102297b..d06838c5eeb3 100644 --- a/arch/arm/dts/zynq-dlc20-rev1.0.dts +++ b/arch/arm/dts/zynq-dlc20-rev1.0.dts @@ -2,7 +2,7 @@ /* * Copyright (C) 2018 Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; #include "zynq-7000.dtsi" diff --git a/arch/arm/dts/zynq-minized.dts b/arch/arm/dts/zynq-minized.dts index 38365d1c0ecb..3214ee49e283 100644 --- a/arch/arm/dts/zynq-minized.dts +++ b/arch/arm/dts/zynq-minized.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2018, Xilinx, Inc. * - * Ibai Erkiaga <ibai.erkiaga-elorza(a)xilinx.com> + * Ibai Erkiaga <ibai.erkiaga-elorza(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-a2197-revA.dts b/arch/arm/dts/zynqmp-a2197-revA.dts index 04f9f025e5ca..84167050d10e 100644 --- a/arch/arm/dts/zynqmp-a2197-revA.dts +++ b/arch/arm/dts/zynqmp-a2197-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 38dc9cd8fc05..173e4bc5f1d8 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <dt-bindings/clock/xlnx-zynqmp-clk.h> diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index 7460e4a4fdea..e287a9b6591c 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 3fa18f560c9c..e24d070adb69 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index 02d2427809d5..b185669b9c5e 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 2d7fe592c8f9..aa4f7c23ede5 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index e46748d32c03..7aa8c2b4d1f6 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index f564817e2c84..459736abe6bc 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts index d1e58eb6d135..08ec2f7b4a9a 100644 --- a/arch/arm/dts/zynqmp-mini-emmc0.dts +++ b/arch/arm/dts/zynqmp-mini-emmc0.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.paladugu(a)xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu(a)amd.com>> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts index 0c139f82aa0b..905de08fdb0b 100644 --- a/arch/arm/dts/zynqmp-mini-emmc1.dts +++ b/arch/arm/dts/zynqmp-mini-emmc1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.paladugu(a)xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu(a)amd.com>> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts index 8fae01b250d4..e5688fd703e6 100644 --- a/arch/arm/dts/zynqmp-mini-nand.dts +++ b/arch/arm/dts/zynqmp-mini-nand.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.paladugu(a)xilinx.com> - * Michal Simek <michal.simek(a)xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu(a)amd.com>> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts index a7cf4eff6cc2..fc0a2e801e49 100644 --- a/arch/arm/dts/zynqmp-mini-qspi.dts +++ b/arch/arm/dts/zynqmp-mini-qspi.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2015 - 2020, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.paladugu(a)xilinx.com> - * Michal Simek <michal.simek(a)xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu(a)amd.com>> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-mini.dts b/arch/arm/dts/zynqmp-mini.dts index 15bee169a90c..b9a24f043635 100644 --- a/arch/arm/dts/zynqmp-mini.dts +++ b/arch/arm/dts/zynqmp-mini.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index d63deb83e3c6..d5f4a16f20eb 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2019, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-r5.dts b/arch/arm/dts/zynqmp-r5.dts index 9789d7144e6f..77b15fe158cf 100644 --- a/arch/arm/dts/zynqmp-r5.dts +++ b/arch/arm/dts/zynqmp-r5.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts index c82e1dfac9da..95347604a27b 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <dt-bindings/gpio/gpio.h> diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts index 9dd160c7a7c9..26ac540e7b0e 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2021 - 2022, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <dt-bindings/gpio/gpio.h> diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts index 6f5a42606568..2b6c3946e858 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts @@ -9,7 +9,7 @@ * "Y" – A01 board modified with legacy interposer (Nexperia) * "Z" – A01 board modified with Diode interposer * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <dt-bindings/gpio/gpio.h> diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index 7764adf1295f..308d7876b882 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2020 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <dt-bindings/gpio/gpio.h> diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index eac0b55de368..e9ec4b79fc1f 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2020 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-smk-k26-revA.dts b/arch/arm/dts/zynqmp-smk-k26-revA.dts index c70966c1f344..85b0d1677240 100644 --- a/arch/arm/dts/zynqmp-smk-k26-revA.dts +++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2020 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include "zynqmp-sm-k26-revA.dts" diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts index 63c553f77242..a288029797b6 100644 --- a/arch/arm/dts/zynqmp-zc1232-revA.dts +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts index 343033cc7e88..5c4acd17cc5d 100644 --- a/arch/arm/dts/zynqmp-zc1254-revA.dts +++ b/arch/arm/dts/zynqmp-zc1254-revA.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2015 - 2020, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> - * Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu(a)amd.com>> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 7ea2a1c96f4e..b663651583c3 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index b6bc2f5be031..9d0cf11665c6 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index 6021f8b4e1be..69ad58039e79 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index e153a64f4fb6..3017c9b29a2b 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index ae2d03d98322..7f973fcf4da4 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Siva Durga Prasad <siva.durga.paladugu(a)xilinx.com> - * Michal Simek <michal.simek(a)xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu(a)amd.com>> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 742a53986467..116037dbe73f 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> * Nathalie Chan King Choy */ diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts index d508f3359943..c0a4d913afea 100644 --- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2020, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include "zynqmp-zcu102-revB.dts" diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.1.dts b/arch/arm/dts/zynqmp-zcu102-rev1.1.dts index b6798394fcf4..705369766a55 100644 --- a/arch/arm/dts/zynqmp-zcu102-rev1.1.dts +++ b/arch/arm/dts/zynqmp-zcu102-rev1.1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2020, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include "zynqmp-zcu102-rev1.0.dts" diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index d78bfb8987fc..8823eb2462e4 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index de3b5ab9d93b..ce0a6e5f60a7 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2020, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include "zynqmp-zcu102-revA.dts" diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index b9d82afc5188..92e01ac921e3 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 6f24e335a19c..c61d8b15ee23 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu106-rev1.0.dts b/arch/arm/dts/zynqmp-zcu106-rev1.0.dts index f43c477a17fb..a9b5826a777d 100644 --- a/arch/arm/dts/zynqmp-zcu106-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu106-rev1.0.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2022, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include "zynqmp-zcu106-revA.dts" diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 266c24e41259..67775eceaa84 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 8535cc089132..7fc1aa238a60 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index e88fc23b1f14..9404c139a24b 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> - * Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu(a)amd.com>> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index 97ae1b2d2d71..c06d262506d0 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2018 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> - * Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu(a)amd.com>> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts index eaf99a9fa82d..99ea143c02ea 100644 --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2018 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> - * Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu(a)amd.com>> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 7e7e1577eb5b..1fac632d6317 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 35a30971cb73..ea96f5c80141 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 6a166381fa77..c9640c44451f 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -4,7 +4,7 @@ * * (C) Copyright 2014 - 2021, Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c index d45b1faaa2c2..ea4eac392d96 100644 --- a/arch/arm/mach-tegra/arm64-mmu.c +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> * (This file derived from arch/arm/mach-zynqmp/cpu.c) * * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. diff --git a/arch/arm/mach-versal/Makefile b/arch/arm/mach-versal/Makefile index ca12e29170d3..864b3053d698 100644 --- a/arch/arm/mach-versal/Makefile +++ b/arch/arm/mach-versal/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2016 - 2018 Xilinx, Inc. -# Michal Simek <michal.simek(a)xilinx.com> +# Michal Simek <michal.simek(a)amd.com> # obj-y += clk.o diff --git a/arch/arm/mach-versal/clk.c b/arch/arm/mach-versal/clk.c index 249e050cc8d6..5e3f44c77822 100644 --- a/arch/arm/mach-versal/clk.c +++ b/arch/arm/mach-versal/clk.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2016 - 2018 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <common.h> diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 9dc308bbc3d9..e4dc305d9288 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2016 - 2018 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <common.h> diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c index 5b850f3f89fb..7bd39289fac5 100644 --- a/arch/arm/mach-versal/mp.c +++ b/arch/arm/mach-versal/mp.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2019 Xilinx, Inc. - * Siva Durga Prasad <siva.durga.paladugu(a)xilinx.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu(a)amd.com>> */ #include <common.h> diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile index bb1830c84625..3f2555494399 100644 --- a/arch/arm/mach-zynqmp/Makefile +++ b/arch/arm/mach-zynqmp/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2014 - 2015 Xilinx, Inc. -# Michal Simek <michal.simek(a)xilinx.com> +# Michal Simek <michal.simek(a)amd.com> obj-y += clk.o obj-y += cpu.o diff --git a/arch/arm/mach-zynqmp/clk.c b/arch/arm/mach-zynqmp/clk.c index 1e6e726e8792..3b05f8455bf5 100644 --- a/arch/arm/mach-zynqmp/clk.c +++ b/arch/arm/mach-zynqmp/clk.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <common.h> diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 26e285c24fe0..6ae27894ecd9 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <common.h> diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c index 511b241462f9..dce92438926e 100644 --- a/arch/arm/mach-zynqmp/handoff.c +++ b/arch/arm/mach-zynqmp/handoff.c @@ -2,7 +2,7 @@ /* * Copyright 2016 - 2017 Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <common.h> diff --git a/arch/arm/mach-zynqmp/include/mach/clk.h b/arch/arm/mach-zynqmp/include/mach/clk.h index cfd44c8e0f7a..9918d469122d 100644 --- a/arch/arm/mach-zynqmp/include/mach/clk.h +++ b/arch/arm/mach-zynqmp/include/mach/clk.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #ifndef _ASM_ARCH_CLK_H_ diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index 70221e03057f..634bf169c637 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #ifndef _ASM_ARCH_HARDWARE_H diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index ede00d73fe0c..15b69e777124 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #ifndef _ASM_ARCH_SYS_PROTO_H diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index 4c514258ba69..aff9054212c5 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <common.h> diff --git a/arch/arm/mach-zynqmp/psu_spl_init.c b/arch/arm/mach-zynqmp/psu_spl_init.c index 5c5c7d136e77..b4d7f44bbeee 100644 --- a/arch/arm/mach-zynqmp/psu_spl_init.c +++ b/arch/arm/mach-zynqmp/psu_spl_init.c @@ -2,7 +2,7 @@ /* * Copyright 2018 Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <common.h> #include <asm/io.h> diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index b428fd53121a..a0f35f36faac 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -2,7 +2,7 @@ /* * Copyright 2015 - 2016 Xilinx, Inc. * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <common.h> diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c index eaa095ba99fa..c21beafdb810 100644 --- a/arch/microblaze/cpu/spl.c +++ b/arch/microblaze/cpu/spl.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2013 - 2014 Xilinx, Inc * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <common.h> diff --git a/arch/microblaze/cpu/u-boot-spl.lds b/arch/microblaze/cpu/u-boot-spl.lds index 597095195cae..09abbea84d06 100644 --- a/arch/microblaze/cpu/u-boot-spl.lds +++ b/arch/microblaze/cpu/u-boot-spl.lds @@ -2,7 +2,7 @@ /* * (C) Copyright 2013 - 2014 Xilinx, Inc * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <asm-offsets.h> diff --git a/arch/microblaze/include/asm/spl.h b/arch/microblaze/include/asm/spl.h index 350d283124e8..7557dc2a5a39 100644 --- a/arch/microblaze/include/asm/spl.h +++ b/arch/microblaze/include/asm/spl.h @@ -2,7 +2,7 @@ /* * (C) Copyright 2013 - 2014 Xilinx, Inc * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #ifndef _ASM_MICROBLAZE_SPL_H_ diff --git a/board/xilinx/common/Makefile b/board/xilinx/common/Makefile index cdc3c9677432..d563290ab901 100644 --- a/board/xilinx/common/Makefile +++ b/board/xilinx/common/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 # # (C) Copyright 2020 Xilinx, Inc. -# Michal Simek <michal.simek(a)xilinx.com> +# Michal Simek <michal.simek(a)amd.com> # obj-y += board.o diff --git a/board/xilinx/common/board.h b/board/xilinx/common/board.h index 922c9d557af0..64d657673e92 100644 --- a/board/xilinx/common/board.h +++ b/board/xilinx/common/board.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * (C) Copyright 2020 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #ifndef _BOARD_XILINX_COMMON_BOARD_H diff --git a/board/xilinx/common/cpu-info.c b/board/xilinx/common/cpu-info.c index 4eccc7abbea5..bfe7f5b7e385 100644 --- a/board/xilinx/common/cpu-info.c +++ b/board/xilinx/common/cpu-info.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2020 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <common.h> diff --git a/board/xilinx/common/fru.h b/board/xilinx/common/fru.h index 586c41b66ef7..2b3fa05a6136 100644 --- a/board/xilinx/common/fru.h +++ b/board/xilinx/common/fru.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2019 Xilinx, Inc. - * Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu(a)amd.com>> */ #ifndef __FRU_H diff --git a/board/xilinx/versal/Makefile b/board/xilinx/versal/Makefile index 4a46ca02d705..d912f2e74f34 100644 --- a/board/xilinx/versal/Makefile +++ b/board/xilinx/versal/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2016 - 2018 Xilinx, Inc. -# Michal Simek <michal.simek(a)xilinx.com> +# Michal Simek <michal.simek(a)amd.com> # obj-y := board.o diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 81e1b69905e9..60bf37d3c90f 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2018 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <command.h> diff --git a/board/xilinx/versal/cmds.c b/board/xilinx/versal/cmds.c index 797c1a5d6892..148fa51266d2 100644 --- a/board/xilinx/versal/cmds.c +++ b/board/xilinx/versal/cmds.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2020 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <cpu_func.h> diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 732f909fc215..204e4fadf0ed 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2014 - 2016 Xilinx, Inc. -# Michal Simek <michal.simek(a)xilinx.com> +# Michal Simek <michal.simek(a)amd.com> obj-y := zynqmp.o diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c index dd1ad66f90c0..ea404d547f6c 100644 --- a/board/xilinx/zynqmp/cmds.c +++ b/board/xilinx/zynqmp/cmds.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2018 Xilinx, Inc. - * Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu(a)amd.com>> */ #include <common.h> diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 39da96bcfb08..309f24a5f43d 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <common.h> diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c index 8139a203273c..93cf420d810a 100644 --- a/common/spl/spl_ram.c +++ b/common/spl/spl_ram.c @@ -6,7 +6,7 @@ * (C) Copyright 2016 * Toradex AG * - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> * Stefan Agner <stefan.agner(a)toradex.com> */ #include <common.h> diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c index 43bcc59cd282..47366438fdfd 100644 --- a/drivers/ata/sata_ceva.c +++ b/drivers/ata/sata_ceva.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2015 - 2016 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #include <common.h> #include <dm.h> diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index faebbab1c6d3..b3b333312358 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2019 Xilinx, Inc. - * Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu(a)amd.com>> */ #include <common.h> diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c index d3876a8f541a..be58db54275c 100644 --- a/drivers/fpga/versalpl.c +++ b/drivers/fpga/versalpl.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2019, Xilinx, Inc, - * Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu(a)amd.com>> */ #include <common.h> diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 7b5128fe27a1..b1f201fb18ba 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2015 - 2016, Xilinx, Inc, - * Michal Simek <michal.simek(a)xilinx.com> - * Siva Durga Prasad <siva.durga.paladugu(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> + * Siva Durga Prasad <siva.durga.prasad.paladugu(a)amd.com>> */ #include <console.h> diff --git a/drivers/net/xilinx_axi_mrmac.c b/drivers/net/xilinx_axi_mrmac.c index 6d15386c66ca..410fb25ddef4 100644 --- a/drivers/net/xilinx_axi_mrmac.c +++ b/drivers/net/xilinx_axi_mrmac.c @@ -3,7 +3,7 @@ * Xilinx Multirate Ethernet MAC(MRMAC) driver * * Author(s): Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> * * Copyright (C) 2021 Xilinx, Inc. All rights reserved. */ diff --git a/drivers/net/xilinx_axi_mrmac.h b/drivers/net/xilinx_axi_mrmac.h index 4f875857cf7f..e2c2105450ce 100644 --- a/drivers/net/xilinx_axi_mrmac.h +++ b/drivers/net/xilinx_axi_mrmac.h @@ -3,7 +3,7 @@ * Xilinx Multirate Ethernet MAC(MRMAC) driver * * Author(s): Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> * * Copyright (C) 2021 Xilinx, Inc. All rights reserved. */ diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index ee6529b3c295..02626a7561e8 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -3,7 +3,7 @@ * Xilinx pinctrl driver for ZynqMP * * Author(s): Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> * * Copyright (C) 2021 Xilinx, Inc. All rights reserved. */ diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index afa277f6049f..d9a5944965ba 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -3,7 +3,7 @@ * Xilinx ZynqMP SOC driver * * Copyright (C) 2021 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> * * Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG * Stefan Herbrechtsmeier <stefan.herbrechtsmeier(a)weidmueller.com> diff --git a/drivers/watchdog/xilinx_tb_wdt.c b/drivers/watchdog/xilinx_tb_wdt.c index 0f9fb0200289..b38c40001611 100644 --- a/drivers/watchdog/xilinx_tb_wdt.c +++ b/drivers/watchdog/xilinx_tb_wdt.c @@ -2,7 +2,7 @@ /* * Xilinx AXI platforms watchdog timer driver. * - * Author(s): Michal Simek <michal.simek(a)xilinx.com> + * Author(s): Michal Simek <michal.simek(a)amd.com> * Shreenidhi Shedi <yesshedi(a)gmail.com> * * Copyright (c) 2011-2018 Xilinx Inc. diff --git a/drivers/watchdog/xilinx_wwdt.c b/drivers/watchdog/xilinx_wwdt.c index 8b6fc30edbe3..963ab22fb452 100644 --- a/drivers/watchdog/xilinx_wwdt.c +++ b/drivers/watchdog/xilinx_wwdt.c @@ -2,7 +2,7 @@ /* * Xilinx window watchdog timer driver. * - * Author(s): Michal Simek <michal.simek(a)xilinx.com> + * Author(s): Michal Simek <michal.simek(a)amd.com> * Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> * * Copyright (c) 2020, Xilinx Inc. diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index e70acd93bac4..a403999977e4 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -2,7 +2,7 @@ /* * Configuration for Xilinx Versal * (C) Copyright 2016 - 2018 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> * * Based on Configuration for Xilinx ZynqMP */ diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h index 23655a475221..628fd80baa62 100644 --- a/include/configs/xilinx_versal_mini.h +++ b/include/configs/xilinx_versal_mini.h @@ -3,8 +3,8 @@ * Configuration for Xilinx Versal MINI configuration * * (C) Copyright 2018-2019 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> - * Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu(a)amd.com>> */ #ifndef __CONFIG_VERSAL_MINI_H diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index f9ffcd6de61b..a8edf13e3465 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -2,7 +2,7 @@ /* * Configuration for Xilinx ZynqMP * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> * * Based on Configuration for Versatile Express */ diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h index 9af05456640b..8afccb7f7375 100644 --- a/include/configs/xilinx_zynqmp_mini.h +++ b/include/configs/xilinx_zynqmp_mini.h @@ -3,8 +3,8 @@ * Configuration for Xilinx ZynqMP Flash utility * * (C) Copyright 2018 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> - * Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu(a)amd.com>> */ #ifndef __CONFIG_ZYNQMP_MINI_H diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h index 1b6e26ee3966..cf3747aab147 100644 --- a/include/configs/xilinx_zynqmp_mini_nand.h +++ b/include/configs/xilinx_zynqmp_mini_nand.h @@ -3,8 +3,8 @@ * Configuration for Xilinx ZynqMP Nand Flash utility * * (C) Copyright 2018 Xilinx, Inc. - * Michal Simek <michal.simek(a)xilinx.com> - * Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu(a)amd.com>> */ #ifndef __CONFIG_ZYNQMP_MINI_NAND_H diff --git a/include/versalpl.h b/include/versalpl.h index 0cc101be2f84..7dae56b23609 100644 --- a/include/versalpl.h +++ b/include/versalpl.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * (C) Copyright 2019 Xilinx, Inc, - * Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu(a)amd.com>> */ #ifndef _VERSALPL_H_ diff --git a/include/zynqmppl.h b/include/zynqmppl.h index acf75a8f079c..3fd334a54d35 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * (C) Copyright 2015 Xilinx, Inc, - * Michal Simek <michal.simek(a)xilinx.com> + * Michal Simek <michal.simek(a)amd.com> */ #ifndef _ZYNQMPPL_H_ diff --git a/tools/zynqmp_psu_init_minimize.sh b/tools/zynqmp_psu_init_minimize.sh index 16c622f6ce7f..5c8b73703bfb 100755 --- a/tools/zynqmp_psu_init_minimize.sh +++ b/tools/zynqmp_psu_init_minimize.sh @@ -1,6 +1,6 @@ #!/bin/bash # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2018 Michal Simek <michal.simek(a)xilinx.com> +# Copyright (C) 2018 Michal Simek <michal.simek(a)amd.com> # Copyright (C) 2019 Luca Ceresoli <luca(a)lucaceresoli.net> # Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG # Stefan Herbrechtsmeier <stefan.herbrechtsmeier(a)weidmueller.com> diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c index 5113ba895f0d..bb54f41a153d 100644 --- a/tools/zynqmpimage.c +++ b/tools/zynqmpimage.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2016 Michal Simek <michals(a)xilinx.com> + * Copyright (C) 2016 Michal Simek <michal.simek(a)amd.com> * Copyright (C) 2015 Nathan Rossi <nathan(a)nathanrossi.com> * * The following Boot Header format/structures and values are defined in the diff --git a/tools/zynqmpimage.h b/tools/zynqmpimage.h index 9d526a17cdd2..ca7489835a8f 100644 --- a/tools/zynqmpimage.h +++ b/tools/zynqmpimage.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2016 Michal Simek <michals(a)xilinx.com> + * Copyright (C) 2016 Michal Simek <michal.simek(a)amd.com> * Copyright (C) 2015 Nathan Rossi <nathan(a)nathanrossi.com> * * The following Boot Header format/structures and values are defined in the -- 2.36.1

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[PATCH] xilinx: zynq: Enable fdt apply utility for zynq
by Michal Simek 17 Jul '23

17 Jul '23

From: Raju Kumar Pothuraju <rajukumar.pothuraju(a)amd.com> Enables the FDT library (libfdt) overlay support for zynq platforms to be able to use fdt apply command. Signed-off-by: Raju Kumar Pothuraju <rajukumar.pothuraju(a)amd.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- configs/xilinx_zynq_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 474abc7f6b0b..990057734595 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -7,6 +7,7 @@ CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_OFFSET=0xE00000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL_STACK=0xfffffe00 CONFIG_SPL=y -- 2.36.1

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