July 2023 - U-Boot

Re: [PATCH v2 1/1] acpi: Add missing RISC-V acpi_table header
by Rick Chen 26 Jul '23

26 Jul '23

> From: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> > Sent: Wednesday, July 26, 2023 2:05 PM > To: Rick Jian-Zhi Chen(陳建志) <rick(a)andestech.com> > Cc: Leo Yu-Chi Liang(梁育齊) <ycliang(a)andestech.com>; u-boot(a)lists.denx.de; Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> > Subject: [PATCH v2 1/1] acpi: Add missing RISC-V acpi_table header > > The pci_mmc.c driver can generate ACPI info and therefore includes asm/acpi_table.h. This file does not exist for the RISC-V architecture and thus code compilation fails when using this driver on RISC-V > > Create an empty include file. > > Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> > --- > v2: > Add include skeleton. > --- > arch/riscv/include/asm/acpi_table.h | 11 +++++++++++ > 1 file changed, 11 insertions(+) Reviewed-by: Rick Chen <rick(a)andestech.com>

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[PATCH v2 1/1] acpi: Add missing RISC-V acpi_table header
by Heinrich Schuchardt 26 Jul '23

26 Jul '23

The pci_mmc.c driver can generate ACPI info and therefore includes asm/acpi_table.h. This file does not exist for the RISC-V architecture and thus code compilation fails when using this driver on RISC-V Create an empty include file. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- v2: Add include skeleton. --- arch/riscv/include/asm/acpi_table.h | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 arch/riscv/include/asm/acpi_table.h diff --git a/arch/riscv/include/asm/acpi_table.h b/arch/riscv/include/asm/acpi_table.h new file mode 100644 index 0000000000..cd851998b2 --- /dev/null +++ b/arch/riscv/include/asm/acpi_table.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __ASM_ACPI_TABLE_H__ +#define __ASM_ACPI_TABLE_H__ + +/* + * This file is needed by some drivers. + * We will fill it when adding ACPI support for RISC-V. + */ + +#endif /* __ASM_ACPI_TABLE_H__ */ -- 2.40.1

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Re: [PATCH v5 5/6] mips: ls1c300: add watchdog support
by Stefan Roese 26 Jul '23

26 Jul '23

On 7/25/23 18:46, Du Huanpeng wrote: > - watchdog driver for ls1c300 with devicetree support > > Signed-off-by: Du Huanpeng <dhu(a)hodcarrier.org> Reviewed-by: Stefan Roese <sr(a)denx.de> Thanks, Stefan > --- > drivers/watchdog/Kconfig | 8 +++ > drivers/watchdog/Makefile | 1 + > drivers/watchdog/lsmips_wdt.c | 127 ++++++++++++++++++++++++++++++++++ > 3 files changed, 136 insertions(+) > create mode 100644 drivers/watchdog/lsmips_wdt.c > > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig > index 646663528a..f60011e5b3 100644 > --- a/drivers/watchdog/Kconfig > +++ b/drivers/watchdog/Kconfig > @@ -171,6 +171,14 @@ config WDT_GPIO > doc/device-tree-bindings/watchdog/gpio-wdt.txt for > information on how to describe the watchdog in device tree. > > +config WDT_LSMIPS > + bool "Loongson MIPS watchdog timer support" > + depends on WDT > + help > + Select this to enable watchdog timer for Loongson SoCs. > + The watchdog timer is stopped when initialized. > + It performs full SoC reset. > + > config WDT_MAX6370 > bool "MAX6370 watchdog timer support" > depends on WDT > diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile > index fd5d9c7376..8afd61a4fc 100644 > --- a/drivers/watchdog/Makefile > +++ b/drivers/watchdog/Makefile > @@ -30,6 +30,7 @@ obj-$(CONFIG_WDT_ORION) += orion_wdt.o > obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o > obj-$(CONFIG_WDT_FTWDT010) += ftwdt010_wdt.o > obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o > +obj-$(CONFIG_WDT_LSMIPS) += lsmips_wdt.o > obj-$(CONFIG_WDT_MAX6370) += max6370_wdt.o > obj-$(CONFIG_WDT_MESON_GXBB) += meson_gxbb_wdt.o > obj-$(CONFIG_WDT_MPC8xxx) += mpc8xxx_wdt.o > diff --git a/drivers/watchdog/lsmips_wdt.c b/drivers/watchdog/lsmips_wdt.c > new file mode 100644 > index 0000000000..421a5029c9 > --- /dev/null > +++ b/drivers/watchdog/lsmips_wdt.c > @@ -0,0 +1,127 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Watchdog driver for MediaTek SoCs > + * > + * Copyright (C) 2018 MediaTek Inc. > + * Author: Ryder Lee <ryder.lee(a)mediatek.com> > + * > + * based on: drivers/watchdog/mtk_wdt.c > + * Copyright (C) 2020-2023 Du Huanpeng <dhu(a)hodcarrier.org> > + */ > + > +#include <common.h> > +#include <dm.h> > +#include <hang.h> > +#include <wdt.h> > +#include <asm/io.h> > +#include <clk.h> > + > + > +struct lsmips_wdt_priv { > + void __iomem *base; > +#define WDT_EN 0 > +#define WDT_TIMER 4 > +#define WDT_SET 8 > + ulong clock; > + unsigned long timeout; > +}; > + > +static int lsmips_wdt_reset(struct udevice *dev) > +{ > + struct lsmips_wdt_priv *priv = dev_get_priv(dev); > + > + writel(priv->timeout, priv->base + WDT_TIMER); > + writel(1, priv->base + WDT_SET); > + > + return 0; > +} > + > +static int lsmips_wdt_stop(struct udevice *dev) > +{ > + struct lsmips_wdt_priv *priv = dev_get_priv(dev); > + > + writel(0, priv->base + WDT_EN); > + return 0; > +} > + > +static int lsmips_wdt_expire_now(struct udevice *dev, ulong flags) > +{ > + struct lsmips_wdt_priv *priv = dev_get_priv(dev); > + > + writel(1, priv->base + WDT_EN); > + writel(1, priv->base + WDT_TIMER); > + writel(1, priv->base + WDT_SET); > + > + hang(); > + return 0; > +} > + > +static int lsmips_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) > +{ > + struct lsmips_wdt_priv *priv = dev_get_priv(dev); > + unsigned int timeout; > + > + timeout = U32_MAX / (priv->clock / 1000UL); > + > + if (timeout < timeout_ms) > + timeout = U32_MAX; > + else > + timeout = timeout_ms * (priv->clock / MSEC_PER_SEC); > + > + debug("WDT: reload = %08x\n", timeout); > + > + writel(1, priv->base + WDT_EN); > + writel(timeout, priv->base + WDT_TIMER); > + writel(1, priv->base + WDT_SET); > + > + priv->timeout = timeout; > + > + return 0; > +} > + > +static int lsmips_wdt_probe(struct udevice *dev) > +{ > + struct lsmips_wdt_priv *priv = dev_get_priv(dev); > + struct clk cl; > + ulong clock; > + > + priv->base = dev_remap_addr(dev); > + if (!priv->base) > + return -ENOENT; > + > + if (clk_get_by_index(dev, 0, &cl) == 0) > + clock = clk_get_rate(&cl); > + > + debug("WDT: clock = %ld\n", clock); > + > + if (IS_ERR_VALUE(clock)) { > + dev_err(dev, "failed to get rate\n"); > + return clock; > + } > + > + priv->clock = clock; > + writel(0, priv->base + WDT_EN); > + return 0; > +} > + > +static const struct wdt_ops lsmips_wdt_ops = { > + .start = lsmips_wdt_start, > + .reset = lsmips_wdt_reset, > + .stop = lsmips_wdt_stop, > + .expire_now = lsmips_wdt_expire_now, > +}; > + > +static const struct udevice_id lsmips_wdt_ids[] = { > + { .compatible = "loongson,ls1c300-wdt"}, > + {} > +}; > + > +U_BOOT_DRIVER(lsmips_wdt) = { > + .name = "lsmips_wdt", > + .id = UCLASS_WDT, > + .of_match = lsmips_wdt_ids, > + .priv_auto = sizeof(struct lsmips_wdt_priv), > + .probe = lsmips_wdt_probe, > + .ops = &lsmips_wdt_ops, > + .flags = DM_FLAG_PRE_RELOC, > +}; Viele Grüße, Stefan Roese -- DENX Software Engineering GmbH, Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr(a)denx.de

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[PATCH] doc: ti: Clarify required file names for K3 platforms
by Tom Rini 26 Jul '23

26 Jul '23

Now that we are using binman in all cases on these platforms, reword things to be clearer that for filesystem booting we need to use a specific name for each component. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- Cc: Neha Malcom Francis <n-francis(a)ti.com> Cc: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- doc/board/ti/am62x_sk.rst | 3 ++- doc/board/ti/am65x_evm.rst | 3 ++- doc/board/ti/j7200_evm.rst | 3 ++- doc/board/ti/j721e_evm.rst | 4 +++- 4 files changed, 9 insertions(+), 4 deletions(-) diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst index 3a122b075641..0721ee30749a 100644 --- a/doc/board/ti/am62x_sk.rst +++ b/doc/board/ti/am62x_sk.rst @@ -169,7 +169,8 @@ Build procedure: Target Images -------------- -Copy the below images to an SD card and boot: +In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC +variant (GP, HS-FS, HS-SE) requires a different source for these files. - GP diff --git a/doc/board/ti/am65x_evm.rst b/doc/board/ti/am65x_evm.rst index 300cd3e9b960..82bae7c633ab 100644 --- a/doc/board/ti/am65x_evm.rst +++ b/doc/board/ti/am65x_evm.rst @@ -170,7 +170,8 @@ Build procedure: Target Images -------------- -Copy the below images to an SD card and boot: +In order to boot we need tiboot3.bin, sysfw.itb, tispl.bin and u-boot.img. +Each SoC variant (GP and HS) requires a different source for these files. - GP diff --git a/doc/board/ti/j7200_evm.rst b/doc/board/ti/j7200_evm.rst index 5e3d75059ca5..d4af3f435349 100644 --- a/doc/board/ti/j7200_evm.rst +++ b/doc/board/ti/j7200_evm.rst @@ -172,7 +172,8 @@ Build procedure: Target Images -------------- -Copy the below images to an SD card and boot: +In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC +variant (GP, HS-FS, HS-SE) requires a different source for these files. - GP diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst index 46244197f346..a93160b77482 100644 --- a/doc/board/ti/j721e_evm.rst +++ b/doc/board/ti/j721e_evm.rst @@ -183,7 +183,9 @@ Build procedure: Target Images -------------- -Copy the below images to an SD card and boot: +In order to boot we need tiboot3.bin, sysfw.itb, tispl.bin and u-boot.img. +Each SoC variant (GP, HS-FS and HS-SE) requires a different source for these +files. - GP -- 2.34.1

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[PATCH 1/1] acpi: Add missing RISC-V acpi_table header
by Heinrich Schuchardt 26 Jul '23

26 Jul '23

The pci_mmc.c driver can generate ACPI info and therefore includes asm/acpi_table.h. This file does not exist for the RISC-V architecture and thus code compilation fails when using this driver on RISC-V Create an empty include file. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- arch/riscv/include/asm/acpi_table.h | 0 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 arch/riscv/include/asm/acpi_table.h diff --git a/arch/riscv/include/asm/acpi_table.h b/arch/riscv/include/asm/acpi_table.h new file mode 100644 index 0000000000..e69de29bb2 -- 2.40.1

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Re: [PATCH] configs: rockchip: drop useless DEBUG_UART_SKIP_INIT
by Kever Yang 26 Jul '23

26 Jul '23

On 2023/7/17 00:53, Pegorer Massimo wrote: > DEBUG_UART_SKIP_INIT feature is implemented only by s5p (DEBUG_UART_S5P) > and pl01x (DEBUG_UART_PL010 or DEBUG_UART_PL011) serial drivers, but all > ARCH_ROCKCHIP configs rely on default DEBUG_UART_NS16550. The ns16550 > serial driver does not depends on DEBUG_UART_SKIP_INIT, so drop it from > rockchip configs. > > Signed-off-by: Massimo Pegorer <massimo.pegorer(a)vimar.com> Reviewed-by: Kever Yang <kever.yang(a)rock-chips.com> Thanks, - Kever > --- > > I have tested this building all of next configs, and the resulting images > do not depend on DEBUG_UART_SKIP_INIT (i.e. they are the same with or > without DEBUG_UART_SKIP_INIT), as expected. > > IMO, DEBUG_UART_SKIP_INIT name and its description seem a little bit > misleading, as suggesting this feature provides skipping debug uart init > at all, while instead its related just to skip init of serial driver used > for debug uart. BTW maybe depends on DEBUG_UART_PL010 || DEBUG_UART_PL011 > || DEBUG_UART_S5P can be added to DEBUG_UART_SKIP_INIT. > > configs/evb-px30_defconfig | 1 - > configs/evb-px5_defconfig | 1 - > configs/evb-rk3308_defconfig | 1 - > configs/evb-rk3328_defconfig | 1 - > configs/firefly-px30_defconfig | 1 - > configs/geekbox_defconfig | 1 - > configs/lion-rk3368_defconfig | 1 - > configs/odroid-go2_defconfig | 1 - > configs/px30-core-ctouch2-of10-px30_defconfig | 1 - > configs/px30-core-ctouch2-px30_defconfig | 1 - > configs/px30-core-edimm2.2-px30_defconfig | 1 - > configs/ringneck-px30_defconfig | 1 - > configs/roc-cc-rk3308_defconfig | 1 - > configs/rock-pi-e-rk3328_defconfig | 1 - > configs/rock-pi-s-rk3308_defconfig | 1 - > configs/sheep-rk3368_defconfig | 1 - > 16 files changed, 16 deletions(-) > > diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig > index 4ac161683c..d75329d385 100644 > --- a/configs/evb-px30_defconfig > +++ b/configs/evb-px30_defconfig > @@ -100,7 +100,6 @@ CONFIG_DM_RNG=y > CONFIG_RNG_ROCKCHIP=y > # CONFIG_SPECIFY_CONSOLE_INDEX is not set > CONFIG_DEBUG_UART_SHIFT=2 > -CONFIG_DEBUG_UART_SKIP_INIT=y > CONFIG_SYS_NS16550_MEM32=y > CONFIG_SOUND=y > CONFIG_SYSRESET=y > diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig > index 29f7516e75..5f32c92674 100644 > --- a/configs/evb-px5_defconfig > +++ b/configs/evb-px5_defconfig > @@ -76,7 +76,6 @@ CONFIG_RAM=y > CONFIG_SPL_RAM=y > CONFIG_TPL_RAM=y > CONFIG_DEBUG_UART_SHIFT=2 > -CONFIG_DEBUG_UART_SKIP_INIT=y > CONFIG_SYS_NS16550_MEM32=y > CONFIG_SYSRESET=y > CONFIG_PANIC_HANG=y > diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig > index 6950b5ba06..a13a809c1e 100644 > --- a/configs/evb-rk3308_defconfig > +++ b/configs/evb-rk3308_defconfig > @@ -73,7 +73,6 @@ CONFIG_PWM_ROCKCHIP=y > CONFIG_RAM=y > CONFIG_BAUDRATE=1500000 > CONFIG_DEBUG_UART_SHIFT=2 > -CONFIG_DEBUG_UART_SKIP_INIT=y > CONFIG_SYS_NS16550_MEM32=y > CONFIG_SYSRESET=y > CONFIG_USB=y > diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig > index 580ee502dc..9bfb8f1df2 100644 > --- a/configs/evb-rk3328_defconfig > +++ b/configs/evb-rk3328_defconfig > @@ -87,7 +87,6 @@ CONFIG_TPL_RAM=y > CONFIG_BAUDRATE=1500000 > CONFIG_DEBUG_UART_SHIFT=2 > CONFIG_DEBUG_UART_ANNOUNCE=y > -CONFIG_DEBUG_UART_SKIP_INIT=y > CONFIG_SYS_NS16550_MEM32=y > CONFIG_SYSRESET=y > # CONFIG_TPL_SYSRESET is not set > diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig > index 47c924c3df..11a3baa7a3 100644 > --- a/configs/firefly-px30_defconfig > +++ b/configs/firefly-px30_defconfig > @@ -99,7 +99,6 @@ CONFIG_TPL_RAM=y > CONFIG_ROCKCHIP_SDRAM_COMMON=y > # CONFIG_SPECIFY_CONSOLE_INDEX is not set > CONFIG_DEBUG_UART_SHIFT=2 > -CONFIG_DEBUG_UART_SKIP_INIT=y > CONFIG_SYS_NS16550_MEM32=y > CONFIG_SOUND=y > CONFIG_SYSRESET=y > diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig > index fdd01b6494..8f4be79831 100644 > --- a/configs/geekbox_defconfig > +++ b/configs/geekbox_defconfig > @@ -26,7 +26,6 @@ CONFIG_PINCTRL=y > CONFIG_RAM=y > CONFIG_DEBUG_UART_SHIFT=2 > CONFIG_DEBUG_UART_ANNOUNCE=y > -CONFIG_DEBUG_UART_SKIP_INIT=y > CONFIG_SYS_NS16550_MEM32=y > CONFIG_SYSRESET=y > CONFIG_ERRNO_STR=y > diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig > index 2a180609b2..7c55b3be0d 100644 > --- a/configs/lion-rk3368_defconfig > +++ b/configs/lion-rk3368_defconfig > @@ -95,7 +95,6 @@ CONFIG_SPL_RAM=y > CONFIG_TPL_RAM=y > CONFIG_DEBUG_UART_SHIFT=2 > CONFIG_DEBUG_UART_ANNOUNCE=y > -CONFIG_DEBUG_UART_SKIP_INIT=y > CONFIG_SYS_NS16550_MEM32=y > CONFIG_ROCKCHIP_SPI=y > CONFIG_SYSINFO=y > diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig > index 459ae3d59c..0a20a3011c 100644 > --- a/configs/odroid-go2_defconfig > +++ b/configs/odroid-go2_defconfig > @@ -103,7 +103,6 @@ CONFIG_TPL_RAM=y > CONFIG_ROCKCHIP_SDRAM_COMMON=y > # CONFIG_SPECIFY_CONSOLE_INDEX is not set > CONFIG_DEBUG_UART_SHIFT=2 > -CONFIG_DEBUG_UART_SKIP_INIT=y > CONFIG_SYS_NS16550_MEM32=y > CONFIG_SOUND=y > CONFIG_SYSRESET=y > diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig > index abe6cfbd57..d96fd14b36 100644 > --- a/configs/px30-core-ctouch2-of10-px30_defconfig > +++ b/configs/px30-core-ctouch2-of10-px30_defconfig > @@ -99,7 +99,6 @@ CONFIG_DM_RNG=y > CONFIG_RNG_ROCKCHIP=y > # CONFIG_SPECIFY_CONSOLE_INDEX is not set > CONFIG_DEBUG_UART_SHIFT=2 > -CONFIG_DEBUG_UART_SKIP_INIT=y > CONFIG_SYS_NS16550_MEM32=y > CONFIG_SOUND=y > CONFIG_SYSRESET=y > diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig > index e839dcb5f6..ac2af6d8cb 100644 > --- a/configs/px30-core-ctouch2-px30_defconfig > +++ b/configs/px30-core-ctouch2-px30_defconfig > @@ -99,7 +99,6 @@ CONFIG_DM_RNG=y > CONFIG_RNG_ROCKCHIP=y > # CONFIG_SPECIFY_CONSOLE_INDEX is not set > CONFIG_DEBUG_UART_SHIFT=2 > -CONFIG_DEBUG_UART_SKIP_INIT=y > CONFIG_SYS_NS16550_MEM32=y > CONFIG_SOUND=y > CONFIG_SYSRESET=y > diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig > index 92540e73be..a49bb4072d 100644 > --- a/configs/px30-core-edimm2.2-px30_defconfig > +++ b/configs/px30-core-edimm2.2-px30_defconfig > @@ -99,7 +99,6 @@ CONFIG_DM_RNG=y > CONFIG_RNG_ROCKCHIP=y > # CONFIG_SPECIFY_CONSOLE_INDEX is not set > CONFIG_DEBUG_UART_SHIFT=2 > -CONFIG_DEBUG_UART_SKIP_INIT=y > CONFIG_SYS_NS16550_MEM32=y > CONFIG_SOUND=y > CONFIG_SYSRESET=y > diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig > index e9234efc2a..cdec0c52e6 100644 > --- a/configs/ringneck-px30_defconfig > +++ b/configs/ringneck-px30_defconfig > @@ -111,7 +111,6 @@ CONFIG_DM_RNG=y > CONFIG_RNG_ROCKCHIP=y > # CONFIG_SPECIFY_CONSOLE_INDEX is not set > CONFIG_DEBUG_UART_SHIFT=2 > -CONFIG_DEBUG_UART_SKIP_INIT=y > CONFIG_SYS_NS16550_MEM32=y > CONFIG_SOUND=y > CONFIG_SYSRESET=y > diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig > index 8eafd52a6b..9a789b212f 100644 > --- a/configs/roc-cc-rk3308_defconfig > +++ b/configs/roc-cc-rk3308_defconfig > @@ -73,7 +73,6 @@ CONFIG_PWM_ROCKCHIP=y > CONFIG_RAM=y > CONFIG_BAUDRATE=1500000 > CONFIG_DEBUG_UART_SHIFT=2 > -CONFIG_DEBUG_UART_SKIP_INIT=y > CONFIG_SYS_NS16550_MEM32=y > CONFIG_SYSRESET=y > CONFIG_USB=y > diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig > index 9c67d0c5fe..68357fed07 100644 > --- a/configs/rock-pi-e-rk3328_defconfig > +++ b/configs/rock-pi-e-rk3328_defconfig > @@ -95,7 +95,6 @@ CONFIG_TPL_RAM=y > CONFIG_BAUDRATE=1500000 > CONFIG_DEBUG_UART_SHIFT=2 > CONFIG_DEBUG_UART_ANNOUNCE=y > -CONFIG_DEBUG_UART_SKIP_INIT=y > CONFIG_SYS_NS16550_MEM32=y > CONFIG_SYSINFO=y > CONFIG_SYSINFO_SMBIOS=y > diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig > index d306b58b8e..cc3274a98b 100644 > --- a/configs/rock-pi-s-rk3308_defconfig > +++ b/configs/rock-pi-s-rk3308_defconfig > @@ -74,7 +74,6 @@ CONFIG_PWM_ROCKCHIP=y > CONFIG_RAM=y > CONFIG_BAUDRATE=1500000 > CONFIG_DEBUG_UART_SHIFT=2 > -CONFIG_DEBUG_UART_SKIP_INIT=y > CONFIG_SYS_NS16550_MEM32=y > CONFIG_SYSRESET=y > CONFIG_USB=y > diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig > index 044e1060a5..a591b2741d 100644 > --- a/configs/sheep-rk3368_defconfig > +++ b/configs/sheep-rk3368_defconfig > @@ -28,7 +28,6 @@ CONFIG_PINCTRL=y > CONFIG_RAM=y > CONFIG_DEBUG_UART_SHIFT=2 > CONFIG_DEBUG_UART_ANNOUNCE=y > -CONFIG_DEBUG_UART_SKIP_INIT=y > CONFIG_SYS_NS16550_MEM32=y > CONFIG_SYSRESET=y > CONFIG_ERRNO_STR=y

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[PATCH v1 0/2] Add support for Radxa ROCK 4SE
by Christopher Obbard 26 Jul '23

26 Jul '23

Add support for the RK3399T-based Radxa ROCK 4SE board. This board offers similar peripherals and form-factor to the ROCK Pi 4B but uses the cost-optimised RK3399T processor (which has different a OPP table but otherwise minimal changes) and some other minor hardware changes between the Rock Pi 4B (described in the devicetree). The first patch syncs the RK3399-based ROCK Pi 4 boards from Linux, moving the RK3399 OPP table from the generic Radxa ROCK Pi 4 dtsi into board-specific devicetree files, in preparation for the ROCK 4SE devicetree file. The second patch adds support for the Radxa ROCK 4SE. Christopher Obbard (2): arm: rockchip: sync ROCK Pi 4 SoCs from Linux arm: rockchip: Add Radxa ROCK 4SE arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-rock-4c-plus.dts | 3 +- arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 6 ++ arch/arm/dts/rk3399-rock-4se.dts | 65 +++++++++++++++ arch/arm/dts/rk3399-rock-pi-4.dtsi | 5 +- arch/arm/dts/rk3399-rock-pi-4a.dts | 1 + arch/arm/dts/rk3399-rock-pi-4c.dts | 1 + board/rockchip/evb_rk3399/MAINTAINERS | 6 ++ configs/rock-4se-rk3399_defconfig | 100 +++++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 2 +- 10 files changed, 184 insertions(+), 6 deletions(-) create mode 100644 arch/arm/dts/rk3399-rock-4se-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rock-4se.dts create mode 100644 configs/rock-4se-rk3399_defconfig -- 2.40.1

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[PATCH] rockchip: px30: Define variables for compressed image support
by Paul Kocialkowski 26 Jul '23

26 Jul '23

The standard boot path expects the kernel_comp_addr_r and kernel_comp_size variables for booting compressed kernel images. Define them using the previous kernel_addr_c value (likely initially meant for this purpose) and usual size. This was tested on the PX30 EVB to successfully boot compressed Linux kernel images. Signed-off-by: Paul Kocialkowski <paul.kocialkowski(a)bootlin.com> --- include/configs/px30_common.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 6fbd2679f099..13ed9011764b 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -21,8 +21,9 @@ "pxefile_addr_r=0x00600000\0" \ "fdt_addr_r=0x08300000\0" \ "kernel_addr_r=0x00280000\0" \ - "kernel_addr_c=0x03e80000\0" \ - "ramdisk_addr_r=0x0a200000\0" + "ramdisk_addr_r=0x0a200000\0" \ + "kernel_comp_addr_r=0x03e80000\0" \ + "kernel_comp_size=0x2000000\0" #define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ -- 2.41.0

2 1

[PATCH v2] board: rockchip: Add Radxa E25 Carrier Board
by Jonas Karlman 26 Jul '23

26 Jul '23

Radxa E25 is a network application carrier board for the Radxa CM3I SoM with a RK3568 SoC. It features dual 2.5G ethernet, mini PCIe, M.2 B Key, USB3, eMMC, SD, nano SIM card slot and a 26-pin GPIO header. Features tested on a Radxa E25 v1.4: - SD-card boot - eMMC boot - USB host - PCIe/Ethernet adapters is detected - SATA Device tree is imported from linux v6.4. Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- Changes in v2: - Remove the unneeded always-on/boot-on prop of vcc3v3_pi6c_05 - Drop PCI_INIT_R=y and add MMC_HS200_SUPPORT=y to speed up boot - Enable sata1 node and set correct regulator to combphy1 node, can be dropped in a future DT sync once linux patch [1] lands This patch depends on the series "board: rockchip: Add Pine64 Quartz64 and SOQuartz boards" [2] and all its depends. A copy of this patch and all its depends can be found at [3]. [1] https://lore.kernel.org/linux-rockchip/20230724145213.3833099-1-jonas@kwibo… [2] https://patchwork.ozlabs.org/project/uboot/list/?series=365266 [3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3568-radxa-e25-v2 arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3568-radxa-cm3i.dtsi | 415 ++++++++++++++++++++++ arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 57 +++ arch/arm/dts/rk3568-radxa-e25.dts | 228 ++++++++++++ board/rockchip/evb_rk3568/MAINTAINERS | 8 + configs/radxa-e25-rk3568_defconfig | 94 +++++ doc/board/rockchip/rockchip.rst | 1 + 7 files changed, 804 insertions(+) create mode 100644 arch/arm/dts/rk3568-radxa-cm3i.dtsi create mode 100644 arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-radxa-e25.dts create mode 100644 configs/radxa-e25-rk3568_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index dabbf116914c..f973f42169cc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -175,6 +175,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-soquartz-model-a.dtb \ rk3568-evb.dtb \ rk3568-odroid-m1.dtb \ + rk3568-radxa-e25.dtb \ rk3568-rock-3a.dtb dtb-$(CONFIG_ROCKCHIP_RK3588) += \ diff --git a/arch/arm/dts/rk3568-radxa-cm3i.dtsi b/arch/arm/dts/rk3568-radxa-cm3i.dtsi new file mode 100644 index 000000000000..c50fbdd48680 --- /dev/null +++ b/arch/arm/dts/rk3568-radxa-cm3i.dtsi @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3568.dtsi" + +/ { + compatible = "radxa,cm3i", "rockchip,rk3568"; + + aliases { + mmc0 = &sdhci; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_user: led-0 { + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_user_en>; + }; + }; + + pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v_input>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_input>; + }; + + /* labeled +5v_input in schematic */ + vcc5v_input: vcc5v-input-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v_input"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&display_subsystem { + status = "disabled"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v_input>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&pinctrl { + leds { + led_user_en: led_user_en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; +}; diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi new file mode 100644 index 000000000000..29f56d829a46 --- /dev/null +++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&combphy1 { + phy-supply = <&vcc3v3_pcie30x1>; +}; + +&pcie2x1 { + pinctrl-0 = <&pcie20m2_pins &pcie20_reset_h>; +}; + +&pcie3x1 { + pinctrl-0 = <&pcie30x1m0_pins &pcie30x1_reset_h>; + /* May cause a sys freeze, disable for now */ + status = "disabled"; +}; + +&pcie3x2 { + pinctrl-0 = <&pcie30x2m1_pins &pcie30x2_reset_h>; +}; + +&pinctrl { + pcie { + pcie30x1_reset_h: pcie30x1-reset-h { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sata1 { + status = "okay"; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; +}; diff --git a/arch/arm/dts/rk3568-radxa-e25.dts b/arch/arm/dts/rk3568-radxa-e25.dts new file mode 100644 index 000000000000..63c4bd873188 --- /dev/null +++ b/arch/arm/dts/rk3568-radxa-e25.dts @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3568-radxa-cm3i.dtsi" + +/ { + model = "Radxa E25 Carrier Board"; + compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568"; + + aliases { + mmc1 = &sdmmc0; + }; + + pwm-leds { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + max-brightness = <255>; + + led-red { + color = <LED_COLOR_ID_RED>; + pwms = <&pwm1 0 1000000 0>; + }; + + led-green { + color = <LED_COLOR_ID_GREEN>; + pwms = <&pwm2 0 1000000 0>; + }; + + led-blue { + color = <LED_COLOR_ID_BLUE>; + pwms = <&pwm12 0 1000000 0>; + }; + }; + }; + + vbus_typec: vbus-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus_typec_en>; + regulator-name = "vbus_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_minipcie: vcc3v3-minipcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_enable_h>; + regulator-name = "vcc3v3_minipcie"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_ngff: vcc3v3-ngff-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ngffpcie_enable_h>; + regulator-name = "vcc3v3_ngff"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* actually fed by vcc5v0_sys, dependent + * on pi6c clock generator + */ + vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1_enable_h>; + regulator-name = "vcc3v3_pcie30x1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_pi6c_05>; + }; + + vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pi6c_05>; + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1m0_pins>; + reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30x1>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x2_reset_h>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pi6c_05>; + status = "okay"; +}; + +&pinctrl { + pcie { + pcie20_reset_h: pcie20-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x1_enable_h: pcie30x1-enable-h { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x2_reset_h: pcie30x2-reset-h { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_enable_h: pcie-enable-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + minipcie_enable_h: minipcie-enable-h { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + ngffpcie_enable_h: ngffpcie-enable-h { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vbus_typec_en: vbus_typec_en { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm12 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm12m1_pins>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + /* Also used in pcie30x1_clkreqnm0 */ + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vbus_typec>; + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc3v3_ngff>; + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index 6b2e7c7575d3..e5a79f8b55d5 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -12,6 +12,14 @@ M: Jagan Teki <jagan(a)amarulasolutions.com> S: Maintained F: configs/radxa-cm3-io-rk3566_defconfig +RADXA-E25 +M: Jonas Karlman <jonas(a)kwiboo.se> +S: Maintained +F: configs/radxa-e25-rk3568_defconfig +F: arch/arm/dts/rk3568-radxa-cm3i.dtsi +F: arch/arm/dts/rk3568-radxa-e25.dts +F: arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi + ROCK-3A M: Akash Gajjar <gajjar04akash(a)gmail.com> S: Maintained diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig new file mode 100644 index 000000000000..a905100a794d --- /dev/null +++ b/configs/radxa-e25-rk3568_defconfig @@ -0,0 +1,94 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-radxa-e25.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 3cd5de55120b..68c7202a2df7 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -101,6 +101,7 @@ List of mainline supported Rockchip boards: - Pine64 SOQuartz on Blade (soquartz-blade-rk3566_defconfig) - Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566_defconfig) - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig) + - Radxa E25 Carrier Board (radxa-e25-rk3568_defconfig) * rk3588 - Rockchip EVB (evb-rk3588) -- 2.41.0

2 2

[PATCH] board: rockchip: Add Radxa E25 Carrier Board
by Jonas Karlman 26 Jul '23

26 Jul '23

Radxa E25 is a network application carrier board for the Radxa CM3I SoM with a RK3568 SoC. It features dual 2.5G ethernet, mini PCIe, M.2 B Key, USB3, eMMC, SD and nano sim card slot. Features tested on a Radxa E25 v1.4: - SD-card boot - eMMC boot - USB host - PCIe/Ethernet adapters is detected Device tree is imported from linux v6.4. Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- This patch depends on the series "board: rockchip: Add Pine64 Quartz64 and SOQuartz boards" [1] [1] https://patchwork.ozlabs.org/project/uboot/list/?series=365266 Boot log with ROCKCHIP_TPL=rk3568_ddr_1560MHz_v1.17.bin and BL31=rk3568_bl31_v1.43.elf: U-Boot SPL 2023.07 (Jul 23 2023 - 22:03:27 +0000) Trying to boot from MMC2 ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK ## Checking hash(es) for Image fdt-1 ... sha256+ OK ## Checking hash(es) for Image atf-2 ... sha256+ OK ## Checking hash(es) for Image atf-3 ... sha256+ OK ## Checking hash(es) for Image atf-4 ... sha256+ OK ## Checking hash(es) for Image atf-5 ... sha256+ OK ## Checking hash(es) for Image atf-6 ... sha256+ OK U-Boot 2023.07 (Jul 23 2023 - 22:03:27 +0000) Model: Radxa E25 Carrier Board DRAM: 2 GiB PMIC: RK8090 (on=0x40, off=0x00) Core: 316 devices, 27 uclasses, devicetree: separate MMC: mmc@fe2b0000: 1, mmc@fe310000: 0 Loading Environment from nowhere... OK In: serial@fe660000 Out: serial@fe660000 Err: serial@fe660000 Model: Radxa E25 Carrier Board Net: eth0: eth_rtl8169, eth1: eth_rtl8169 Hit any key to stop autoboot: 0 => pci BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x1d87 0x3566 Bridge device 0x04 01.00.00 0x10ec 0x8125 Network controller 0x00 02.00.00 0x1d87 0x3566 Bridge device 0x04 03.00.00 0x10ec 0x8125 Network controller 0x00 => arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3568-radxa-cm3i.dtsi | 415 ++++++++++++++++++++++ arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 56 +++ arch/arm/dts/rk3568-radxa-e25.dts | 228 ++++++++++++ board/rockchip/evb_rk3568/MAINTAINERS | 8 + configs/radxa-e25-rk3568_defconfig | 94 +++++ doc/board/rockchip/rockchip.rst | 1 + 7 files changed, 803 insertions(+) create mode 100644 arch/arm/dts/rk3568-radxa-cm3i.dtsi create mode 100644 arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-radxa-e25.dts create mode 100644 configs/radxa-e25-rk3568_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index dabbf116914c..f973f42169cc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -175,6 +175,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-soquartz-model-a.dtb \ rk3568-evb.dtb \ rk3568-odroid-m1.dtb \ + rk3568-radxa-e25.dtb \ rk3568-rock-3a.dtb dtb-$(CONFIG_ROCKCHIP_RK3588) += \ diff --git a/arch/arm/dts/rk3568-radxa-cm3i.dtsi b/arch/arm/dts/rk3568-radxa-cm3i.dtsi new file mode 100644 index 000000000000..c50fbdd48680 --- /dev/null +++ b/arch/arm/dts/rk3568-radxa-cm3i.dtsi @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3568.dtsi" + +/ { + compatible = "radxa,cm3i", "rockchip,rk3568"; + + aliases { + mmc0 = &sdhci; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_user: led-0 { + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_user_en>; + }; + }; + + pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v_input>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_input>; + }; + + /* labeled +5v_input in schematic */ + vcc5v_input: vcc5v-input-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v_input"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&display_subsystem { + status = "disabled"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v_input>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&pinctrl { + leds { + led_user_en: led_user_en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; +}; diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi new file mode 100644 index 000000000000..305dee67ed37 --- /dev/null +++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&pcie2x1 { + /delete-property/ vpcie3v3-supply; + pinctrl-0 = <&pcie20m2_pins &pcie20_reset_h>; +}; + +&pcie3x1 { + pinctrl-0 = <&pcie30x1m0_pins &pcie30x1_reset_h>; + /* May cause a sys freeze, disable for now */ + status = "disabled"; +}; + +&pcie3x2 { + /delete-property/ vpcie3v3-supply; + pinctrl-0 = <&pcie30x2m1_pins &pcie30x2_reset_h>; +}; + +&pinctrl { + pcie { + pcie30x1_reset_h: pcie30x1-reset-h { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; +}; + +&vcc3v3_pi6c_05 { + regulator-always-on; + regulator-boot-on; +}; diff --git a/arch/arm/dts/rk3568-radxa-e25.dts b/arch/arm/dts/rk3568-radxa-e25.dts new file mode 100644 index 000000000000..63c4bd873188 --- /dev/null +++ b/arch/arm/dts/rk3568-radxa-e25.dts @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3568-radxa-cm3i.dtsi" + +/ { + model = "Radxa E25 Carrier Board"; + compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568"; + + aliases { + mmc1 = &sdmmc0; + }; + + pwm-leds { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + max-brightness = <255>; + + led-red { + color = <LED_COLOR_ID_RED>; + pwms = <&pwm1 0 1000000 0>; + }; + + led-green { + color = <LED_COLOR_ID_GREEN>; + pwms = <&pwm2 0 1000000 0>; + }; + + led-blue { + color = <LED_COLOR_ID_BLUE>; + pwms = <&pwm12 0 1000000 0>; + }; + }; + }; + + vbus_typec: vbus-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus_typec_en>; + regulator-name = "vbus_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_minipcie: vcc3v3-minipcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_enable_h>; + regulator-name = "vcc3v3_minipcie"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_ngff: vcc3v3-ngff-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ngffpcie_enable_h>; + regulator-name = "vcc3v3_ngff"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* actually fed by vcc5v0_sys, dependent + * on pi6c clock generator + */ + vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1_enable_h>; + regulator-name = "vcc3v3_pcie30x1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_pi6c_05>; + }; + + vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pi6c_05>; + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1m0_pins>; + reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30x1>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x2_reset_h>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pi6c_05>; + status = "okay"; +}; + +&pinctrl { + pcie { + pcie20_reset_h: pcie20-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x1_enable_h: pcie30x1-enable-h { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x2_reset_h: pcie30x2-reset-h { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_enable_h: pcie-enable-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + minipcie_enable_h: minipcie-enable-h { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + ngffpcie_enable_h: ngffpcie-enable-h { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vbus_typec_en: vbus_typec_en { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm12 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm12m1_pins>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + /* Also used in pcie30x1_clkreqnm0 */ + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vbus_typec>; + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc3v3_ngff>; + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index 6b2e7c7575d3..e5a79f8b55d5 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -12,6 +12,14 @@ M: Jagan Teki <jagan(a)amarulasolutions.com> S: Maintained F: configs/radxa-cm3-io-rk3566_defconfig +RADXA-E25 +M: Jonas Karlman <jonas(a)kwiboo.se> +S: Maintained +F: configs/radxa-e25-rk3568_defconfig +F: arch/arm/dts/rk3568-radxa-cm3i.dtsi +F: arch/arm/dts/rk3568-radxa-e25.dts +F: arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi + ROCK-3A M: Akash Gajjar <gajjar04akash(a)gmail.com> S: Maintained diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig new file mode 100644 index 000000000000..00502326defb --- /dev/null +++ b/configs/radxa-e25-rk3568_defconfig @@ -0,0 +1,94 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-radxa-e25.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_PCI_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=115200 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 3cd5de55120b..68c7202a2df7 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -101,6 +101,7 @@ List of mainline supported Rockchip boards: - Pine64 SOQuartz on Blade (soquartz-blade-rk3566_defconfig) - Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566_defconfig) - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig) + - Radxa E25 Carrier Board (radxa-e25-rk3568_defconfig) * rk3588 - Rockchip EVB (evb-rk3588) -- 2.41.0

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