July 2023 - U-Boot

[PATCHv4 0/5] net/lwip: add lwip library for the network stack
by Maxim Uvarov 02 Aug '23

02 Aug '23

changelog: v4: - tested with tests/py/ did some minor fixes (out of tree build, variables set after downloads). - accounted review comments for documentation. - implemented dns command - corrected wget command to not use serverip variable and use just url string. v3: - use lwip commands for ping,tftp,wget,dhcp if this patch applied. Drop CONFIG_LIB_LWIP_REPLACE_<COMMAND> option. - docs: use rst variant and drop references to RFC. build: git submodule init git submodule update make I tested with qemu and ubuntu host for the server manually and with ./test/py/test -bd qemu_arm64 --build -k net. Maxim Uvarov (5): net/lwip: add lwip-external submodule net/lwip: add lwip library for the network stack net/lwip: add doc/develop/net_lwip.rst net/lwip: add dns command net/lwip: apps/http: add dns support .gitignore | 9 + .gitmodules | 3 + boot/bootmeth_pxe.c | 2 +- cmd/net.c | 89 +------- cmd/pxe.c | 2 +- doc/develop/index.rst | 1 + doc/develop/net_lwip.rst | 59 +++++ include/net.h | 8 +- lib/Kconfig | 2 + lib/Makefile | 2 + lib/lwip/Kconfig | 63 ++++++ lib/lwip/Makefile | 103 +++++++++ lib/lwip/apps/dhcp/lwip-dhcp.c | 52 +++++ lib/lwip/apps/dns/lwip-dns.c | 46 ++++ lib/lwip/apps/dns/lwip-dns.h | 3 + lib/lwip/apps/http/lwip-wget.c | 121 ++++++++++ lib/lwip/apps/ping/lwip_ping.c | 37 ++++ lib/lwip/apps/ping/lwip_ping.h | 24 ++ lib/lwip/apps/ping/ping.h | 35 +++ lib/lwip/apps/tftp/lwip-tftp.c | 124 +++++++++++ lib/lwip/cmd-lwip.c | 308 ++++++++++++++++++++++++++ lib/lwip/lwip-external | 1 + lib/lwip/lwipopts.h | 203 +++++++++++++++++ lib/lwip/port/if.c | 260 ++++++++++++++++++++++ lib/lwip/port/include/arch/cc.h | 46 ++++ lib/lwip/port/include/arch/sys_arch.h | 59 +++++ lib/lwip/port/include/limits.h | 0 lib/lwip/port/sys-arch.c | 20 ++ lib/lwip/ulwip.h | 9 + net/Kconfig | 1 + net/net.c | 24 ++ 31 files changed, 1634 insertions(+), 82 deletions(-) create mode 100644 .gitmodules create mode 100644 doc/develop/net_lwip.rst create mode 100644 lib/lwip/Kconfig create mode 100644 lib/lwip/Makefile create mode 100644 lib/lwip/apps/dhcp/lwip-dhcp.c create mode 100644 lib/lwip/apps/dns/lwip-dns.c create mode 100644 lib/lwip/apps/dns/lwip-dns.h create mode 100644 lib/lwip/apps/http/lwip-wget.c create mode 100644 lib/lwip/apps/ping/lwip_ping.c create mode 100644 lib/lwip/apps/ping/lwip_ping.h create mode 100644 lib/lwip/apps/ping/ping.h create mode 100644 lib/lwip/apps/tftp/lwip-tftp.c create mode 100644 lib/lwip/cmd-lwip.c create mode 160000 lib/lwip/lwip-external create mode 100644 lib/lwip/lwipopts.h create mode 100644 lib/lwip/port/if.c create mode 100644 lib/lwip/port/include/arch/cc.h create mode 100644 lib/lwip/port/include/arch/sys_arch.h create mode 100644 lib/lwip/port/include/limits.h create mode 100644 lib/lwip/port/sys-arch.c create mode 100644 lib/lwip/ulwip.h -- 2.30.2

5 19

[PATCH v3 1/4] cmd: bind: Add unbind command with driver filter
by Marek Vasut 02 Aug '23

02 Aug '23

Extend the driver core to perform lookup by both OF node and driver bound to the node. Use this to look up specific device instances to unbind from nodes in the unbind command. One example where this is needed is USB peripheral controller, which may have multiple gadget drivers bound to it. The unbind command has to select that specific gadget driver instance to unbind from the controller, not unbind the controller driver itself from the controller. USB ethernet gadget usage looks as follows with this change. Notice the extra 'usb_ether' addition in the 'unbind' command at the end. " bind /soc/usb-otg@49000000 usb_ether setenv ethact usb_ether setenv loadaddr 0xc2000000 setenv ipaddr 10.0.0.2 setenv serverip 10.0.0.1 setenv netmask 255.255.255.0 tftpboot 0xc2000000 10.0.0.1:test.file unbind /soc/usb-otg@49000000 usb_ether " Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Kevin Hilman <khilman(a)baylibre.com> Cc: Lukasz Majewski <lukma(a)denx.de> Cc: Miquel Raynal <miquel.raynal(a)bootlin.com> Cc: Simon Glass <sjg(a)chromium.org> --- V2: No change V3: No change --- cmd/bind.c | 10 +++++----- drivers/core/device.c | 20 +++++++++++++++----- include/dm/device.h | 17 +++++++++++++++++ 3 files changed, 37 insertions(+), 10 deletions(-) diff --git a/cmd/bind.c b/cmd/bind.c index 4d1b7885e60..3137cdf6cb5 100644 --- a/cmd/bind.c +++ b/cmd/bind.c @@ -162,7 +162,7 @@ static int bind_by_node_path(const char *path, const char *drv_name) return 0; } -static int unbind_by_node_path(const char *path) +static int unbind_by_node_path(const char *path, const char *drv_name) { struct udevice *dev; int ret; @@ -174,7 +174,7 @@ static int unbind_by_node_path(const char *path) return -EINVAL; } - ret = device_find_global_by_ofnode(ofnode, &dev); + ret = device_find_global_by_ofnode_driver(ofnode, drv_name, &dev); if (!dev || ret) { printf("Cannot find a device with path %s\n", path); @@ -214,9 +214,9 @@ static int do_bind_unbind(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_USAGE; ret = bind_by_node_path(argv[1], argv[2]); } else if (by_node && !bind) { - if (argc != 2) + if (argc != 2 && argc != 3) return CMD_RET_USAGE; - ret = unbind_by_node_path(argv[1]); + ret = unbind_by_node_path(argv[1], argv[2]); } else if (!by_node && bind) { int index = (argc > 2) ? dectoul(argv[2], NULL) : 0; @@ -251,7 +251,7 @@ U_BOOT_CMD( U_BOOT_CMD( unbind, 4, 0, do_bind_unbind, "Unbind a device from a driver", - "<node path>\n" + "<node path> [<driver>]\n" "unbind <class> <index>\n" "unbind <class> <index> <driver>\n" ); diff --git a/drivers/core/device.c b/drivers/core/device.c index 6e26b64fb81..52fceb69341 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -877,15 +877,17 @@ int device_get_child_by_of_offset(const struct udevice *parent, int node, } static struct udevice *_device_find_global_by_ofnode(struct udevice *parent, - ofnode ofnode) + ofnode ofnode, + const char *drv) { struct udevice *dev, *found; - if (ofnode_equal(dev_ofnode(parent), ofnode)) + if (ofnode_equal(dev_ofnode(parent), ofnode) && + (!drv || (drv && !strcmp(parent->driver->name, drv)))) return parent; device_foreach_child(dev, parent) { - found = _device_find_global_by_ofnode(dev, ofnode); + found = _device_find_global_by_ofnode(dev, ofnode, drv); if (found) return found; } @@ -895,7 +897,15 @@ static struct udevice *_device_find_global_by_ofnode(struct udevice *parent, int device_find_global_by_ofnode(ofnode ofnode, struct udevice **devp) { - *devp = _device_find_global_by_ofnode(gd->dm_root, ofnode); + *devp = _device_find_global_by_ofnode(gd->dm_root, ofnode, NULL); + + return *devp ? 0 : -ENOENT; +} + +int device_find_global_by_ofnode_driver(ofnode ofnode, const char *drv, + struct udevice **devp) +{ + *devp = _device_find_global_by_ofnode(gd->dm_root, ofnode, drv); return *devp ? 0 : -ENOENT; } @@ -904,7 +914,7 @@ int device_get_global_by_ofnode(ofnode ofnode, struct udevice **devp) { struct udevice *dev; - dev = _device_find_global_by_ofnode(gd->dm_root, ofnode); + dev = _device_find_global_by_ofnode(gd->dm_root, ofnode, NULL); return device_get_device_tail(dev, dev ? 0 : -ENOENT, devp); } diff --git a/include/dm/device.h b/include/dm/device.h index b86bf90609b..5f05ae0924f 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -748,6 +748,23 @@ int device_get_child_by_of_offset(const struct udevice *parent, int of_offset, int device_find_global_by_ofnode(ofnode node, struct udevice **devp); +/** + * device_find_global_by_ofnode_driver() - Get a device based on ofnode and driver + * + * Locates a device by its device tree ofnode and driver currently bound to + * it, searching globally throughout the all driver model devices. + * + * The device is NOT probed + * + * @node: Device tree ofnode to find + * @drv: Driver name bound to device + * @devp: Returns pointer to device if found, otherwise this is set to NULL + * Return: 0 if OK, -ve on error + */ + +int device_find_global_by_ofnode_driver(ofnode node, const char *drv, + struct udevice **devp); + /** * device_get_global_by_ofnode() - Get a device based on ofnode * -- 2.40.1

2 16

[PATCH 0/5] ARM: dts: at91: Improve sam9x60-curiosity
by Alexander Dahl 02 Aug '23

02 Aug '23

Hello everyone, currently I have the Microchip SAM9X60-Curiosity board on my desk and for evaluation purposes I'm trying to get it booting from NAND flash without SD card. This series contains a collection of patches I made on that journey. It's probably not the last set of patches, but I send it out now before my holidays so anyone who's interested has some time to look into it before I return to my desk in roughly two weeks. ;-) Note: while I could access the I²C EEPROM populated on that board with Linux v6.4 through nvmem and the 100 bytes content seem valid including a MAC address attributed to Microchip, I could not do so in U-Boot. That also means out of the box access to Ethernet is currently broken without valid MAC address. Note: I prepared the patches at the office, but sending them from home now. This is why I use two different mail addresses. Greets Alex Alexander Dahl (5): ARM: dts: at91: sam9x60: Better align with upstream dtsi ARM: dts: at91: sam9x60-curiosity: Fix EEPROM type ARM: dts: at91: sam9x60: Change i2c compatible ARM: dts: at91: sam9x60-curiosity: Improve alignment with upstream ARM: dts: at91: sam9x60-curiosity: Add raw NAND flash .../dts/at91-sam9x60_curiosity-u-boot.dtsi | 8 +- arch/arm/dts/at91-sam9x60_curiosity.dts | 203 +++++++++++++----- arch/arm/dts/sam9x60.dtsi | 66 +++--- arch/arm/dts/sam9x60ek.dts | 2 +- 4 files changed, 190 insertions(+), 89 deletions(-) base-commit: e1bebc16e1d9aa0ddd56c53c0b781f7186dce557 -- 2.30.2

3 13

[PATCH 0/2] Update remove method for DSS driver
by Nikhil M Jain 01 Aug '23

01 Aug '23

This patch series aims at updating the remove method for DSS video driver. Nikhil M Jain (2): drivers: video: tidss: tidss_drv: Change remove method drivers: video: tidss: tidss_drv: Use kconfig VIDEO_REMOVE to remove video drivers/video/tidss/tidss_drv.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) -- 2.34.1

3 6

[PATCH 00/18] video: bochs: Remove the x86 limitation
by Bin Meng 01 Aug '23

01 Aug '23

The Bochs VGA card emulated by QEMU does not enforce any architecture. It was first introduced on x86 and indeed the x86 IO instruction is used to access the legacy VGA IO ports, but that does not mean it has to be done like this. The first half of this series enhances the bochs video driver to remove the x86 limitation. The second half of this series enables bochs video as the output console for QEMU RISC-V, to prove that the bochs video driver can indeed work on a non-x86 architecture. To make it actually useful, enable a usb keyboard as well, otherwise we can't just type anything :-) This series is available at u-boot-x86/bochs for testing. Bin Meng (17): dm: video: Cosmetic style fix video: bochs: Drop inclusion of <asm/mtrr.h> video: bochs: Drop the useless argument of bochs_vga_write() video: bochs: Avoid using IO instructions to access VGA IO port video: bochs: Remove the x86 dependency video: kconfig: Fix wrong text for the PCI default FB size video: kconfig: Drop the superfluous dependency video: kconfig: Set default FB size for Bochs video: bochs: Set the frame buffer size per configuration riscv: qemu: Enable Bochs video support console: kconfig: Drop the redundant VIDEO dependency console: Make stdio_print_current_devices() static console: Refactor stdio_print_current_devices() a little bit console: Print out complete stdio device list riscv: qemu: Enable PRE_CONSOLE_BUFFER riscv: qemu: Remove out-of-date "riscv,kernel-start" handling riscv: qemu: Enable usb keyboard as an input device Heinrich Schuchardt (1): riscv: define a cache line size for the generic CPU arch/riscv/cpu/generic/Kconfig | 1 + board/emulation/qemu-riscv/Kconfig | 13 ++++++++ board/emulation/qemu-riscv/qemu-riscv.c | 27 +++------------ common/Kconfig | 2 +- common/console.c | 44 ++++++++++++++++--------- doc/board/emulation/qemu-riscv.rst | 10 ++++++ drivers/video/Kconfig | 15 +++++---- drivers/video/bochs.c | 12 +++---- drivers/video/bochs.h | 7 ++-- drivers/video/video-uclass.c | 6 ++-- include/configs/qemu-riscv.h | 15 +++------ include/stdio_dev.h | 2 -- 12 files changed, 84 insertions(+), 70 deletions(-) -- 2.34.1

7 57

[PATCH v4 00/12] Integrate EFI capsule tasks into u-boot's build flow
by Sughosh Ganu 01 Aug '23

01 Aug '23

This patchset aims to bring two capsule related tasks under the u-boot build flow. One is the embedding of the public key into the platform's dtb. The public key is in the form of an EFI Signature List(ESL) file and is used for capsule authentication. This is being achieved by adding the signature node containing the capsule public key in the architecture's u-boot.dtsi file. Currently, the u-boot.dtsi file has been added for the sandbox and arm architectures. The path to the ESL file is being provided through a Kconfig symbol(CONFIG_EFI_CAPSULE_ESL_FILE). Changes have also been made to the test flow so that the keys used for signing the capsule, and the ESL file, are generated prior to invoking the u-boot's build, which enables embedding the ESL file into the dtb as part of the u-boot build. The other task is related to generation of capsules. Support is being added to generate capsules by specifying the capsule parameters in a config file. Calling the mkeficapsule tool then results in generation of the corresponding capsule files. The capsules can be generated as part of u-boot build, and this is being achieved through binman, by adding a capsule entry type. The capsules can be generated either by specifying the capsule parameters in a config file, or through specifying them as properties under the capsule entry node. If using the config file, the path to the config file is to be specified through a Kconfig symbol(CONFIG_EFI_CAPSULE_CFG_FILE). Changes have also been made to the efi capsule update feature testing setup on the sandbox variants. Currently, the capsule files and the public key ESL file are generated after u-boot has been built. This logic has been changed so that the capsule input files along with the keys needed for capsule signing and authentication are generated prior to initiation of the u-boot build. The placement of all the files needed for generation of capsules, along with the generated capsule files is under the /tmp/capsules/ directory. Currently, the capsule update feature is tested on the sandbox and sandbox_flattree variants in CI. The capsule generation through config file is enabled for the sandbox variant, with the sandbox_flattree variant generating capsules through the command-line parameters. The document has been updated to reflect the above changes. Changes since V3: * New patch to support passing multiple commands to the build_from_git * Put the two ifdef statements together in arm architecture's u-boot.dtsi file. * Remove the extra blank line in the Kconfig. function to build the tool. * Add support for firmware versioning, needed after rebasing on current master. * Add test cases for covering the various capsule generation scenarios. * Add function comments in the mkeficapsule bintool. * Fix the fetch method of the mkeficapsule bintool to enable building the tool. * Add more details about the capsule parameters in the documentation as well as the code. * Fix order of module imports, and addition of blank lines in the capsule.py file. * Use SetContents in the ObtainContents method. * Move the paragraph on version support under a separate subsection. * Move the description on generating capsules through config file under the section to describe capsule generation. * Add a subsection highlighting generation of capsules through binman. * Remove whitespace in the command to generate capsule keys. * Use fstrings for format specifiers. * Rebase on top of current master to work with test configuration for version support in capsule updates. * Use fstrings for format specifiers. * Add entries for generating capsules with version parameter. * Use blob nodes instead of incbin for including the binaries in FIT image. * Enable generation of capsules with versioning support. Sughosh Ganu (12): binman: bintool: Build a tool from a list of commands nuvoton: npcm845-evb: Add a newline at the end of file capsule: authenticate: Add capsule public key in platform's dtb doc: capsule: Document the new mechanism to embed ESL file into dtb tools: mkeficapsule: Add support for parsing capsule params from config file binman: capsule: Add support for generating capsules doc: Add documentation to highlight capsule generation related updates CI: capsule: Setup the files needed for capsule update testing test: py: Setup capsule files for testing test: capsule: Remove public key embed logic from capsule update test sandbox: capsule: Add a config file for generating capsules sandbox: capsule: Generate capsule related files through binman .azure-pipelines.yml | 26 ++ .gitlab-ci.yml | 24 ++ arch/arm/dts/nuvoton-npcm845-evb.dts | 2 +- arch/arm/dts/u-boot.dtsi | 17 + arch/sandbox/dts/u-boot.dtsi | 282 ++++++++++++++ configs/sandbox_defconfig | 3 + configs/sandbox_flattree_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + doc/develop/uefi/uefi.rst | 106 +++++- lib/efi_loader/Kconfig | 10 + lib/efi_loader/Makefile | 7 + test/py/conftest.py | 89 +++++ test/py/tests/test_efi_capsule/conftest.py | 164 +------- .../test_efi_capsule/sandbox_capsule_cfg.txt | 162 ++++++++ test/py/tests/test_efi_capsule/signature.dts | 10 - .../tests/test_efi_capsule/uboot_bin_env.its | 36 -- tools/Kconfig | 16 + tools/Makefile | 1 + tools/binman/bintool.py | 19 +- tools/binman/btool/_testing.py | 3 +- tools/binman/btool/fiptool.py | 4 +- tools/binman/btool/futility.py | 4 +- tools/binman/btool/mkeficapsule.py | 158 ++++++++ tools/binman/entries.rst | 37 ++ tools/binman/etype/capsule.py | 132 +++++++ tools/binman/ftest.py | 127 +++++++ tools/binman/test/282_capsule.dts | 18 + tools/binman/test/283_capsule_signed.dts | 20 + tools/binman/test/284_capsule_conf.dts | 14 + tools/binman/test/285_capsule_missing_key.dts | 19 + .../binman/test/286_capsule_missing_index.dts | 17 + .../binman/test/287_capsule_missing_guid.dts | 17 + .../test/288_capsule_missing_payload.dts | 17 + tools/binman/test/289_capsule_missing.dts | 17 + tools/binman/test/290_capsule_version.dts | 19 + tools/binman/test/capsule_cfg.txt | 6 + tools/eficapsule.h | 115 ++++++ tools/mkeficapsule.c | 87 +++-- tools/mkeficapsule_parse.c | 352 ++++++++++++++++++ 39 files changed, 1900 insertions(+), 259 deletions(-) create mode 100644 arch/arm/dts/u-boot.dtsi create mode 100644 arch/sandbox/dts/u-boot.dtsi create mode 100644 test/py/tests/test_efi_capsule/sandbox_capsule_cfg.txt delete mode 100644 test/py/tests/test_efi_capsule/signature.dts delete mode 100644 test/py/tests/test_efi_capsule/uboot_bin_env.its create mode 100644 tools/binman/btool/mkeficapsule.py create mode 100644 tools/binman/etype/capsule.py create mode 100644 tools/binman/test/282_capsule.dts create mode 100644 tools/binman/test/283_capsule_signed.dts create mode 100644 tools/binman/test/284_capsule_conf.dts create mode 100644 tools/binman/test/285_capsule_missing_key.dts create mode 100644 tools/binman/test/286_capsule_missing_index.dts create mode 100644 tools/binman/test/287_capsule_missing_guid.dts create mode 100644 tools/binman/test/288_capsule_missing_payload.dts create mode 100644 tools/binman/test/289_capsule_missing.dts create mode 100644 tools/binman/test/290_capsule_version.dts create mode 100644 tools/binman/test/capsule_cfg.txt create mode 100644 tools/mkeficapsule_parse.c -- 2.34.1

2 35

[PATCH v3] board: rockchip: Add Radxa E25 Carrier Board
by Jonas Karlman 01 Aug '23

01 Aug '23

Radxa E25 is a network application carrier board for the Radxa CM3I SoM with a RK3568 SoC. It features dual 2.5G ethernet, mini PCIe, M.2 B Key, USB3, eMMC, SD, nano SIM card slot and a 26-pin GPIO header. Features tested on a Radxa E25 v1.4: - SD-card boot - eMMC boot - USB host - PCIe/Ethernet adapters is detected - SATA Device tree is imported from linux next-20230728. Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> Reviewed-by: Kever Yang <kever.yang(a)rock-chips.com> --- Changes in v3: - Rebased on master and "board: rockchip: Add Pine64 Quartz64 and SOQuartz boards" v2 series - Sync device tree from linux next-20230728 to include sata1, combphy1 and regulator fixes merged into linux maintainer tree since v2 - Drop u-boot.dtsi pcie pinctrl change that caused pinmux issue in linux when using EFI boot flow - Collect r-b tag Changes in v2: - Remove the unneeded always-on/boot-on prop of vcc3v3_pi6c_05 - Drop PCI_INIT_R=y and add MMC_HS200_SUPPORT=y to speed up boot - Enable sata1 node and set correct regulator to combphy1 node, can be dropped in a future DT sync once linux patch [1] lands This patch depends on the series "board: rockchip: Add Pine64 Quartz64 and SOQuartz boards" v2 [2] and all its depends. A copy of this patch and all its depends can be found at [3]. [1] https://lore.kernel.org/linux-rockchip/20230724145213.3833099-1-jonas@kwibo… [2] https://patchwork.ozlabs.org/project/uboot/list/?series=366399 [3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3568-radxa-e25-v3 arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3568-radxa-cm3i.dtsi | 415 ++++++++++++++++++++++ arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 32 ++ arch/arm/dts/rk3568-radxa-e25.dts | 236 ++++++++++++ board/rockchip/evb_rk3568/MAINTAINERS | 8 + configs/radxa-e25-rk3568_defconfig | 94 +++++ doc/board/rockchip/rockchip.rst | 1 + 7 files changed, 787 insertions(+) create mode 100644 arch/arm/dts/rk3568-radxa-cm3i.dtsi create mode 100644 arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-radxa-e25.dts create mode 100644 configs/radxa-e25-rk3568_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index bf8c568260a6..01aba388994e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -180,6 +180,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3568-nanopi-r5c.dtb \ rk3568-nanopi-r5s.dtb \ rk3568-odroid-m1.dtb \ + rk3568-radxa-e25.dtb \ rk3568-rock-3a.dtb dtb-$(CONFIG_ROCKCHIP_RK3588) += \ diff --git a/arch/arm/dts/rk3568-radxa-cm3i.dtsi b/arch/arm/dts/rk3568-radxa-cm3i.dtsi new file mode 100644 index 000000000000..c50fbdd48680 --- /dev/null +++ b/arch/arm/dts/rk3568-radxa-cm3i.dtsi @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3568.dtsi" + +/ { + compatible = "radxa,cm3i", "rockchip,rk3568"; + + aliases { + mmc0 = &sdhci; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_user: led-0 { + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_GREEN>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_user_en>; + }; + }; + + pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v_input>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_input>; + }; + + /* labeled +5v_input in schematic */ + vcc5v_input: vcc5v-input-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v_input"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&display_subsystem { + status = "disabled"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v_input>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&pinctrl { + leds { + led_user_en: led_user_en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; +}; diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi new file mode 100644 index 000000000000..572bdc5665b1 --- /dev/null +++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +/* PCIe PHY driver in U-Boot does not support bifurcation */ +&pcie3x1 { + status = "disabled"; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; +}; diff --git a/arch/arm/dts/rk3568-radxa-e25.dts b/arch/arm/dts/rk3568-radxa-e25.dts new file mode 100644 index 000000000000..72ad74c38a2b --- /dev/null +++ b/arch/arm/dts/rk3568-radxa-e25.dts @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3568-radxa-cm3i.dtsi" + +/ { + model = "Radxa E25 Carrier Board"; + compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568"; + + aliases { + mmc1 = &sdmmc0; + }; + + pwm-leds { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + max-brightness = <255>; + + led-red { + color = <LED_COLOR_ID_RED>; + pwms = <&pwm1 0 1000000 0>; + }; + + led-green { + color = <LED_COLOR_ID_GREEN>; + pwms = <&pwm2 0 1000000 0>; + }; + + led-blue { + color = <LED_COLOR_ID_BLUE>; + pwms = <&pwm12 0 1000000 0>; + }; + }; + }; + + vbus_typec: vbus-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus_typec_en>; + regulator-name = "vbus_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* actually fed by vcc5v0_sys, dependent + * on pi6c clock generator + */ + vcc3v3_minipcie: vcc3v3-minipcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_enable_h>; + regulator-name = "vcc3v3_minipcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_pi6c_05>; + }; + + vcc3v3_ngff: vcc3v3-ngff-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ngffpcie_enable_h>; + regulator-name = "vcc3v3_ngff"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1_enable_h>; + regulator-name = "vcc3v3_pcie30x1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy1 { + phy-supply = <&vcc3v3_pcie30x1>; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pi6c_05>; + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1m0_pins>; + reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x2_reset_h>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pi6c_05>; + status = "okay"; +}; + +&pinctrl { + pcie { + pcie20_reset_h: pcie20-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x1_enable_h: pcie30x1-enable-h { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x2_reset_h: pcie30x2-reset-h { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_enable_h: pcie-enable-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + minipcie_enable_h: minipcie-enable-h { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + ngffpcie_enable_h: ngffpcie-enable-h { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vbus_typec_en: vbus_typec_en { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm12 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm12m1_pins>; + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + /* Also used in pcie30x1_clkreqnm0 */ + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vbus_typec>; + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc3v3_ngff>; + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index a8ed2508a162..82a92b89fa64 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -27,6 +27,14 @@ M: Jagan Teki <jagan(a)amarulasolutions.com> S: Maintained F: configs/radxa-cm3-io-rk3566_defconfig +RADXA-E25 +M: Jonas Karlman <jonas(a)kwiboo.se> +S: Maintained +F: configs/radxa-e25-rk3568_defconfig +F: arch/arm/dts/rk3568-radxa-cm3i.dtsi +F: arch/arm/dts/rk3568-radxa-e25.dts +F: arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi + ROCK-3A M: Akash Gajjar <gajjar04akash(a)gmail.com> S: Maintained diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig new file mode 100644 index 000000000000..a905100a794d --- /dev/null +++ b/configs/radxa-e25-rk3568_defconfig @@ -0,0 +1,94 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-radxa-e25.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index e23237e453f3..10fffb56f13d 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -101,6 +101,7 @@ List of mainline supported Rockchip boards: - Pine64 SOQuartz on Blade (soquartz-blade-rk3566_defconfig) - Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566_defconfig) - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig) + - Radxa E25 Carrier Board (radxa-e25-rk3568_defconfig) * rk3588 - Rockchip EVB (evb-rk3588) -- 2.41.0

2 2

[PATCH v3] rockchip: rk3568: Add EmbedFire Lubancat 2 support
by Andy Yan 01 Aug '23

01 Aug '23

LubanCat2 is a rk3568 based SBC from EmbedFire. Specification: - Rockchip rk3568 - LPDDR4/4X 1/2/4/8 GB - TF scard slot - eMMC 8/32/64/128 GB - Gigabit ethernet x 2 - HDMI out - USB 2.0 Host x 1 - USB 2.0 Type-C OTG x 1 - USB 3.0 Host x 1 - Mini PCIE interface for WIFI/BT module - M.2 key for 2280 NVME - 40 pin header The dts file is sync from linux mainline. There are some dts bootph-all and USB3 update according to Jonas suggestion[0], so this patch based on Jonas patch [1] [2]. Signed-off-by: Andy Yan <andyshrk(a)163.com> [0]:http://patchwork.ozlabs.org/project/uboot/patch/20230708102556.25472-1-a… [1]:http://patchwork.ozlabs.org/project/uboot/cover/20230728115302.1735429-1… [2]:http://patchwork.ozlabs.org/project/uboot/cover/20230728124011.1747408-1… --- Changes in v3: - some alphabetical order update - disable all SPI flash related options. - remove bootph-all for pinctrl - add emmc_datastrobe pinconfig for hs200/hs400 in u-boot.dtsi - use USB_DWC3_GENERIC driver as Jonas suggested. - add CONFIG_SPL_DM_SEQ_ALIAS Changes in v2: - enable SPL_FIT_SIGNATURE arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi | 28 + arch/arm/dts/rk3568-lubancat-2.dts | 734 +++++++++++++++++++++ configs/lubancat-2-rk3568_defconfig | 87 +++ 4 files changed, 850 insertions(+) create mode 100644 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-lubancat-2.dts create mode 100644 configs/lubancat-2-rk3568_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index bd5887bf75..fb139a14fe 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -172,6 +172,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-anbernic-rgxx3.dtb \ rk3566-radxa-cm3-io.dtb \ rk3568-evb.dtb \ + rk3568-lubancat-2.dtb \ rk3568-nanopi-r5c.dtb \ rk3568-nanopi-r5s.dtb \ rk3568-odroid-m1.dtb \ diff --git a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi new file mode 100644 index 0000000000..52bd757bd0 --- /dev/null +++ b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023 Rockchip Electronics Co., Ltd + * (C) Copyright 2023 Andy Yan <andyshrk(a)163.com> + */ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3568-lubancat-2.dts b/arch/arm/dts/rk3568-lubancat-2.dts new file mode 100644 index 0000000000..da257b0591 --- /dev/null +++ b/arch/arm/dts/rk3568-lubancat-2.dts @@ -0,0 +1,734 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 EmbedFire <embedfire(a)embedfire.com> + * Copyright (c) 2023 Andy Yan <andyshrk(a)163.com> + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3568.dtsi" + +/ { + model = "EmbedFire LubanCat 2"; + compatible = "embedfire,lubancat-2", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + + user_led: user-led { + label = "user_led"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&user_led_pin>; + }; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + dc_5v: dc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_5v>; + }; + + vcc3v3_m2_pcie: vcc3v3-m2-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "m2_pcie_3v3"; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc3v3_m2_pcie_en>; + pinctrl-names = "default"; + startup-delay-us = <200000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_mini_pcie: vcc3v3-mini-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "minipcie_3v3"; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc3v3_mini_pcie_en>; + pinctrl-names = "default"; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb20_host: vcc5v0-usb20-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb20_host"; + enable-active-high; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc5v0_usb20_host_en>; + pinctrl-names = "default"; + }; + + vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb30_host"; + enable-active-high; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc5v0_usb30_host_en>; + pinctrl-names = "default"; + }; + + vcc5v0_otg_vbus: vcc5v0-otg-vbus-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg_vbus"; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc5v0_otg_vbus_en>; + pinctrl-names = "default"; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2s1_8ch { + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x22>; + rx_delay = <0x0e>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x21>; + rx_delay = <0x0e>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&gic { + mbi-ranges = <94 31>, <229 31>, <289 31>; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_m2_pcie>; + status = "okay"; +}; + +&pcie2x1 { + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + disable-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_mini_pcie>; + status = "okay"; +}; + +&pmu_io_domains { + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm8 { + status = "okay"; +}; + +&pwm9 { + status = "disabled"; +}; + +&pwm10 { + status = "disabled"; +}; + +&pwm14 { + status = "disabled"; +}; + +&spi3 { + pinctrl-0 = <&spi3m1_pins>; + status = "disabled"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; + status = "disabled"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&sdhci { + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>, <200000000>; + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + supports-emmc; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +/* USB OTG/USB Host_1 USB 2.0 Comb */ +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_otg_vbus>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +/* USB Host_2/USB Host_3 USB 2.0 Comb */ +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +/* MULTI_PHY0 For SATA0, USB3.0 OTG Only USB2.0 */ +&usb_host0_xhci { + phys = <&usb2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + dr_mode = "host"; + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +/* USB3.0 Host */ +&usb_host1_xhci { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&pinctrl { + leds { + user_led_pin: user-status-led-pin { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb20_host_en: vcc5v0-usb20-host-en { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb30_host_en: vcc5v0-usb30-host-en { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_vbus_en: vcc5v0-otg-vbus-en { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + vcc3v3_m2_pcie_en: vcc3v3-m2-pcie-en { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc3v3_mini_pcie_en: vcc3v3-mini-pcie-en { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig new file mode 100644 index 0000000000..278ee8dc70 --- /dev/null +++ b/configs/lubancat-2-rk3568_defconfig @@ -0,0 +1,87 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lubancat-2.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +# CONFIG_SPI_FLASH is not set +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y +CONFIG_EFI_VAR_BUF_SIZE=16384 -- 2.34.1

2 3

[PATCH V2] doc: board: ti: k3: Add a guide to debugging with OpenOCD
by Nishanth Menon 01 Aug '23

01 Aug '23

From: Jason Kacines <j-kacines(a)ti.com> Bootloader debug usually tends to be a bit dicey prior to DDR and serial port getting active in the system. JTAG typically remains the only practical debug option during the initial bringup. OpenOCD is one of the most popular environment for providing debug capability via a gdb compatible interface for developers to work with. Debugging U-boot and bootloaders on K3 platform does have a bit of tribal knowledge that is better documented in our common platform documentation. Signed-off-by: Jason Kacines <j-kacines(a)ti.com> Signed-off-by: Nishanth Menon <nm(a)ti.com> --- Changes since V1: * Merged into k3.rst and added anchors for include, reference to other files * Added documentation for other board documentation. V1: https://lore.kernel.org/u-boot/20230721191934.1959003-1-j-kacines@ti.com/ doc/board/ti/am62x_sk.rst | 16 + doc/board/ti/am65x_evm.rst | 16 + doc/board/ti/img/openocd-overview.svg | 580 ++++++++++++++++++++++++++ doc/board/ti/j7200_evm.rst | 16 + doc/board/ti/j721e_evm.rst | 16 + doc/board/ti/k3.rst | 468 +++++++++++++++++++++ 6 files changed, 1112 insertions(+) create mode 100644 doc/board/ti/img/openocd-overview.svg diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst index 637985cb096e..75aa1e827010 100644 --- a/doc/board/ti/am62x_sk.rst +++ b/doc/board/ti/am62x_sk.rst @@ -246,3 +246,19 @@ https://www.ti.com/lit/pdf/spruiv7 under the `Boot Mode Pins` section. - 11001010 For SW2 and SW1, the switch state in the "ON" position = 1. + +Debugging U-boot +---------------- + +See :ref:`Common Debugging environment - openOCD<k3_rst_refer_openocd>`: for +detailed setup information. + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_openocd_connect_xds110 + :end-before: .. k3_rst_include_end_openocd_connect_xds110 + +To start OpenOCD to connect to the board + +.. code-block:: bash + + openocd -f board/ti_am625evm.cfg diff --git a/doc/board/ti/am65x_evm.rst b/doc/board/ti/am65x_evm.rst index 0129235c2b29..daea943ebfbb 100644 --- a/doc/board/ti/am65x_evm.rst +++ b/doc/board/ti/am65x_evm.rst @@ -287,3 +287,19 @@ artifacts needed to the device: sb --ymodem tispl.bin > $MAIN_DEV < $MAIN_DEV sleep 1 sb --xmodem u-boot.img > $MAIN_DEV < $MAIN_DEV + +Debugging U-boot +---------------- + +See :ref:`Common Debugging environment - openOCD<k3_rst_refer_openocd>`: for +detailed setup information. + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_openocd_connect_xds110 + :end-before: .. k3_rst_include_end_openocd_connect_xds110 + +To start OpenOCD to connect to the board + +.. code-block:: bash + + openocd -f board/ti_am654evm.cfg diff --git a/doc/board/ti/img/openocd-overview.svg b/doc/board/ti/img/openocd-overview.svg new file mode 100644 index 000000000000..a86a5d7939a8 --- /dev/null +++ b/doc/board/ti/img/openocd-overview.svg @@ -0,0 +1,580 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> + + + + +<svg + xmlns:xhtml="http://www.w3.org/1999/xhtml" + xmlns:dc="http://purl.org/dc/elements/1.1/" + xmlns:cc="http://creativecommons.org/ns#" + xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns="http://www.w3.org/2000/svg" + xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" + xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" + version="1.1" + width="281px" + height="671px" + viewBox="-0.5 -0.5 281 671" + id="svg128" + sodipodi:docname="openocd-overview.svg" + inkscape:version="0.92.3 (2405546, 2018-03-11)"> + <metadata + id="metadata132"> + <rdf:RDF> + <cc:Work + rdf:about=""> + <dc:format>image/svg+xml</dc:format> + <dc:type + rdf:resource="http://purl.org/dc/dcmitype/StillImage" /> + </cc:Work> + </rdf:RDF> + </metadata> + <sodipodi:namedview + pagecolor="#ffffff" + bordercolor="#666666" + borderopacity="1" + objecttolerance="10" + gridtolerance="10" + guidetolerance="10" + inkscape:pageopacity="0" + inkscape:pageshadow="2" + inkscape:window-width="3440" + inkscape:window-height="1391" + id="namedview130" + showgrid="false" + inkscape:zoom="1.4068554" + inkscape:cx="283.8637" + inkscape:cy="385.05999" + inkscape:window-x="0" + inkscape:window-y="25" + inkscape:window-maximized="1" + inkscape:current-layer="svg128" /> + <defs + id="defs2" /> + <g + id="g118"> + <path + d="M 0 510 L 0 510 L 280 510 L 280 510" + fill="rgb(255, 255, 255)" + stroke="#ff0a1b" + stroke-miterlimit="10" + pointer-events="all" + id="path4" /> + <path + d="M 0 510 L 0 670 L 280 670 L 280 510" + fill="none" + stroke="#ff0a1b" + stroke-miterlimit="10" + pointer-events="none" + id="path6" /> + <rect + x="10" + y="590" + width="100" + height="70" + fill="#f8cecc" + stroke="#b85450" + pointer-events="none" + id="rect8" /> + <path + d="M 20 590 L 20 660 M 100 590 L 100 660" + fill="none" + stroke="#b85450" + stroke-miterlimit="10" + pointer-events="none" + id="path10" /> + <g + transform="translate(-0.5 -0.5)" + id="g16"> + <switch + id="switch14"> + <foreignObject + style="overflow: visible; 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align-items: unsafe center; justify-content: unsafe center; width: 58px; height: 1px; padding-top: 385px; margin-left: 141px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">USB</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="170" + y="389" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text74">USB</text> + </switch> + </g> + <g + transform="translate(-0.5 -0.5)" + id="g84"> + <switch + id="switch82"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 58px; height: 1px; padding-top: 485px; margin-left: 141px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">JTAG</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="170" + y="489" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text80">JTAG</text> + </switch> + </g> + <path + d="M 100 230 L 180 230 L 200 270 L 180 310 L 100 310 L 80 270 Z" + fill="#e1d5e7" + stroke="#9673a6" + stroke-miterlimit="10" + pointer-events="none" + id="path86" /> + <g + transform="translate(-0.5 -0.5)" + id="g92"> + <switch + id="switch90"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 118px; height: 1px; padding-top: 270px; margin-left: 81px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">OpenOCD</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="140" + y="274" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text88">OpenOCD</text> + </switch> + </g> + <path + d="M 140 200 L 140 220 L 140 210 L 140 223.63" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="none" + id="path94" /> + <path + d="M 140 228.88 L 136.5 221.88 L 140 223.63 L 143.5 221.88 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="none" + id="path96" /> + <path + d="M 100 120 L 180 120 L 200 160 L 180 200 L 100 200 L 80 160 Z" + fill="#e1d5e7" + stroke="#9673a6" + stroke-miterlimit="10" + pointer-events="none" + id="path98" /> + <g + transform="translate(-0.5 -0.5)" + id="g104"> + <switch + id="switch102"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 118px; height: 1px; padding-top: 160px; margin-left: 81px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">gdb</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="140" + y="164" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text100">gdb</text> + </switch> + </g> + <path + d="M 140 80 L 140 113.63" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="none" + id="path106" /> + <path + d="M 140 118.88 L 136.5 111.88 L 140 113.63 L 143.5 111.88 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="none" + id="path108" /> + <path + d="M 80 0 L 200 0 L 200 68 Q 170 46.4 140 68 Q 110 89.6 80 68 L 80 12 Z" + fill="#e1d5e7" + stroke="#9673a6" + stroke-miterlimit="10" + pointer-events="none" + id="path110" /> + <g + transform="translate(-0.5 -0.5)" + id="g116"> + <switch + id="switch114"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 118px; height: 1px; padding-top: 28px; margin-left: 81px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">IDE debugging code</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="140" + y="32" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text112">IDE debugging code</text> + </switch> + </g> + </g> +</svg> diff --git a/doc/board/ti/j7200_evm.rst b/doc/board/ti/j7200_evm.rst index 69abc55a93ce..021ff70d968f 100644 --- a/doc/board/ti/j7200_evm.rst +++ b/doc/board/ti/j7200_evm.rst @@ -201,3 +201,19 @@ fat formatted UDA FS as file. In case of booting from eMMC, write above images into raw or UDA FS. and set mmc partconf accordingly. + +Debugging U-boot +---------------- + +See :ref:`Common Debugging environment - openOCD<k3_rst_refer_openocd>`: for +detailed setup information. + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_openocd_connect_xds110 + :end-before: .. k3_rst_include_end_openocd_connect_xds110 + +To start OpenOCD to connect to the board + +.. code-block:: bash + + openocd -f board/ti_j7200evm.cfg diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst index f4b4c192d9da..f387a0e5139e 100644 --- a/doc/board/ti/j721e_evm.rst +++ b/doc/board/ti/j721e_evm.rst @@ -228,3 +228,19 @@ J721E common processor board can be attached to a Ethernet QSGMII card and the PHY in the card has to be reset before it can be used for data transfer. "do_main_cpsw0_qsgmii_phyinit" env variable has to be set for the U-BOOT to configure this PHY. + +Debugging U-boot +---------------- + +See :ref:`Common Debugging environment - openOCD<k3_rst_refer_openocd>`: for +detailed setup information. + +.. include:: k3.rst + :start-after: .. k3_rst_include_start_openocd_connect_xds110 + :end-before: .. k3_rst_include_end_openocd_connect_xds110 + +To start OpenOCD to connect to the board + +.. code-block:: bash + + openocd -f board/ti_j721eevm.cfg diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index 9d40675b6007..825ce2aec90e 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -467,3 +467,471 @@ filesystem and then imported => fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile} => env import -t ${loadaddr} ${filesize} + +.. _k3_rst_refer_openocd: + +Common Debugging environment - OpenOCD +-------------------------------------- + +This section will show you how to connect a board to `OpenOCD +<https://openocd.org/>`_ and load the SPL symbols for debugging with +a K3 generation device. To follow this guide, you must build custom +u-boot binaries, start your board from an boot media such as SD card, +and use OpenOCD environment. This section uses generic examples, +though you can apply these instructions to any supported K3 generation +device. + +Overall structure of this setup is shown in the following figure. + +.. image:: img/openocd-overview.svg + +.. note:: + + If you find these instructions useful, please consider `donating + <https://openocd.org/pages/donations.html>`_ to OpenOCD. + +Step 1: Download and install OpenOCD +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +To get started, it is more convenient if the distribution you +use supports OpenOCD by default. Follow the instructions in the +`getting OpenOCD <https://openocd.org/pages/getting-openocd.html>`_ +documentation to pick the installation steps appropriate to your +environment. Some references to OpenOCD documentations: + +* `OpenOCD User Guide <https://openocd.org/doc/html/index.html>`_ +* `OpenOCD Developer's Guide <https://openocd.org/doc/doxygen/html/index.html>`_ + +Refer to the release notes corresponding to the `OpenOCD version +<https://github.com/openocd-org/openocd/releases>`_ to ensure that: + +* Processor is supported: In general, the processor support + shouldn't present any difficulties since OpenOCD provides + solid support for both armv8 and armv7. +* SoC is supported: Support for System-on-a-Chip (SoC) usually + comes in the form of a tcl file that may be merged at various times. + One typically needs to ensure that the correct version of openOCD is + used OR use the tcl files from the mentioned or latest release. +* Board or the jtag adapter is supported: In most cases, board support + is a relatively easy problem to solve if the board has a jtag pin header. + All you need to do is ensure that the adapter you select is compatible + with OpenOCD. Some boards do come with onboard JTAG adapter that just + needs a USB cable to be plugged into the board, in which case, it is + important to ensure that the jtag adapter is supported. Fortunately, + almost all TI K3 SK/EVMs come with TI's xds110 which is supported out + of box with OpenOCD. The board specific documentation will cover the + details and any adapter recommendations. + +.. code-block:: bash + + openocd -v + +.. note:: + + OpenOCD version 0.12.0 is usually required to connect to most of K3 devices. + In case the support is on a newer version that is supported out of box + in your distribution, you may need to build it from source. + +Building OpenOCD from source +"""""""""""""""""""""""""""" + +Following dependency package installation instructions are based on +debian systems, but equivalent instructions should exist on systems +with other package managers. Please refer to `OpenOCD Documentation +<https://openocd.org/>`_ for more recent instructions. + +.. code-block:: bash + + $ sudo apt-get install libtool pkg-config texinfo libusb-dev \ + libusb-1.0.0-dev libftdi-dev libhidapi-dev autoconf automake + $ git clone https://github.com/openocd-org/openocd.git openocd + $ cd openocd + $ git submodule init + $ git submodule update + $ ./bootstrap + $ ./configure --prefix=/usr/local/ + $ make -j`nproc` + $ sudo make install + +.. note:: + + The example above uses the github mirror site. See + `git repo information <https://openocd.org/doc/html/Developers.html#OpenOCD-Git-Repository>`_ + information to pick the official git repo. + If a specific version is desired, select the version using `git checkout tag`. + +Installing OpenOCD udev rules +""""""""""""""""""""""""""""" + +The step is not necessary if the distribution supports the OpenOCD, but if +building from source, ensure that the udev rules are installed correctly to +ensure sane system. + +.. code-block:: bash + + # Go to the OpenOCD source directory + $ cd openocd + # Copy the udev rules to the correct system location + $ sudo cp ./contrib/60-openocd.rules \ + ./src/jtag/drivers/libjaylink/contrib/99-libjaylink.rules \ + /etc/udev/rules.d/ + # Get Udev to load the new rules up + $ sudo udevadm control --reload-rules + # Use the new rules on existing connected devices + $ sudo udevadm trigger + +Step 2: Setup gdb +^^^^^^^^^^^^^^^^^ + +Most systems come with gdb-multiarch package. + +.. code-block:: bash + + # Go to the OpenOCD source directory + $ sudo apt-get install gdb-multiarch + +Though using gdb natively is normal, developers with interest in using IDE +will find few of these interesting: + +* `gdb-dashboard <https://github.com/cyrus-and/gdb-dashboard>`_ +* `gef <https://github.com/hugsy/gef>`_ +* `peda <https://github.com/longld/peda>`_ +* `pwndbg <https://github.com/pwndbg/pwndbg>`_ +* `voltron <https://github.com/snare/voltron>`_ +* `ddd <https://www.gnu.org/software/ddd/>`_ +* `vscode <https://www.justinmklam.com/posts/2017/10/vscode-debugger-setup/>`_ +* `vim conque-gdb <https://github.com/vim-scripts/Conque-GDB>`_ +* `emacs realgud <https://github.com/realgud/realgud/wiki/gdb-notes>`_ +* `lauterbach IDE <https://www2.lauterbach.com/pdf/backend_gdb.pdf>`_ + +.. warning:: + lldb support for OpenOCD is still a work in progress as of this writing. + Using gdb is probably the safest option at this point in time. + +Step 3: Setup of board to PC +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +There are few patterns of boards in the ecosystem + +.. k3_rst_include_start_openocd_connect_xds110 + +**Integrated JTAG adapter**: The board has a micro-USB connector labelled +XDS110 USB or JTAG. Connect a USB cable to the board to the mentioned port. + +.. note:: + + There are multiple USB ports on a typical board, So, ensure you have read + the user guide for the board and confirm the silk screen label to ensure + connecting to the correct port. + +.. k3_rst_include_end_openocd_connect_xds110 + +.. k3_rst_include_start_openocd_connect_cti20 + +**cTI20 connector**: The TI's `cTI20 +<https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_jtag_connec…>`_ connector +is probably the most prevelant on TI platforms. Though many +TI boards do have onboard xds110, cTI20 connector is usually +provided as an alternate scheme to connect alternatives such +as `Lauterbach <https://www.lauterbach.com/>`_ or `xds560 +<https://www.ti.com/tool/TMDSEMU560V2STM-U>`_. + +To debug on these boards, the following combinations is suggested: + +* `TUMPA <https://www.diygadget.com/jtag-cables-and-microcontroller-programmers/tiao-…>`_ + or equivalent supported by OpenOCD +* Cable such as `Tag-connect ribbon cable <https://www.tag-connect.com/product/20-pin-cortex-ribbon-cable-4-length-wit…>`_ +* Adapter to convert cTI20 to ARM20 such as those from + `Segger <https://www.segger.com/products/debug-probes/j-link/accessories/adapters/ti…>`_ + `Lauterbach LA-3780 <https://www.lauterbach.com/ad3780.html>`_ + Or optionally, if you have manufacturing capability then you could try + `beagle bone jtag adapter <https://github.com/mmorawiec/BeagleBone-Black-JTAG-Adapters>`_ + +.. warning:: + XDS560 and Lauterbach are proprietary solutions and is not supported by + OpenOCD. + When purchasing off the shelf adapters, you do want to be careful about the + signalling though. Please `read for additional info <https://software-dl.ti.com/ccs/esd/xdsdebugprobes/emu_jtag_connectors.html>`_ + +.. k3_rst_include_end_openocd_connect_cti20 + +.. k3_rst_include_start_openocd_connect_tag_connect + +**Tag-Connect**: `Tag-Connect <https://www.tag-connect.com/>`_ +pads on the boards which require special cable. Please check the documentation +to `identify <https://www.tag-connect.com/info/legs-or-no-legs>`_ if "legged" +or "no-leg" version of the cable is appropriate for the board. + +To debug on these boards, you will need: + +* `TUMPA <https://www.diygadget.com/jtag-cables-and-microcontroller-programmers/tiao-…>`_ + or equivalent supported by OpenOCD +* Tag-Connect cable appropriate to the board such as + `tc2050-idc-nl <https://www.tag-connect.com/product/tc2050-idc-nl-10-pin-no-legs-cable-with…>`_ +* In case of no-leg, version, a + `retaining clip <https://www.tag-connect.com/product/tc2050-clip-3pack-retaining-clip>`_ +* Tag-Connect to ARM20 + `adapter <https://www.tag-connect.com/product/tc2050-arm2010-arm-20-pin-to-tc2050-ada…>`_ + +.. note:: + You can optionally use a 3d printed solution such as + `Protective cap <https://www.thingiverse.com/thing:3025584>`_ or + `clip <https://www.thingiverse.com/thing:3035278>`_ to replace + the retaining clip. + +.. warning:: + With the Tag-Connect to ARM20 adapter, Please solder the "Trst" signal for + connection to work. + +.. k3_rst_include_end_openocd_connect_tag_connect + +Debugging with OpenOCD +^^^^^^^^^^^^^^^^^^^^^^ + +Debugging U-boot is different from debugging regular user space +applications. The bootloader initialization process involves many boot +media and hardware configuration operations. For K3 devices, there +are also interactions with security firmware. While reloading the +"elf" file works through gdb, developers must be mindful of cascading +initialization's potential consequences. + +Consider the following code change: + +.. code-block:: diff + + --- a/file.c 2023-07-29 10:55:29.647928811 -0500 + +++ b/file.c 2023-07-29 10:55:46.091856816 -0500 + @@ -1,3 +1,3 @@ + val = readl(reg); + -val |= 0x2; + +val |= 0x1; + writel(val, reg); + +Re-running the elf file with the above change will result in the +register setting 0x3 instead of the intended 0x1. There are other +hardware blocks which may not behave very well with re-initialization +sequence without proper shutdown. + +To help narrow the debug down, it is usually more simpler to use the +standard boot media to get to the booloader and debug only in the area +of interest. + +In general, to debug u-boot spl/u-boot with OpenOCD there are three steps: + +* Modify the code to put a loop to allow debugger to attach near the point + of interest. Boot up normally to stop at the loop. +* Connect with OpenOCD and step out of the loop +* Step through code to find the root of issue + +Typical debug involves a few iterations of the above sequence. Though +most bootloader developers like to use printf to debug, debug with +jtag tends to be most efficient since it is possible to investigate +code flow and inspect hardware registers without repeated iterations. + +Code modification +""""""""""""""""" + +* **start.S**: Adding an infinite while loop at the very entry of + U-Boot. For this, look for the corresponding start.S entry file. + This is usually only required when debugging some core SoC or + processor related function. For example: arch/arm/cpu/armv8/start.S or + arch/arm/cpu/armv7/start.S + +.. code-block:: diff + + diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S + index 69e281b086..744929e825 100644 + --- a/arch/arm/cpu/armv7/start.S + +++ b/arch/arm/cpu/armv7/start.S + @@ -37,6 +37,8 @@ + #endif + + reset: + +dead_loop: + + b dead_loop + /* Allow the board to save important registers */ + b save_boot_params + save_boot_params_ret: + +* **board_init_f**: Adding an infinite while loop at the board entry + function. In many cases, it is important to debug the boot process if + any changes are made for board-specific applications. Below is a step + by step process for debugging the boot SPL or Armv8 SPL: + + To debug the boot process in either domain, we will first + add a modification in the code we would like to debug. + In this example, we will debug ``board_init_f`` inside + ``arch/arm/mach-k3/{soc}_init.c``. Since some sections of U-Boot + will be executed multiple times during the bootup process of K3 + devices, we will need to include either ``CONFIG_CPU_ARM64`` or + ``CONFIG_CPU_V7R`` to catch the CPU at the desired place during the + bootup process (Main or Wakeup domains). For example, modify the + file as follows (depending on need): + +.. code-block:: c + + void board_init_f(ulong dummy) + { + . + . + /* Code to run on the R5F (Wakeup/Boot Domain) */ + if (IS_ENABLED(CONFIG_CPU_V7R)) { + volatile int x = 1; + while(x) {}; + } + ... + /* Code to run on the ARMV8 (Main Domain) */ + if (IS_ENABLED(CONFIG_CPU_ARM64)) { + volatile int x = 1; + while(x) {}; + } + . + . + } + +Connecting with OpenOCD for debug session +""""""""""""""""""""""""""""""""""""""""" + +Startup openocd to debug the platform as follows: + +* **integrated jtag interface**: If the evm has a debugger such as + xds110 inbuilt, there is typically an evm board support added and a + cfg file will be available. + +.. k3_rst_include_start_openocd_cfg_xds110 + +.. code-block:: bash + + openocd -f board/{board_of_choice}.cfg + +.. k3_rst_include_end_openocd_cfg_xds110 + +* **External jtag adapter/interface**: In other cases, where an + adapter is used, a simple cfg file can be created to integrate the SoC + and adapter information. See `supported TI K3 SoCs + <https://github.com/openocd-org/openocd/blob/master/tcl/target/ti_k3.cfg#L59>`_ + to decide if the SoC is supported or not. + + For example, with BeaglePlay (AM62X platform): + +.. code-block:: tcl + + # TUMPA example: + # http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User's_Manual + source [find interface/ftdi/tumpa.cfg] + + transport select jtag + + # default JTAG configuration has only SRST and no TRST + reset_config srst_only srst_push_pull + + # delay after SRST goes inactive + adapter srst delay 20 + + if { ![info exists SOC] } { + # Set the SoC of interest + set SOC am625 + } + + source [find target/ti_k3.cfg] + + ftdi tdo_sample_edge falling + + # Speeds for FT2232H are in multiples of 2, and 32MHz is tops + # max speed we seem to achieve is ~20MHz.. so we pick 16MHz + adapter speed 16000 + +Below is an example of what the output of this command will print. + +.. code-block:: console + + Info : Listening on port 6666 for tcl connections + Info : Listening on port 4444 for telnet connections + Info : XDS110: connected + Info : XDS110: vid/pid = 0451/bef3 + Info : XDS110: firmware version = 3.0.0.20 + Info : XDS110: hardware version = 0x002f + Info : XDS110: connected to target via JTAG + Info : XDS110: TCK set to 2500 kHz + Info : clock speed 2500 kHz + Info : JTAG tap: am625.cpu tap/device found: 0x0bb7e02f (mfg: 0x017 (Texas Instruments), part: 0xbb7e, ver: 0x0) + Info : starting gdb server for am625.cpu.sysctrl on 3333 + Info : Listening on port 3333 for gdb connections + Info : starting gdb server for am625.cpu.a53.0 on 3334 + Info : Listening on port 3334 for gdb connections + Info : starting gdb server for am625.cpu.a53.1 on 3335 + Info : Listening on port 3335 for gdb connections + Info : starting gdb server for am625.cpu.a53.2 on 3336 + Info : Listening on port 3336 for gdb connections + Info : starting gdb server for am625.cpu.a53.3 on 3337 + Info : Listening on port 3337 for gdb connections + Info : starting gdb server for am625.cpu.main0_r5.0 on 3338 + Info : Listening on port 3338 for gdb connections + Info : starting gdb server for am625.cpu.gp_mcu on 3339 + Info : Listening on port 3339 for gdb connections + +.. note:: + Notice the default configuration is non-SMP configuration allowing + for each of the core to be attached and debugged simultaneously. + armv8 SPL/U-boot starts up on cpu0 of a53/a72. + +To debug using this server, use gdb directly or your preferred +gdb-based IDE. To start up gdb in the terminal, run the following +command. + +.. code-block:: bash + + gdb-multiarch + +To connect to your desired core, run the following command within gdb +and load the symbols from the corresponding elf file. + +.. code-block:: bash + + target extended-remote localhost:{port for desired core} + symbol-file {path to elf file} + +In the above example of AM625, + +.. code-block:: bash + + target extended-remote localhost:3338 <- R5F (Wakeup Domain) + target extended-remote localhost:3334 <- A53 (Main Domain) + +The core can now be debugged directly within gdb using gdb commands or +if using IDE, as appropriate to the IDE. + +Stepping through the code +""""""""""""""""""""""""" + +Use the gdb command ``lay next`` after loading the symbols to see the +code and breakpoints. To exit the debug loop added above, add any +breakpoints needed and run the following gdb commands. + +.. code-block:: bash + + set x = 0 + continue + +The platform has now been successfully setup to debug with OpenOCD +using gdb commands or a gdb-based IDE. See `OpenOCD documentation for +gdb <https://openocd.org/doc/html/GDB-and-OpenOCD.html>`_ for further +information. + +.. warning:: + + On the K3 family of devices, a watchdog timer within the DMSC is + enabled by default by the ROM bootcode with a timeout of 3 minutes. + The watchdog timer is serviced by System Firmware (SYSFW) or TI + Foundational Security (TIFS) during normal operation. If debugging + the SPL before the SYSFW is loaded, the watchdog timer will not get + serviced automatically and the debug session will reset after 3 + minutes. It is recommended to start debugging SPL code only after + the startup of SYSFW to avoid running into the watchdog timer reset. + +Misc notes with openOCD +^^^^^^^^^^^^^^^^^^^^^^^ + +At the time of this writing openOCD does not support tracing for K3 +platforms. Tracing function could be very useful if the bug in code +occurs deep within nested function and can optionally save developers +major trouble of stepping through large quantity of code. -- 2.37.2

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[PATCH] spl: spl_legacy: Fix spl_end address for non ARM target
by Shiji Yang 01 Aug '23

01 Aug '23

Only ARM target defines _image_binary_end symbol as char*, All other targets define it as an ulong type in include/asm-generic/sections.h. This patch fixes the boot failure on MIPS target. Error log: SPL: Image overlaps SPL Fixes: 1b8a1be1a1f1 ("spl: spl_legacy: Fix spl_end address") Signed-off-by: Shiji Yang <yangshiji66(a)outlook.com> --- common/spl/spl_legacy.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c index 095443c63d..0fef890384 100644 --- a/common/spl/spl_legacy.c +++ b/common/spl/spl_legacy.c @@ -18,9 +18,13 @@ static void spl_parse_legacy_validate(uintptr_t start, uintptr_t size) { + uintptr_t end = start + size; uintptr_t spl_start = (uintptr_t)_start; +#ifdef CONFIG_ARM uintptr_t spl_end = (uintptr_t)_image_binary_end; - uintptr_t end = start + size; +#else + uintptr_t spl_end = (uintptr_t)&_image_binary_end; +#endif /* CONFIG_ARM */ if ((start >= spl_start && start < spl_end) || (end > spl_start && end <= spl_end) || -- 2.39.2

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