June 2023 - U-Boot

[PATCH] drivers: clk: Adjust temp var data type to properly match that of struct clk_ops
by Nathan Barrett-Morrison 01 Nov '23

01 Nov '23

In commit 5c5992cb90cf ("clk: Add debugging for return values"), a temporary storage variable was added around the ops->get_rate() call inside clk_get_rate(), so that the result could be passed through log_ret. This temporary variable was declared as an int, yet when we look in struct clk_ops, we can see this needs to be a ulong: ulong (*get_rate)(struct clk *clk); This was resulting in a signed to unsigned casting error on our builds, where a clock value of 0xABCDABCD was being incorrectly cast to 0xFFFFFFFFABCDABCD. Signed-off-by: Nathan Barrett-Morrison <nathan.morrison(a)timesys.com> --- drivers/clk/clk-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index dc3e9d6a26..4e3e3b8537 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -471,7 +471,7 @@ void clk_free(struct clk *clk) ulong clk_get_rate(struct clk *clk) { const struct clk_ops *ops; - int ret; + ulong ret; debug("%s(clk=%p)\n", __func__, clk); if (!clk_valid(clk)) -- 2.34.1

2 2

[PATCH] clk: fix count parameter type for clk_release_all
by Eugen Hristev 01 Nov '23

01 Nov '23

The second parameter for clk_release_all is used as an unsigned (which makes sense) but the function prototype declares it as an int. This causes warnings/error like such below: include/clk.h:422:48: error: conversion to ‘int’ from ‘unsigned int’ may change the sign of the result [-Werror=sign-conversion] 422 | return clk_release_all(bulk->clks, bulk->count); To fix this, changed the type of the count to `unsigned int` Fixes: 82a8a669b4f7 ("clk: add clk_release_all()") Signed-off-by: Eugen Hristev <eugen.hristev(a)collabora.com> --- drivers/clk/clk-uclass.c | 7 ++++--- include/clk.h | 4 ++-- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index dc3e9d6a2615..eada3a3a5b62 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -416,12 +416,13 @@ int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk) return clk_get_by_index_nodev(node, index, clk); } -int clk_release_all(struct clk *clk, int count) +int clk_release_all(struct clk *clk, unsigned int count) { - int i, ret; + unsigned int i; + int ret; for (i = 0; i < count; i++) { - debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]); + debug("%s(clk[%u]=%p)\n", __func__, i, &clk[i]); /* check if clock has been previously requested */ if (!clk[i].dev) diff --git a/include/clk.h b/include/clk.h index d91285235f79..a342297007b6 100644 --- a/include/clk.h +++ b/include/clk.h @@ -243,7 +243,7 @@ static inline struct clk *devm_clk_get_optional(struct udevice *dev, * * Return: zero on success, or -ve error code. */ -int clk_release_all(struct clk *clk, int count); +int clk_release_all(struct clk *clk, unsigned int count); /** * devm_clk_put - "free" a managed clock source @@ -307,7 +307,7 @@ clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk) return -ENOSYS; } -static inline int clk_release_all(struct clk *clk, int count) +static inline int clk_release_all(struct clk *clk, unsigned int count) { return -ENOSYS; } -- 2.34.1

3 4

[PATCH] clk: change log_err() to log_info() to make it quiet with clk_register_fixed_rate()
by notfound405 01 Nov '23

01 Nov '23

clk_register_fixed_rate() calls clk_register() with the fourth argument(parent_name) being NULL, making it output error message. Change to log_info() to fix it. Signed-off-by: Yang Xiwen <forbidden405(a)foxmail.com> --- The previous email is signed with a wrong name. The patch is not modified. drivers/clk/clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index a5a3461b66..0619937cee 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -24,7 +24,7 @@ int clk_register(struct clk *clk, const char *drv_name, ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent); if (ret) { - log_err("%s: failed to get %s device (parent of %s)\n", + log_info("%s: failed to get %s device (parent of %s)\n", __func__, parent_name, name); } else { log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name, -- 2.39.2

2 1

[PATCH v1] clk: nuvoton: add read only feature for clk driver
by Jim Liu 01 Nov '23

01 Nov '23

Set ahb/apb/fiu clock divider as read-only Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> --- drivers/clk/nuvoton/clk_npcm.c | 15 ++++++++++++--- drivers/clk/nuvoton/clk_npcm.h | 1 + drivers/clk/nuvoton/clk_npcm8xx.c | 12 ++++++------ 3 files changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/clk/nuvoton/clk_npcm.c b/drivers/clk/nuvoton/clk_npcm.c index 8d71f2a24b..18cb9cddbf 100644 --- a/drivers/clk/nuvoton/clk_npcm.c +++ b/drivers/clk/nuvoton/clk_npcm.c @@ -135,7 +135,7 @@ static u32 npcm_clk_get_div(struct clk *clk) return div; } -static u32 npcm_clk_set_div(struct clk *clk, u32 div) +static int npcm_clk_set_div(struct clk *clk, u32 div) { struct npcm_clk_priv *priv = dev_get_priv(clk->dev); struct npcm_clk_div *divider; @@ -145,6 +145,9 @@ static u32 npcm_clk_set_div(struct clk *clk, u32 div) if (!divider) return -EINVAL; + if (divider->flags & DIV_RO) + return 0; + if (divider->flags & PRE_DIV2) div = div >> 1; @@ -153,6 +156,12 @@ static u32 npcm_clk_set_div(struct clk *clk, u32 div) else clkdiv = ilog2(div); + if (clkdiv > (divider->mask >> (ffs(divider->mask) - 1))) { + printf("clkdiv(%d) for clk(%ld) is over limit\n", + clkdiv, clk->id); + return -EINVAL; + } + val = readl(priv->base + divider->reg); val &= ~divider->mask; val |= (clkdiv << (ffs(divider->mask) - 1)) & divider->mask; @@ -253,8 +262,8 @@ static ulong npcm_clk_set_rate(struct clk *clk, ulong rate) if (ret) return ret; - debug("%s: rate %lu, new rate (%lu / %u)\n", __func__, rate, parent_rate, div); - return (parent_rate / div); + debug("%s: rate %lu, new rate %lu\n", __func__, rate, npcm_clk_get_rate(clk)); + return npcm_clk_get_rate(clk); } static int npcm_clk_set_parent(struct clk *clk, struct clk *parent) diff --git a/drivers/clk/nuvoton/clk_npcm.h b/drivers/clk/nuvoton/clk_npcm.h index 06b60dc8b8..b4726d8381 100644 --- a/drivers/clk/nuvoton/clk_npcm.h +++ b/drivers/clk/nuvoton/clk_npcm.h @@ -50,6 +50,7 @@ #define PRE_DIV2 BIT(2) /* Pre divisor = 2 */ #define POST_DIV2 BIT(3) /* Post divisor = 2 */ #define FIXED_PARENT BIT(4) /* clock source is fixed */ +#define DIV_RO BIT(5) /* divider is read-only */ /* Parameters of PLL configuration */ struct npcm_clk_pll { diff --git a/drivers/clk/nuvoton/clk_npcm8xx.c b/drivers/clk/nuvoton/clk_npcm8xx.c index 27e3cfcf55..d1b32e3237 100644 --- a/drivers/clk/nuvoton/clk_npcm8xx.c +++ b/drivers/clk/nuvoton/clk_npcm8xx.c @@ -45,12 +45,12 @@ static struct npcm_clk_select npcm8xx_clk_selectors[] = { }; static struct npcm_clk_div npcm8xx_clk_dividers[] = { - {NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2}, - {NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2}, - {NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2}, - {NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1}, - {NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1}, - {NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1}, + {NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2 | DIV_RO}, + {NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2 | DIV_RO}, + {NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2 | DIV_RO}, + {NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1 | DIV_RO}, + {NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1 | DIV_RO}, + {NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1 | DIV_RO}, {NPCM8XX_CLK_SPIX, CLKDIV3, SPIXCKDIV, DIV_TYPE1}, {NPCM8XX_CLK_UART, CLKDIV1, UARTDIV1, DIV_TYPE1}, {NPCM8XX_CLK_UART2, CLKDIV3, UARTDIV2, DIV_TYPE1}, -- 2.17.1

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[PATCH v4 0/2] sunxi, usb: Clean up SRAM initialization code
by Sam Edwards 01 Nov '23

01 Nov '23

Hi list, Only change from v4 is that I reworded the commit message in 2/2 not to mention the TODO comment block that I removed in v3. Cheers, Sam Sam Edwards (2): usb: musb-new: sunxi: only perform SRAM initialization when necessary usb: musb-new: sunxi: clarify the purpose of SRAM initialization drivers/usb/musb-new/sunxi.c | 36 +++++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) -- 2.39.2

2 3

[PATCH 1/3] arm: dts: imx8mm: Sync with Linux 6.3
by Fabio Estevam 18 Oct '23

18 Oct '23

From: Fabio Estevam <festevam(a)denx.de> Sync imx8mm.dtsi with Linux 6.3. The motivation for doing this sync was a bug when doing "ums 0 mmc 1" on imx8mm-evk. It worked well for the first time, but after doing a CTRL+C and launching the ums again, the command did not work. Adam Ford suggested to sync imx8mm.dtsi with the Linux dts, as there was a recent USB power domain reorganization there. After syncing the imx8mm.dtsi with Linux, the ums command works without problem after a CTRL+C. Suggested-by: Adam Ford <aford173(a)gmail.com> Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- arch/arm/dts/imx8mm.dtsi | 52 +++++++++++++++++++++++++++++----------- 1 file changed, 38 insertions(+), 14 deletions(-) diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi index afb90f59c83c..31f4548f85cf 100644 --- a/arch/arm/dts/imx8mm.dtsi +++ b/arch/arm/dts/imx8mm.dtsi @@ -139,6 +139,7 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; @@ -276,6 +277,7 @@ assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; clock-names = "main_clk"; + power-domains = <&pgc_otg1>; }; usbphynop2: usbphynop2 { @@ -285,6 +287,7 @@ assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; clock-names = "main_clk"; + power-domains = <&pgc_otg2>; }; soc: soc@0 { @@ -493,6 +496,8 @@ compatible = "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; }; @@ -547,8 +552,8 @@ reg = <0x30330000 0x10000>; }; - gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; + gpr: syscon@30340000 { + compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; @@ -560,22 +565,40 @@ #address-cells = <1>; #size-cells = <1>; - imx8mm_uid: unique-id@410 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = <ADDR SIZE>; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x4 0x8> describes fuses 0x410 and + * 0x420). + */ + imx8mm_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - fec_mac_address: mac-address@90 { + tmu_calib: calib@3c { /* 0x4f0 */ + reg = <0x3c 4>; + }; + + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; }; - anatop: anatop@30360000 { - compatible = "fsl,imx8mm-anatop", "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; + #clock-cells = <1>; }; snvs: snvs@30370000 { @@ -674,13 +697,11 @@ pgc_otg1: power-domain@2 { #power-domain-cells = <0>; reg = <IMX8MM_POWER_DOMAIN_OTG1>; - power-domains = <&pgc_hsiomix>; }; pgc_otg2: power-domain@3 { #power-domain-cells = <0>; reg = <IMX8MM_POWER_DOMAIN_OTG2>; - power-domains = <&pgc_hsiomix>; }; pgc_gpumix: power-domain@4 { @@ -1186,7 +1207,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; - power-domains = <&pgc_otg1>; + power-domains = <&pgc_hsiomix>; status = "disabled"; }; @@ -1206,7 +1227,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop2>; fsl,usbmisc = <&usbmisc2 0>; - power-domains = <&pgc_otg2>; + power-domains = <&pgc_hsiomix>; status = "disabled"; }; @@ -1238,16 +1259,15 @@ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; }; - gpmi: nand-controller@33002000{ + gpmi: nand-controller@33002000 { compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; reg = <0x33002000 0x2000>, <0x33004000 0x4000>; reg-names = "gpmi-nand", "bch"; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; @@ -1282,6 +1302,10 @@ <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; linux,pci-domain = <0>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; -- 2.34.1

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[PATCH 0/3] Use FEAT_HAFDBS to track dirty pages
by Ying-Chun Liu (PaulLiu) 17 Oct '23

17 Oct '23

For some ARM64 cores there is a facility that allows the page table walker to track the dirty state of a page. These commits enhances the performance of CMOs by VA. Marc Zyngier (2): arm64: Use FEAT_HAFDBS to track dirty pages when available arm64: Use level-2 for largest block mappings when FEAT_HAFDBS is present meitao (1): armv8: enable HAFDBS for other ELx when FEAT_HAFDBS is present arch/arm/cpu/armv8/cache_v8.c | 30 +++++++++++++++++++++++++++--- arch/arm/include/asm/armv8/mmu.h | 20 ++++++++++++++++---- arch/arm/include/asm/global_data.h | 2 ++ 3 files changed, 45 insertions(+), 7 deletions(-) -- 2.39.2

4 12

[PATCH v3 0/2] dfu: mtd: mark bad the MTD block on erase error
by Patrick Delaunay 13 Oct '23

13 Oct '23

V3 for http://patchwork.ozlabs.org/project/uboot/list/?series=357878 after remarks and missing impact after comts d9fa61f54e7f9a ("mtd: nand: Show reserved block in chip.erase") and cfb82f7c123e4 ("mtd: nand: Mark reserved blocks") Patrick Changes in v3: - Split serie with trace fix and support of bad block in MTD erase - Fix trace for "bbt reserved" when mtd_block_isbad return 2 Changes in v2: - fix mtd_block_isbad offset parameter for erase check - Add trace when bad block are skipped in erase loop - Add remaining byte in trace "Limit reached" Patrick Delaunay (2): dfu: mtd: fix the trace when limit is reached dfu: mtd: mark bad the MTD block on erase error drivers/dfu/dfu_mtd.c | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) -- 2.25.1

3 5

[PATCH] ARM: stm32: Power cycle Buck3 in reset on DHSOM
by Marek Vasut 12 Oct '23

12 Oct '23

In case the DHSOM is in suspend state and either reset button is pushed or IWDG2 triggers a watchdog reset, then DRAM initialization could fail as follows: " RAM: DDR3L 32bits 2x4Gb 533MHz DDR invalid size : 0x4, expected 0x40000000 DRAM init failed: -22 ### ERROR ### Please RESET the board ### " Avoid this failure by not keeping any Buck regulators enabled during reset, let the SoC and DRAMs power cycle fully. Since the change which keeps Buck3 VDD enabled during reset is ST specific, move this addition to ST specific SPL board initialization so that it wouldn't affect the DHSOM . Signed-off-by: Marek Vasut <marex(a)denx.de> --- NOTE: This is 2023.07 material NOTE: d1a4b09de64 ("board: st: stpmic1: add function stpmic1_init") mentions 'keep vdd on during the reset cycle (to avoid issue when backup battery is absent)', but there is no further description of the 'issue'. Can you please elaborate ? --- Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: uboot-stm32(a)st-md-mailman.stormreply.com --- board/st/common/stpmic1.c | 10 +++------- board/st/common/stpmic1.h | 2 +- board/st/stm32mp1/spl.c | 13 +++++++++++-- 3 files changed, 15 insertions(+), 10 deletions(-) diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c index d52dce4f657..969ad484864 100644 --- a/board/st/common/stpmic1.c +++ b/board/st/common/stpmic1.c @@ -185,21 +185,17 @@ static int stmpic_buck1_set(struct udevice *dev, u32 voltage_mv) } /* early init of PMIC */ -void stpmic1_init(u32 voltage_mv) +struct udevice *stpmic1_init(u32 voltage_mv) { struct udevice *dev; if (uclass_get_device_by_driver(UCLASS_PMIC, DM_DRIVER_GET(pmic_stpmic1), &dev)) - return; + return NULL; /* update VDDCORE = BUCK1 */ if (voltage_mv) stmpic_buck1_set(dev, voltage_mv); - /* Keep vdd on during the reset cycle */ - pmic_clrsetbits(dev, - STPMIC1_BUCKS_MRST_CR, - STPMIC1_MRST_BUCK(STPMIC1_BUCK3), - STPMIC1_MRST_BUCK(STPMIC1_BUCK3)); + return dev; } diff --git a/board/st/common/stpmic1.h b/board/st/common/stpmic1.h index b17d6f16338..7a7169d7cea 100644 --- a/board/st/common/stpmic1.h +++ b/board/st/common/stpmic1.h @@ -3,4 +3,4 @@ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved */ -void stpmic1_init(u32 voltage_mv); +struct udevice *stpmic1_init(u32 voltage_mv); diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c index 747ec7e445a..8b4a529f759 100644 --- a/board/st/stm32mp1/spl.c +++ b/board/st/stm32mp1/spl.c @@ -5,6 +5,8 @@ #include <config.h> #include <common.h> +#include <power/pmic.h> +#include <power/stpmic1.h> #include <asm/arch/sys_proto.h> #include "../common/stpmic1.h" @@ -19,8 +21,15 @@ void board_vddcore_init(u32 voltage_mv) int board_early_init_f(void) { - if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER)) - stpmic1_init(opp_voltage_mv); + if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER)) { + struct udevice *dev = stpmic1_init(opp_voltage_mv); + + /* Keep vdd on during the reset cycle */ + pmic_clrsetbits(dev, + STPMIC1_BUCKS_MRST_CR, + STPMIC1_MRST_BUCK(STPMIC1_BUCK3), + STPMIC1_MRST_BUCK(STPMIC1_BUCK3)); + } return 0; } -- 2.39.2

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[PATCH v5 00/11] Add ethernet driver for StarFive JH7110 SoC
by Yanhong Wang 11 Oct '23

11 Oct '23

This series of patches base on the latest branch/master,and adds ethernet support for the StarFive JH7110 RISC-V SoC. The series includes EEPROM, PHY and MAC drivers. The PHY model is YT8531 (from Motorcomm Inc), and the MAC version is dwmac-5.20 (from Synopsys DesignWare). The implementation of the phy driver is ported from linux, but it has been adjusted for the u-boot framework. EEPROM stores board-related information, such as DDR capacity, PCB version, MAC address, etc. The main difference between StarFive VisionFive 2 1.2A and 1.3B is gmac, but the difference in gmac is not defined in DT, but reads the PCB version from EEPROM, and then dynamically configures the difference of gmac according to different PCB versions, which is compatible with 1.2A and 1.3B versions, which is more user-friendly. The PHY and MAC driver has been tested on the StarFive VisionFive 2 1.2A and 1.3B boards and works normally. For more information and support,you can visit RVspace wiki[1]. [1] https://wiki.rvspace.org/ v5: - Reorder a series of patches to make each patch is independent. - Move CONFIG_DEFAULT_FDT_FILE and CONFIG_DEFAULT_DEVICE_TREE changes to patch 4. - Move the definition of 'board_fdt_blob_setup' to patch 9. v4: - Reworded the definition of the 'pbuf' variable in visionfive2-i2c-eeprom.c from a const pointer to const union. - Added the section (".data") attribute to the 'pbuf' and 'has_been_read' global variables in visionfive2-i2-eeprom.c. v3: - Added EEPROM support. - Combine the board device tree of 1.2A and 1.3B into one. - Removed the delay configuration of gmac phy clock from DT. - Dynamically configure gmac differences of 1.2A and 1.3B to DT according to the PCB version. - DDR capacity information is read from EEPROM first, if not, it is defined by default in DT. v2: - Reworded the phy driver. Added platform private data struct to save the configuration data read from dts. - Reworded the MAC driver. Added platform private data struct to save the configuration data read from dts. Previous versions: v1 - https://patchwork.ozlabs.org/project/uboot/cover/20230317010536.17860-1-yan… v2 - https://patchwork.ozlabs.org/project/uboot/cover/20230329102720.25439-1-yan… v3 - https://patchwork.ozlabs.org/project/uboot/cover/20230428022515.29393-1-yan… v4 - https://patchwork.ozlabs.org/project/uboot/cover/20230525093637.31364-1-yan… Yanhong Wang (11): net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy net: dwc_eth_qos: Add StarFive ethernet driver glue layer riscv: dts: jh7110: Add ethernet device tree nodes riscv: dts: jh7110: Combine the board device tree files of 1.2A and 1.3B doc: board: starfive:　Reword the make defconfig information configs: starfive: Enable ethernet configuration for StarFive VisionFive2 eeprom: starfive: Enable ID EEPROM configuration riscv: dts: starfive: Add support eeprom device tree node configs: starfive: Enable ID EEPROM configuration ram: starfive: Read memory size information from EEPROM board: starfive: Dynamic configuration of DT for 1.2A and 1.3B arch/riscv/cpu/jh7110/spl.c | 32 +- arch/riscv/dts/Makefile | 3 +- ... jh7110-starfive-visionfive-2-u-boot.dtsi} | 39 +- .../jh7110-starfive-visionfive-2-v1.2a.dts | 12 - ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69 --- ...b.dts => jh7110-starfive-visionfive-2.dts} | 3 +- .../dts/jh7110-starfive-visionfive-2.dtsi | 40 ++ arch/riscv/dts/jh7110.dtsi | 69 +++ arch/riscv/include/asm/arch-jh7110/eeprom.h | 13 + board/starfive/visionfive2/Makefile | 1 + board/starfive/visionfive2/spl.c | 157 +++++ .../visionfive2/starfive_visionfive2.c | 13 + .../visionfive2/visionfive2-i2c-eeprom.c | 561 ++++++++++++++++++ configs/starfive_visionfive2_defconfig | 32 +- doc/board/starfive/visionfive2.rst | 6 +- drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/dwc_eth_qos.c | 6 + drivers/net/dwc_eth_qos.h | 1 + drivers/net/dwc_eth_qos_starfive.c | 249 ++++++++ drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/motorcomm.c | 437 ++++++++++++++ drivers/ram/starfive/starfive_ddr.c | 2 - 24 files changed, 1665 insertions(+), 95 deletions(-) rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi => jh7110-starfive-visionfive-2-u-boot.dtsi} (58%) delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi rename arch/riscv/dts/{jh7110-starfive-visionfive-2-v1.3b.dts => jh7110-starfive-visionfive-2.dts} (65%) create mode 100644 arch/riscv/include/asm/arch-jh7110/eeprom.h create mode 100644 board/starfive/visionfive2/visionfive2-i2c-eeprom.c create mode 100644 drivers/net/dwc_eth_qos_starfive.c create mode 100644 drivers/net/phy/motorcomm.c base-commit: 19b77d3d23966a0d6dbb3c86187765f11100fb6f -- 2.17.1

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