June 2023 - U-Boot

[PATCH v1] configs: verdin-imx8mp: enable ARCH_MISC_INIT
by Marcel Ziswiler 11 Jul '23

11 Jul '23

From: Sergio Prado <sergio.prado(a)toradex.com> This is required to boot a FIT image, otherwise the caam_jr driver is not initialized and the hash verification fails with the following error: Verifying Hash Integrity ... sha256dev_get_priv: null device CAAM was not setup properly or it is faulty Signed-off-by: Sergio Prado <sergio.prado(a)toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> --- configs/verdin-imx8mp_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index f0856aca9cc..97f4158ba63 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -42,6 +42,7 @@ CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx8mp-verdin-${variant}-${ CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 -- 2.36.1

2 1

[PATCH] board: gateworks: venice: add eraseenv command
by Tim Harvey 11 Jul '23

11 Jul '23

Add eraseenv command and remove the unnecessary env command. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- board/gateworks/venice/venice.env | 1 - configs/imx8mm_venice_defconfig | 1 + configs/imx8mn_venice_defconfig | 1 + configs/imx8mp_venice_defconfig | 1 + 4 files changed, 3 insertions(+), 1 deletion(-) diff --git a/board/gateworks/venice/venice.env b/board/gateworks/venice/venice.env index f81804ca12c1..2054c029a3e9 100644 --- a/board/gateworks/venice/venice.env +++ b/board/gateworks/venice/venice.env @@ -31,4 +31,3 @@ update_rootfs=tftpboot $loadaddr $image && gzwrite mmc $dev $loadaddr $filesize 100000 1000000 update_all=tftpboot $loadaddr $image && gzwrite mmc $dev $loadaddr $filesize -erase_env=mmc dev $dev; mmc erase 0x7f08 0x40 diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index a55e0cd76b54..ad5b7616f30a 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_PBSIZE=2074 CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 4709ecace65c..0742fa759b08 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_PBSIZE=2074 CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index 6b6a15588cd4..ae0c0120d107 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_PBSIZE=2074 CONFIG_SYS_BOOTM_LEN=0x10000000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y -- 2.25.1

3 2

[PATCH 1/5] arm: mxs: Provide Kconfig option to to not use VDD5V as IMX28 PMU source
by Lukasz Majewski 11 Jul '23

11 Jul '23

This option sets the current limit for 5V source to zero, so all the PMU outputs are primarily powered from battery source (DCDC_BAT). This option may be set on systems, where the 5V is NOT supposed to be in any scenario powering the system - for example on systems where DCDC_BAT is connected to fixed and regulated 4.2V source (so the "battery" is not present). Signed-off-by: Lukasz Majewski <lukma(a)denx.de> --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 4 ++++ arch/arm/mach-imx/mxs/Kconfig | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index c33170f06d..9965810ac2 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -752,6 +752,10 @@ static void mxs_batt_boot(void) POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); + if (CONFIG_IS_ENABLED(MXS_PMU_MINIMAL_VDD5V_CURRENT)) + setbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_ILIMIT_EQ_ZERO); + mxs_power_enable_4p2(); } diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index b2026a3758..3232b0fb67 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -51,6 +51,14 @@ endchoice config SYS_SOC default "mxs" +config SPL_MXS_PMU_MINIMAL_VDD5V_CURRENT + bool "Force minimal current draw from VDD5V by MX28 PMU" + default n + help + After setting this option, the current drawn from VDD5V + by the PMU is reduced to zero - the DCDC_BATT is used as + the main power source for PMU. + source "board/freescale/mx28evk/Kconfig" source "board/liebherr/xea/Kconfig" -- 2.30.2

4 17

[PATCH] configs: imx8m: Prepare imx8m-venice boards for HAB support
by Tim Harvey 11 Jul '23

11 Jul '23

In order to enable HAB, FSL_CAAM, ARCH_MISC_INIT and SPL_CRYPTO should be enabled in Kconfig like other i.MX8M boards. This also needs to occur in the SPL so enable CONFIG_SPL_BOARD_INIT and add a void spl_board_init function which calls arch_misc_init to probe the CAAM driver. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- arch/arm/mach-imx/imx8m/Kconfig | 9 +++++++++ board/gateworks/venice/spl.c | 5 +++++ configs/imx8mm_venice_defconfig | 1 + configs/imx8mn_venice_defconfig | 1 + configs/imx8mp_venice_defconfig | 1 + 5 files changed, 17 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 7639439bdc97..4244541a4a9d 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -124,6 +124,9 @@ config TARGET_IMX8MM_VENICE select IMX8M_LPDDR4 select GATEWORKS_SC select MISC + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_KONTRON_MX8MM bool "Kontron Electronics N80xx" @@ -175,6 +178,9 @@ config TARGET_IMX8MN_VENICE select IMX8M_LPDDR4 select GATEWORKS_SC select MISC + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_IMX8MP_DATA_MODUL_EDM_SBC bool "Data Modul eDM SBC i.MX8M Plus" @@ -232,6 +238,9 @@ config TARGET_IMX8MP_VENICE select IMX8M_LPDDR4 select GATEWORKS_SC select MISC + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_PICO_IMX8MQ bool "Support Technexion Pico iMX8MQ" diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 4eb7bdfcee67..50fdf7ead2cc 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -340,3 +340,8 @@ const char *spl_board_loader_name(u32 boot_device) return NULL; } } + +void spl_board_init(void) +{ + arch_misc_init(); +} diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 9d0d0ee315ed..03febee26023 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -36,6 +36,7 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SYS_SPL_MALLOC=y CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 3974a384d1e7..9104a75c0c65 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -38,6 +38,7 @@ CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x950000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SYS_SPL_MALLOC=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index a6f6ec67c523..cfc1dbd3cb17 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -38,6 +38,7 @@ CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x98fc00 CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SYS_SPL_MALLOC=y -- 2.25.1

3 2

[PATCH v2] mx8m: csf.sh: use vars for keys to avoid file edits when signing
by Tim Harvey 11 Jul '23

11 Jul '23

The csf_spl.txt and csf_fit.txt templates contain file paths which must be edited for the location of your NXP CST generated key files. Streamline the process of signing an image by assigning unique var names to these which can be expended from env variables in the csf.sh script. The following vars are used: SRK_TABLE - full path to SRK_1_2_3_4_table.bin CSF_KEY - full path to the CSF Key CSF1_1_sha256_4096_65537_v3_usr_crt.pem IMG_KEY - full path to the IMG Key IMG1_1_sha256_4096_65537_v3_usr_crt.pem Additionally provide an example of running the csf.sh script. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> Reviewed-by: Fabio Estevam <festevam(a)denx.de> --- v2: - fix typo: s/SKK_TABLE/SRK_TABLE - add Fabio's rb tag --- doc/imx/habv4/csf_examples/mx8m/csf.sh | 21 +++++++++++++++++++ doc/imx/habv4/csf_examples/mx8m/csf_fit.txt | 12 +++++------ doc/imx/habv4/csf_examples/mx8m/csf_spl.txt | 12 +++++------ doc/imx/habv4/guides/mx8m_spl_secure_boot.txt | 10 +++++++++ 4 files changed, 43 insertions(+), 12 deletions(-) diff --git a/doc/imx/habv4/csf_examples/mx8m/csf.sh b/doc/imx/habv4/csf_examples/mx8m/csf.sh index 7a9a05e63392..c4e610adf1c4 100644 --- a/doc/imx/habv4/csf_examples/mx8m/csf.sh +++ b/doc/imx/habv4/csf_examples/mx8m/csf.sh @@ -22,6 +22,27 @@ cp doc/imx/habv4/csf_examples/mx8m/csf_spl.txt csf_spl.tmp cp doc/imx/habv4/csf_examples/mx8m/csf_fit.txt csf_fit.tmp +# update File Paths from env vars +if ! [ -r $CSF_KEY ]; then + echo "Error: \$CSF_KEY not found" + exit 1 +fi +if ! [ -r $IMG_KEY ]; then + echo "Error: \$IMG_KEY not found" + exit 1 +fi +if ! [ -r $SRK_TABLE ]; then + echo "Error: \$SRK_TABLE not found" + exit 1 +fi +sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_spl.tmp +sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_spl.tmp +sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_spl.tmp +sed -i "s:\$CSF_KEY:$CSF_KEY:" csf_fit.tmp +sed -i "s:\$IMG_KEY:$IMG_KEY:" csf_fit.tmp +sed -i "s:\$SRK_TABLE:$SRK_TABLE:" csf_fit.tmp + +# update SPL Blocks spl_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SPL_TEXT_BASE=/ s@.*=@@p" .config) - 0x40)) ) spl_block_size=$(printf "0x%x" $(stat -tc %s u-boot-spl-ddr.bin)) sed -i "/Blocks = / s@.*@ Blocks = $spl_block_base 0x0 $spl_block_size \"flash.bin\"@" csf_spl.tmp diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt index cd1d4070a5e5..dfcfb777c248 100644 --- a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt +++ b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt @@ -7,21 +7,21 @@ Signature Format = CMS [Install SRK] - # FIXME: Adjust path here - File = "/path/to/cst-3.3.1/crts/SRK_1_2_3_4_table.bin" + # SRK_TABLE is full path to SRK_1_2_3_4_table.bin + File = "$SRK_TABLE" Source index = 0 [Install CSFK] - # FIXME: Adjust path here - File = "/path/to/cst-3.3.1/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem" + # CSF_KEY is full path to CSF1_1_sha256_4096_65537_v3_usr_crt.pem + File = "$CSF_KEY" [Authenticate CSF] [Install Key] Verification index = 0 Target Index = 2 - # FIXME: Adjust path here - File = "/path/to/cst-3.3.1/crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem" + # IMG_KEY is full path to IMG1_1_sha256_4096_65537_v3_usr_crt.pem + File = "$IMG_KEY" [Authenticate Data] Verification index = 2 diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt b/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt index 00e34f6b1b95..88fa420a5fa0 100644 --- a/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt +++ b/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt @@ -7,13 +7,13 @@ Signature Format = CMS [Install SRK] - # FIXME: Adjust path here - File = "/path/to/cst-3.3.1/crts/SRK_1_2_3_4_table.bin" + # SRK_TABLE is full path to SRK_1_2_3_4_table.bin + File = "$SRK_TABLE" Source index = 0 [Install CSFK] - # FIXME: Adjust path here - File = "/path/to/cst-3.3.1/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem" + # CSF_KEY is full path to CSF1_1_sha256_4096_65537_v3_usr_crt.pem + File = "$CSF_KEY" [Authenticate CSF] @@ -24,8 +24,8 @@ [Install Key] Verification index = 0 Target Index = 2 - # FIXME: Adjust path here - File = "/path/to/cst-3.3.1/crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem" + # IMG_KEY is full path to IMG1_1_sha256_4096_65537_v3_usr_crt.pem + File = "$IMG_KEY" [Authenticate Data] Verification index = 2 diff --git a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt index 3e3d38440f94..e789bae55940 100644 --- a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt +++ b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt @@ -251,6 +251,16 @@ dd if=csf_fit.bin of=flash.bin bs=1 seek=${csf_block_offset} conv=notrunc ``` The entire script is available in doc/imx/habv4/csf_examples/mx8m/csf.sh +and can be used as follows to modify flash.bin to be signed +(adjust paths as needed): +``` +export CST_DIR=/usr/src/cst-3.3.1/ +export CSF_KEY=$CST_DIR/crts/CSF1_1_sha256_4096_65537_v3_usr_crt.pem +export IMG_KEY=$CST_DIR/crts/IMG1_1_sha256_4096_65537_v3_usr_crt.pem +export SRK_TABLE=$CST_DIR/crts/SRK_1_2_3_4_table.bin +export PATH=$CST_DIR/linux64/bin:$PATH +/bin/sh doc/imx/habv4/csf_examples/mx8m/csf.sh +``` 1.4 Closing the device ----------------------- -- 2.25.1

3 2

[PATCH] arm: dts: imx8m: move CAAM nodes into common u-boot.dtsi
by Tim Harvey 11 Jul '23

11 Jul '23

Move the crypto and sec_jr* nodes from board-specific u-boot.dtsi files into the common files. Additionally protect the nodes with ifdef FSL_CAAM as they don't serve any purpose if that is not enabled. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- arch/arm/dts/imx8mm-evk-u-boot.dtsi | 16 --------------- .../dts/imx8mm-kontron-bl-common-u-boot.dtsi | 16 --------------- arch/arm/dts/imx8mm-u-boot.dtsi | 20 +++++++++++++++++++ arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 16 --------------- arch/arm/dts/imx8mn-u-boot.dtsi | 20 +++++++++++++++++++ arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi | 16 --------------- arch/arm/dts/imx8mp-evk-u-boot.dtsi | 16 --------------- .../imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi | 16 --------------- arch/arm/dts/imx8mp-u-boot.dtsi | 20 +++++++++++++++++++ .../dts/imx8mp-verdin-wifi-dev-u-boot.dtsi | 16 --------------- 10 files changed, 60 insertions(+), 112 deletions(-) diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index 155670da18d1..9a5b0795133b 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -65,22 +65,6 @@ bootph-pre-ram; }; -&crypto { - bootph-pre-ram; -}; - -&sec_jr0 { - bootph-pre-ram; -}; - -&sec_jr1 { - bootph-pre-ram; -}; - -&sec_jr2 { - bootph-pre-ram; -}; - &usbmisc1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi b/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi index 1ad9d49a1118..ae542fdcffad 100644 --- a/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi @@ -18,22 +18,6 @@ }; }; -&crypto { - bootph-pre-ram; -}; - -&sec_jr0 { - bootph-pre-ram; -}; - -&sec_jr1 { - bootph-pre-ram; -}; - -&sec_jr2 { - bootph-pre-ram; -}; - &i2c1 { bootph-pre-ram; bootph-all; diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index 61f907a4743b..303a43e63527 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -18,6 +18,12 @@ #endif }; +#ifdef FSL_CAAM +&crypto { + bootph-pre-ram; +}; +#endif + &soc { bootph-all; bootph-pre-ram; @@ -235,6 +241,20 @@ bootph-pre-ram; }; +#ifdef FSL_CAAM +&sec_jr0 { + bootph-pre-ram; +}; + +&sec_jr1 { + bootph-pre-ram; +}; + +&sec_jr2 { + bootph-pre-ram; +}; +#endif + &spba1 { bootph-all; bootph-pre-ram; diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 315714f39848..c31f3dec3de4 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -57,22 +57,6 @@ bootph-pre-ram; }; -&crypto { - bootph-pre-ram; -}; - -&sec_jr0 { - bootph-pre-ram; -}; - -&sec_jr1 { - bootph-pre-ram; -}; - -&sec_jr2 { - bootph-pre-ram; -}; - &usdhc1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index 15cec4ffab44..77b3097d5f52 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -54,6 +54,12 @@ /delete-property/ assigned-clock-rates; }; +#ifdef FSL_CAAM +&crypto { + bootph-pre-ram; +}; +#endif + &iomuxc { bootph-pre-ram; }; @@ -63,6 +69,20 @@ bootph-all; }; +#ifdef FSL_CAMM +&sec_jr0 { + bootph-pre-ram; +}; + +&sec_jr1 { + bootph-pre-ram; +}; + +&sec_jr2 { + bootph-pre-ram; +}; +#endif + &spba1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi index bb0f9bd0c8d3..82e90d743d08 100644 --- a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi @@ -21,10 +21,6 @@ bootph-pre-ram; }; -&crypto { - bootph-pre-ram; -}; - &eqos { /delete-property/ assigned-clocks; /delete-property/ assigned-clock-parents; @@ -131,18 +127,6 @@ u-boot,off-on-delay-us = <20000>; }; -&sec_jr0 { - bootph-pre-ram; -}; - -&sec_jr1 { - bootph-pre-ram; -}; - -&sec_jr2 { - bootph-pre-ram; -}; - &tpm { compatible = "tcg,tpm_tis-spi"; }; diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 17965c58ba10..6d9b229989ac 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -65,22 +65,6 @@ bootph-pre-ram; }; -&crypto { - bootph-pre-ram; -}; - -&sec_jr0 { - bootph-pre-ram; -}; - -&sec_jr1 { - bootph-pre-ram; -}; - -&sec_jr2 { - bootph-pre-ram; -}; - &i2c1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi index fe20938af536..cf2a87a9b903 100644 --- a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi @@ -62,22 +62,6 @@ bootph-pre-ram; }; -&crypto { - bootph-pre-ram; -}; - -&sec_jr0 { - bootph-pre-ram; -}; - -&sec_jr1 { - bootph-pre-ram; -}; - -&sec_jr2 { - bootph-pre-ram; -}; - &i2c1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index b46fc7eeed0d..1ba6b769341f 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -19,6 +19,12 @@ #endif }; +#ifdef FSL_CAAM +&crypto { + bootph-pre-ram; +}; +#endif + &soc { bootph-all; bootph-pre-ram; @@ -59,6 +65,20 @@ bootph-pre-ram; }; +#ifdef FSL_CAAM +&sec_jr0 { + bootph-pre-ram; +}; + +&sec_jr1 { + bootph-pre-ram; +}; + +&sec_jr2 { + bootph-pre-ram; +}; +#endif + &binman { u-boot-spl-ddr { filename = "u-boot-spl-ddr.bin"; diff --git a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi index a985645ff8c3..0ea194ba152c 100644 --- a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi @@ -28,10 +28,6 @@ }; -&crypto { - bootph-pre-ram; -}; - &gpio1 { bootph-pre-ram; }; @@ -132,18 +128,6 @@ bootph-pre-ram; }; -&sec_jr0 { - bootph-pre-ram; -}; - -&sec_jr1 { - bootph-pre-ram; -}; - -&sec_jr2 { - bootph-pre-ram; -}; - &uart3 { bootph-pre-ram; }; -- 2.25.1

4 3

[PATCH V2 1/2] imx: imx8mm-beacon: Enable FlexSPI in U-Boot
by Adam Ford 11 Jul '23

11 Jul '23

In order to use the FlexSPI interface in U-Boot, configure the alias to make spi0 point to flexspi. With that enabled, sf probe detects the QSPI part as: SF: Detected n25q256ax1 with page size 256 Bytes, erase size 4 KiB, total 32 MiB Signed-off-by: Adam Ford <aford173(a)gmail.com> --- V2: No Change diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi index 00ac413f36..4f5b9cd23c 100644 --- a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi @@ -6,6 +6,10 @@ #include "imx8mm-u-boot.dtsi" / { + aliases { + spi0 = &flexspi; + }; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; -- 2.34.1

2 3

[PATCH] board: gateworks: venice: add GPIO name lookup
by Tim Harvey 11 Jul '23

11 Jul '23

Add GPIO name lookup so that you can act on GPIO's by name vs controller id: Before: u-boot=> gpio input pci_wdis# GPIO: 'pci_wdis#' not found Command 'gpio' failed: Error -22 After: u-boot=> gpio input pci_wdis# gpio: pin pci_wdis# (gpio 103) value is 1 Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- configs/imx8mm_venice_defconfig | 1 + configs/imx8mn_venice_defconfig | 1 + configs/imx8mp_venice_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index db2da79ab109..a55e0cd76b54 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -88,6 +88,7 @@ CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y CONFIG_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_LED=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index e9cb26495075..4709ecace65c 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -89,6 +89,7 @@ CONFIG_SPL_DM=y CONFIG_SPL_CLK_IMX8MN=y CONFIG_CLK_IMX8MN=y CONFIG_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_LED=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index 4d0432078d56..6b6a15588cd4 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -86,6 +86,7 @@ CONFIG_SPL_DM=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y CONFIG_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_LED=y -- 2.25.1

3 2

[PATCH] board: gateworks: venice: add imx8mp-gw7905-2x support
by Tim Harvey 11 Jul '23

11 Jul '23

The Gateworks imx8mp-venice-gw7905-2x consists of a SOM + baseboard. The GW702x SOM contains the following: - i.MX8M Plus SoC - LPDDR4 memory - eMMC Boot device - Gateworks System Controller (GSC) with integrated EEPROM, button controller, and ADC's - PMIC - SOM connector providing: - eQoS GbE MII - 1x SPI - 2x I2C - 4x UART - 2x USB 3.0 - 1x PCI - 1x SDIO (4-bit 3.3V) - 1x SDIO (4-bit 3.3V/1.8V) - GPIO The GW7905 Baseboard contains the following: - GPS - microSD - off-board I/O connector with I2C, SPI, GPIO - EERPOM - PCIe clock generator - 1x full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0 - 1x half-length miniPCIe socket with USB2.0 and USB3.0 - USB 3.0 HUB - USB Type-C with USB PD Sink capability and peripheral support - USB Type-C with USB 3.0 host support Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi | 12 + arch/arm/dts/imx8mp-venice-gw702x.dtsi | 587 ++++++++++++++++++ .../dts/imx8mp-venice-gw7905-2x-u-boot.dtsi | 51 ++ arch/arm/dts/imx8mp-venice-gw7905-2x.dts | 28 + arch/arm/dts/imx8mp-venice-gw7905.dtsi | 309 +++++++++ board/gateworks/venice/eeprom.c | 5 + board/gateworks/venice/lpddr4_timing.h | 1 + board/gateworks/venice/lpddr4_timing_imx8mp.c | 532 ++++++++++++++++ board/gateworks/venice/spl.c | 19 +- configs/imx8mp_venice_defconfig | 2 +- 11 files changed, 1544 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-venice-gw702x.dtsi create mode 100644 arch/arm/dts/imx8mp-venice-gw7905-2x-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-venice-gw7905-2x.dts create mode 100644 arch/arm/dts/imx8mp-venice-gw7905.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 480269fa6065..909a4d23f4a7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1016,6 +1016,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-phyboard-pollux-rdk.dtb \ imx8mp-venice.dtb \ imx8mp-venice-gw74xx.dtb \ + imx8mp-venice-gw7905-2x.dtb \ imx8mp-verdin-wifi-dev.dtb \ imx8mq-pico-pi.dtb \ imx8mq-kontron-pitx-imx8m.dtb \ diff --git a/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi new file mode 100644 index 000000000000..b9e3db7de937 --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw702x-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 Gateworks Corporation + */ + +#include "imx8mp-venice-u-boot.dtsi" + +&eqos { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw702x.dtsi b/arch/arm/dts/imx8mp-venice-gw702x.dtsi new file mode 100644 index 000000000000..560c68e4da6d --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw702x.dtsi @@ -0,0 +1,587 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/net/ti-dp83867.h> + +/ { + aliases { + ethernet0 = &eqos; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-user-pb { + label = "user_pb"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + + key-user-pb1x { + label = "user_pb1x"; + linux,code = <BTN_1>; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key_erased"; + linux,code = <BTN_2>; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + key-eeprom-wp { + label = "eeprom_wp"; + linux,code = <BTN_3>; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + key-tamper { + label = "tamper"; + linux,code = <BTN_4>; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = <BTN_5>; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck3_reg>; +}; + +&A53_1 { + cpu-supply = <&buck3_reg>; +}; + +&A53_2 { + cpu-supply = <&buck3_reg>; +}; + +&A53_3 { + cpu-supply = <&buck3_reg>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <&ethphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + pinctrl-0 = <&pinctrl_ethphy0>; + pinctrl-names = "default"; + reg = <0x0>; + interrupt-parent = <&gpio3>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + pinctrl-0 = <&pinctrl_gsc>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <3>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@16 { + gw,mode = <4>; + reg = <0x16>; + label = "fan_tach"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vdd_vin"; + gw,voltage-divider-ohms = <22100 1000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vdd_adc1"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_adc2"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_1p0"; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_1p8"; + }; + + channel@8e { + gw,mode = <2>; + reg = <0x8e>; + label = "vdd_2p5"; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_dram"; + }; + + channel@98 { + gw,mode = <2>; + reg = <0x98>; + label = "vdd_soc"; + }; + + channel@9a { + gw,mode = <2>; + reg = <0x9a>; + label = "vdd_arm"; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + + fan-controller@0 { + compatible = "gw,gsc-fan"; + reg = <0x0a>; + }; + }; + + gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; + + pmic@69 { + compatible = "mps,mp5416"; + reg = <0x69>; + + regulators { + /* vdd_soc */ + buck1 { + regulator-name = "buck1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* vdd_dram */ + buck2 { + regulator-name = "buck2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + /* vdd_arm */ + buck3_reg: buck3 { + regulator-name = "buck3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* vdd_1p8 */ + buck4 { + regulator-name = "buck4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* OUT2: nvcc_snvs_1p8 */ + ldo1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* OUT3: vdd_1p0 */ + ldo2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* OUT4: vdd_2p5 */ + ldo3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + regulator-boot-on; + }; + + /* OUT5: vdd_3p3 */ + ldo4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +/* off-board header */ +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + eeprom@52 { + compatible = "atmel,24c32"; + reg = <0x52>; + pagesize = <32>; + }; +}; + +/* off-board header */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +/* off-board header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* off-board header */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* off-board */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + non-removable; + status = "okay"; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + >; + }; + + pinctrl_ethphy0: ethphy0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x140 /* RST# */ + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x150 /* IRQ# */ + >; + }; + + pinctrl_gsc: gscgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x150 /* IRQ# */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw7905-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw7905-2x-u-boot.dtsi new file mode 100644 index 000000000000..981841cee0a9 --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw7905-2x-u-boot.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 Gateworks Corporation + */ +#include "imx8mp-venice-gw702x-u-boot.dtsi" + +&gpio1 { + app_gpioa { + gpio-hog; + input; + gpios = <13 GPIO_ACTIVE_HIGH>; + line-name = "gpioa"; + }; +}; + +&gpio4 { + app_gpiod { + gpio-hog; + input; + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "gpiod"; + }; + + app_gpiob { + gpio-hog; + input; + gpios = <4 GPIO_ACTIVE_HIGH>; + line-name = "gpiob"; + }; + + app_gpioc { + gpio-hog; + input; + gpios = <5 GPIO_ACTIVE_HIGH>; + line-name = "gpioc"; + }; + + pci_usb_sel { + gpio-hog; + output-low; + gpios = <26 GPIO_ACTIVE_HIGH>; + line-name = "pci_usb_sel"; + }; + + pci_wdis { + gpio-hog; + output-high; + gpios = <28 GPIO_ACTIVE_HIGH>; + line-name = "pci_wdis#"; + }; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw7905-2x.dts b/arch/arm/dts/imx8mp-venice-gw7905-2x.dts new file mode 100644 index 000000000000..4a1bbbbe19e6 --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw7905-2x.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx8mp.dtsi" +#include "imx8mp-venice-gw702x.dtsi" +#include "imx8mp-venice-gw7905.dtsi" + +/ { + model = "Gateworks Venice GW7905-2x i.MX8MP Development Kit"; + compatible = "gateworks,imx8mp-gw7905-2x", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; +}; + +/* Disable SOM interfaces not used on baseboard */ +&eqos { + status = "disabled"; +}; + +&usdhc1 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw7905.dtsi b/arch/arm/dts/imx8mp-venice-gw7905.dtsi new file mode 100644 index 000000000000..0d40cb0f05f6 --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw7905.dtsi @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> + +/ { + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_en>; + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus"; + gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + compatible = "regulator-fixed"; + regulator-name = "SD2_3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "gpioa", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "gpiod", "", "", + "gpiob", "gpioc", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "pci_usb_sel", "", + "pci_wdis#", "", "", ""; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@52 { + compatible = "atmel,24c32"; + reg = <0x52>; + pagesize = <32>; + }; +}; + +/* off-board header */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pcie_phy { + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* GPS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* USB1 - Type C front panel SINK port J14 */ +&usb3_0 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +/* USB2 4-port USB3.0 HUB: + * P1 - USBC connector (host only) + * P2 - USB2 test connector + * P3 - miniPCIe full card + * P4 - miniPCIe half card + */ +&usb3_phy1 { + vbus-supply = <&reg_usb2_vbus>; + status = "okay"; +}; + +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <&reg_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40000040 /* GPIOA */ + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000040 /* GPIOD */ + MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x40000040 /* GPIOB */ + MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x40000040 /* GPIOC */ + MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000106 /* PCI_USBSEL */ + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCI_WDIS# */ + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */ + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x6 /* LEDR */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_pcie0: pciegrp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106 + >; + }; + + pinctrl_reg_usb2_en: regusb2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x6 /* USBHUB_RST# (ext p/u) */ + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; +}; diff --git a/board/gateworks/venice/eeprom.c b/board/gateworks/venice/eeprom.c index 6aea60ad05c7..241be4ee630b 100644 --- a/board/gateworks/venice/eeprom.c +++ b/board/gateworks/venice/eeprom.c @@ -218,6 +218,11 @@ const char *eeprom_get_dtb_name(int level, char *buf, int sz) int rev_base_bom = get_bom_rev(base_info.model); snprintf(buf, sz, "%s%2dxx-%dx", pre, base, som); + /* GW79xx baseboards have no build options */ + if (base == 79) { + base = (int)strtoul(base_info.model + 2, NULL, 10); + snprintf(buf, sz, "%s%4d-%dx", pre, base, som); + } switch (level) { case 0: /* full model (ie gw73xx-0x-a1a1) */ if (rev_base_bom) diff --git a/board/gateworks/venice/lpddr4_timing.h b/board/gateworks/venice/lpddr4_timing.h index 62b860610c5a..d19902f10ec3 100644 --- a/board/gateworks/venice/lpddr4_timing.h +++ b/board/gateworks/venice/lpddr4_timing.h @@ -16,6 +16,7 @@ extern struct dram_timing_info dram_timing_1gb_single_die; extern struct dram_timing_info dram_timing_2gb_single_die; extern struct dram_timing_info dram_timing_2gb_dual_die; #elif CONFIG_IMX8MP +extern struct dram_timing_info dram_timing_1gb_single_die; extern struct dram_timing_info dram_timing_4gb_dual_die; #endif diff --git a/board/gateworks/venice/lpddr4_timing_imx8mp.c b/board/gateworks/venice/lpddr4_timing_imx8mp.c index 2e96332f8b5f..7bfd1b556bb3 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mp.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mp.c @@ -1314,6 +1314,538 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0xd0000, 0x1 } }; +/* + * Generated code from MX8M_DDR_tool v3.30 using MX8MP Plus RPAv9 + * - 1GiB: ixm8mp-gw7020 1x Micron MT53E256M32D2DS 2-ch single-die per channel + */ +struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x1203 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b0087 }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x402 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0x8d }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0x699 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, + { 0x3d400208, 0x0 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0xf070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1001 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc0012 }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x302 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x13 }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0x599 }, + { 0x3d403020, 0x1001 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30005 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x302 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x5 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0x599 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x3 }, + { 0x100a3, 0x2 }, + { 0x100a4, 0x5 }, + { 0x100a5, 0x4 }, + { 0x100a6, 0x7 }, + { 0x100a7, 0x6 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x2 }, + { 0x110a3, 0x3 }, + { 0x110a4, 0x4 }, + { 0x110a5, 0x5 }, + { 0x110a6, 0x6 }, + { 0x110a7, 0x7 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x2 }, + { 0x120a3, 0x3 }, + { 0x120a4, 0x4 }, + { 0x120a5, 0x5 }, + { 0x120a6, 0x6 }, + { 0x120a7, 0x7 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x3 }, + { 0x130a3, 0x4 }, + { 0x130a4, 0x5 }, + { 0x130a5, 0x2 }, + { 0x130a6, 0x7 }, + { 0x130a7, 0x6 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg_1gb_single_die[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg_1gb_single_die[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg_1gb_single_die[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg_1gb_single_die, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_1gb_single_die), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg_1gb_single_die, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg_1gb_single_die), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg_1gb_single_die, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_1gb_single_die), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg_1gb_single_die, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_1gb_single_die), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_1gb_single_die = { + .ddrc_cfg = ddr_ddrc_cfg_1gb_single_die, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_1gb_single_die), + .ddrphy_cfg = ddr_ddrphy_cfg_1gb_single_die, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg_1gb_single_die), + .fsp_msg = ddr_dram_fsp_msg_1gb_single_die, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg_1gb_single_die), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; + /* * Generated code from MX8M_DDR_tool v3.30 using MX8M Plus RPAv7 * - 4GiB: imx8mp-gw7401 1x Micron MT53D1024M32D4DT 2-ch dual-die per channel diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index c81498e830d6..606738a8c97c 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -71,6 +71,9 @@ static void spl_dram_init(int size) dram_timing = &dram_timing_2gb_dual_die; size = 2048; #elif CONFIG_IMX8MP + case 1024: + dram_timing = &dram_timing_1gb_single_die; + break; case 4096: dram_timing = &dram_timing_4gb_dual_die; break; @@ -124,7 +127,8 @@ static int power_init_board(void) if ((!strncmp(model, "GW71", 4)) || (!strncmp(model, "GW72", 4)) || - (!strncmp(model, "GW73", 4))) { + (!strncmp(model, "GW73", 4)) || + (!strncmp(model, "GW7905", 6))) { ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); if (ret) { printf("PMIC : failed I2C1 probe: %d\n", ret); @@ -135,11 +139,22 @@ static int power_init_board(void) printf("PMIC : failed probe: %d\n", ret); return ret; } - puts("PMIC : MP5416\n"); +#ifdef CONFIG_IMX8MM + puts("PMIC : MP5416 (IMX8MM)\n"); /* set VDD_ARM SW3 to 0.92V for 1.6GHz */ dm_i2c_reg_write(dev, MP5416_VSET_SW3, BIT(7) | MP5416_VSET_SW3_SVAL(920000)); +#elif CONFIG_IMX8MP + puts("PMIC : MP5416 (IMX8MP)\n"); + + /* set VDD_ARM SW3 to 0.95V for 1.6GHz */ + dm_i2c_reg_write(dev, MP5416_VSET_SW3, + BIT(7) | MP5416_VSET_SW3_SVAL(950000)); + /* set VDD_SOC SW1 to 0.95V for 1.6GHz */ + dm_i2c_reg_write(dev, MP5416_VSET_SW1, + BIT(7) | MP5416_VSET_SW1_SVAL(950000)); +#endif } else if (!strncmp(model, "GW74", 4)) { diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index f9065e7bf09d..ee4b84db1914 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -76,7 +76,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="imx8mp-venice imx8mp-venice-gw74xx" +CONFIG_OF_LIST="imx8mp-venice imx8mp-venice-gw74xx imx8mp-venice-gw7905-2x" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_MMC_ENV_DEV=2 -- 2.25.1

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[PATCH] arm: mx6: module_fuse: fix build failure due to wrong argument name
by Giulio Benetti 11 Jul '23

11 Jul '23

nodeoff variable should be variable off returned by fdt_path_offset() so let's rename it to off. Signed-off-by: Giulio Benetti <giulio.benetti(a)benettiengineering.com> --- arch/arm/mach-imx/mx6/module_fuse.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mx6/module_fuse.c b/arch/arm/mach-imx/mx6/module_fuse.c index 0f4565e311..b58f11c1e5 100644 --- a/arch/arm/mach-imx/mx6/module_fuse.c +++ b/arch/arm/mach-imx/mx6/module_fuse.c @@ -206,7 +206,7 @@ int ft_system_setup(void *blob, struct bd_info *bd) if (off < 0) continue; /* Not found, skip it */ add_status: - rc = fdt_setprop(blob, nodeoff, "status", status, + rc = fdt_setprop(blob, off, "status", status, strlen(status) + 1); if (rc) { if (rc == -FDT_ERR_NOSPACE) { -- 2.34.1

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