May 2023 - U-Boot

How to debug u-boot data abort
by qianfan 22 Jul '23

22 Jul '23

Hi: I had a custom AM335X board connected my computer by usbnet. It always report data abort when 'dhcp': Next it the log: U-Boot 2022.01-rc1-00183-gfa5b4e2d19-dirty (Feb 25 2022 - 15:45:02 +0800) CPU : AM335X-GP rev 2.1 Model: WISDOM AM335X CCT DRAM: 512 MiB NAND: 256 MiB MMC: OMAP SD/MMC: 0 Loading Environment from NAND... *** Warning - bad CRC, using default environment Net: Could not get PHY for ethernet@4a100000: addr 0 eth2: ethernet@4a100000, eth3: usb_ether Hit any key to stop autoboot: 0 => setenv autoload no => dhcp using musb-hdrc, OUT ep1out IN ep1in STATUS ep2in MAC de:ad:be:ef:00:01 HOST MAC de:ad:be:ef:00:00 RNDIS ready musb-hdrc: peripheral reset irq lost! high speed config #2: 2 mA, Ethernet Gadget, using RNDIS USB RNDIS network up! BOOTP broadcast 1 BOOTP broadcast 2 BOOTP broadcast 3 DHCP client bound to address 192.168.200.4 (757 ms) data abort pc : [<9fe9b0a2>] lr : [<9febbc3f>] reloc pc : [<808130a2>] lr : [<80833c3f>] sp : 9de53410 ip : 9de53578 fp : 00000001 r10: 9de5345c r9 : 9de67e80 r8 : 9febbae5 r7 : 9de72c30 r6 : 9feec710 r5 : 0000000d r4 : 00000018 r3 : 3fdd8e04 r2 : 00000002 r1 : 9feec728 r0 : 9feec700 Flags: Nzcv IRQs off FIQs on Mode SVC_32 (T) Code: f023 0303 60ca 4403 (6091) 685a Resetting CPU ... resetting ... It's there has any doc about how to debug data abort? Or is the bug is already fixed? Thanks

7 22

[u-boot-test-hooks PATCH 1/1] qemu_arm64_na: enable semihosting
by Heinrich Schuchardt 21 Jul '23

21 Jul '23

For testing semihosting we need to pass parameter -semihosting. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- bin/travis-ci/conf.qemu_arm64_na | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/travis-ci/conf.qemu_arm64_na b/bin/travis-ci/conf.qemu_arm64_na index 14577d8..e195b5e 100644 --- a/bin/travis-ci/conf.qemu_arm64_na +++ b/bin/travis-ci/conf.qemu_arm64_na @@ -24,7 +24,7 @@ console_impl=qemu qemu_machine="virt" qemu_helper_script="swtpm" qemu_binary="qemu-system-aarch64" -qemu_extra_args="-cpu cortex-a57 -nographic -netdev user,id=net0,tftp=${UBOOT_TRAVIS_BUILD_DIR} -device e1000,netdev=net0 -device virtio-rng-pci -chardev socket,id=chrtpm,path=/tmp/tpm/swtpm-sock -tpmdev emulator,id=tpm0,chardev=chrtpm -device tpm-tis-device,tpmdev=tpm0" +qemu_extra_args="-cpu cortex-a57 -nographic -netdev user,id=net0,tftp=${UBOOT_TRAVIS_BUILD_DIR} -device e1000,netdev=net0 -device virtio-rng-pci -semihosting -chardev socket,id=chrtpm,path=/tmp/tpm/swtpm-sock -tpmdev emulator,id=tpm0,chardev=chrtpm -device tpm-tis-device,tpmdev=tpm0" qemu_kernel_args="-bios ${U_BOOT_BUILD_DIR}/u-boot.bin" reset_impl=none flash_impl=none -- 2.39.2

2 1

[PATCH 1/2] net: rtl8169: add minimal support for 8125B variant
by Eugen Hristev 21 Jul '23

21 Jul '23

Add minimal support for 8125B version. Changes are based on the Linux driver. Tested on Radxa Rock 5B Rk3588 board. Connection to a laptop worked fine in 100 Mbps mode. 1000 Mbps mode is not working at the moment. Signed-off-by: Eugen Hristev <eugen.hristev(a)collabora.com> --- drivers/net/rtl8169.c | 52 ++++++++++++++++++++++++++++++------------- 1 file changed, 37 insertions(+), 15 deletions(-) diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index c9c07a5a8ffe..2276a465e787 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -118,9 +118,9 @@ enum RTL8169_registers { FLASH = 0x30, ERSR = 0x36, ChipCmd = 0x37, - TxPoll = 0x38, - IntrMask = 0x3C, - IntrStatus = 0x3E, + TxPoll_8169 = 0x38, + IntrMask_8169 = 0x3C, + IntrStatus_8169 = 0x3E, TxConfig = 0x40, RxConfig = 0x44, RxMissed = 0x4C, @@ -148,6 +148,12 @@ enum RTL8169_registers { FuncForceEvent = 0xFC, }; +enum RTL8125_registers { + IntrMask_8125 = 0x38, + IntrStatus_8125 = 0x3C, + TxPoll_8125 = 0x90, +}; + enum RTL8169_register_content { /*InterruptStatusBits */ SYSErr = 0x8000, @@ -263,6 +269,7 @@ static struct { {"RTL-8101e", 0x34, 0xff7e1880,}, {"RTL-8100e", 0x32, 0xff7e1880,}, {"RTL-8168h/8111h", 0x54, 0xff7e1880,}, + {"RTL-8125B", 0x64, 0xff7e1880,}, }; enum _DescStatusBit { @@ -347,6 +354,7 @@ static struct pci_device_id supported[] = { { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) }, { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) }, { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) }, + { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8125) }, {} }; @@ -517,6 +525,7 @@ static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase, /* return true if there's an ethernet packet ready to read */ /* nic->packet should contain data on return */ /* nic->packetlen should contain length of data */ + struct pci_child_plat *pplat = dev_get_parent_plat(dev); int cur_rx; int length = 0; @@ -558,6 +567,10 @@ static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase, return length; } else { + u32 IntrStatus = IntrStatus_8169; + + if (pplat->device == 0x8125) + IntrStatus = IntrStatus_8125; ushort sts = RTL_R8(IntrStatus); RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); udelay(100); /* wait */ @@ -582,6 +595,7 @@ static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase, { /* send the packet to destination */ + struct pci_child_plat *pplat = dev_get_parent_plat(dev); u32 to; u8 *ptxb; int entry = tpc->cur_tx % NUM_TX_DESC; @@ -618,7 +632,10 @@ static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase, ((len > ETH_ZLEN) ? len : ETH_ZLEN)); } rtl_flush_tx_desc(&tpc->TxDescArray[entry]); - RTL_W8(TxPoll, 0x40); /* set polling bit */ + if (pplat->device == 0x8125) + RTL_W8(TxPoll_8125, 0x1); /* set polling bit */ + else + RTL_W8(TxPoll_8169, 0x40); /* set polling bit */ tpc->cur_tx++; to = currticks() + TX_TIMEOUT; @@ -824,21 +841,26 @@ static int rtl8169_eth_start(struct udevice *dev) return 0; } -static void rtl_halt_common(unsigned long dev_iobase) +static void rtl_halt_common(struct udevice *dev) { + struct rtl8169_private *priv = dev_get_priv(dev); + struct pci_child_plat *pplat = dev_get_parent_plat(dev); int i; #ifdef DEBUG_RTL8169 printf ("%s\n", __FUNCTION__); #endif - ioaddr = dev_iobase; + ioaddr = priv->iobase; /* Stop the chip's Tx and Rx DMA processes. */ RTL_W8(ChipCmd, 0x00); /* Disable interrupts by clearing the interrupt mask. */ - RTL_W16(IntrMask, 0x0000); + if (pplat->device == 0x8125) + RTL_W16(IntrMask_8125, 0x0000); + else + RTL_W16(IntrMask_8169, 0x0000); RTL_W32(RxMissed, 0); @@ -849,9 +871,7 @@ static void rtl_halt_common(unsigned long dev_iobase) void rtl8169_eth_stop(struct udevice *dev) { - struct rtl8169_private *priv = dev_get_priv(dev); - - rtl_halt_common(priv->iobase); + rtl_halt_common(dev); } static int rtl8169_write_hwaddr(struct udevice *dev) @@ -1025,23 +1045,25 @@ static int rtl8169_eth_probe(struct udevice *dev) struct pci_child_plat *pplat = dev_get_parent_plat(dev); struct rtl8169_private *priv = dev_get_priv(dev); struct eth_pdata *plat = dev_get_plat(dev); - u32 iobase; int region; int ret; - debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); switch (pplat->device) { case 0x8168: + case 0x8125: region = 2; break; default: region = 1; break; } - dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0 + region * 4, &iobase); - iobase &= ~0xf; - priv->iobase = (int)dm_pci_mem_to_phys(dev, iobase); + priv->iobase = (ulong)dm_pci_map_bar(dev, + PCI_BASE_ADDRESS_0 + region * 4, + 0, 0, + PCI_REGION_TYPE, PCI_REGION_MEM); + + debug("rtl8169: REALTEK RTL8169 @0x%lx\n", priv->iobase); ret = rtl_init(priv->iobase, dev->name, plat->enetaddr); if (ret < 0) { printf(pr_fmt("failed to initialize card: %d\n"), ret); -- 2.34.1

4 15

[PATCH] travis-ci: Add m68k M5208EVBE machine
by Marek Vasut 20 Jul '23

20 Jul '23

Add m68k M5208EVBE machine configured to test U-Boot m68k support. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- Cc: Angelo Dureghello <angelo(a)kernel-space.org> Cc: Stephen Warren <swarren(a)nvidia.com> Cc: Tom Rini <trini(a)konsulko.com> --- bin/travis-ci/conf.M5208EVBE_qemu | 27 +++++++++++++++++++ .../u_boot_boardenv_M5208EVBE_qemu.py | 6 +++++ 2 files changed, 33 insertions(+) create mode 100644 bin/travis-ci/conf.M5208EVBE_qemu create mode 100644 py/travis-ci/u_boot_boardenv_M5208EVBE_qemu.py diff --git a/bin/travis-ci/conf.M5208EVBE_qemu b/bin/travis-ci/conf.M5208EVBE_qemu new file mode 100644 index 0000000..947f13c --- /dev/null +++ b/bin/travis-ci/conf.M5208EVBE_qemu @@ -0,0 +1,27 @@ +# Copyright (c) 2023 Marek Vasut <marek.vasut+renesas(a)mailbox.org> +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +console_impl=qemu +qemu_machine="mcf5208evb" +qemu_binary="qemu-system-m68k" +qemu_extra_args="-nographic -serial mon:stdio -net user,tftp=${UBOOT_TRAVIS_BUILD_DIR} -net nic,model=mcf-fec" +qemu_kernel_args="-bios ${U_BOOT_BUILD_DIR}/u-boot.bin" +reset_impl=none +flash_impl=none diff --git a/py/travis-ci/u_boot_boardenv_M5208EVBE_qemu.py b/py/travis-ci/u_boot_boardenv_M5208EVBE_qemu.py new file mode 100644 index 0000000..4e100cd --- /dev/null +++ b/py/travis-ci/u_boot_boardenv_M5208EVBE_qemu.py @@ -0,0 +1,6 @@ +import os +import travis_tftp + +env__net_uses_pci = False +env__net_dhcp_server = True +env__net_tftp_readable_file = travis_tftp.file2env('u-boot') -- 2.39.2

4 7

[BUG] efi_loader: incorrect creation of device paths
by Heinrich Schuchardt 19 Jul '23

19 Jul '23

Hello Takahiro, in a prior mail we have discussed the creation of device paths for USB mass storage devices. On the sand boxyou get the following devices after 'usb start': Class Index Probed Driver Name ----------------------------------------------------------- usb 0 [ + ] usb_sandbox |-- usb@1 usb_hub 0 [ + ] usb_hub | `-- hub usb_mass_s 0 [ + ] usb_mass_storage | |-- usb_mass_storage blk 3 [ ] usb_storage_blk | | `-- usb_mass_storage.lun0 usb_mass_s 1 [ + ] usb_mass_storage | |-- usb_mass_storage blk 4 [ ] usb_storage_blk | | `-- usb_mass_storage.lun0 usb_mass_s 2 [ + ] usb_mass_storage | `-- usb_mass_storage blk 5 [ ] usb_storage_blk | `-- usb_mass_storage.lun0 For of these storage devices we try to create the same device path which is not allowable: => usb start starting USB... Bus usb@1: scanning bus usb@1 for devices... 5 USB Device(s) found scanning usb for storage devices... 3 Storage Device(s) found => => efidebug dh Scanning disk mmc2.blk... handle 0000000015e34f00, /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)/SD(2)/SD(0) Scanning disk mmc1.blk... handle 0000000015e36b30, /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)/SD(1)/SD(1) Scanning disk mmc0.blk... handle 0000000015e35b00, /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)/SD(0)/SD(2) Scanning disk usb_mass_storage.lun0... handle 0000000015e35c10, /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)/UsbClass(0x1234,0x5678,0x9,0x0,0x0)/UsbClass(0x1234,0x5678,0x0,0x0,0x0) fs_devread read outside partition 2 Failed to mount ext2 filesystem... BTRFS: superblock end 69632 is larger than device size 512 Scanning disk usb_mass_storage.lun0... handle 0000000015e361f0, /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)/UsbClass(0x1234,0x5678,0x9,0x0,0x0)/UsbClass(0x1234,0x5678,0x0,0x0,0x0) ERROR: failure to add disk device usb_mass_storage.lun0, r = 20 Error: Cannot initialize UEFI sub-system, r = 20 I will provide a patch that will allow the first USB device to be used and avoids stopping the boot process. But we really have to walk the dm tree to create a device patch for USB devices based on port IDs. We should add a new field to struct uclass_driver: struct efi_device_path *get_node(udevice *dev); This function shall return a pointer to an freshly allocated buffer with the device node for the device. To build the devicepath we can then walk the dm tree. To make migration easier: If the function pointer or the return value is NULL we can create a CTRL() node as dummy using the uclass_id and the device number. Best regards Heinrich

3 8

[PATCH 1/5] imx: imx8mm-beacon: Move environment definition to env file
by Adam Ford 17 Jul '23

17 Jul '23

Instead of cluttering up a header file with a bunch of defines, move the default environmental variables to a file called imx8mm_beacon.env and reference it from the defconfig. Signed-off-by: Adam Ford <aford173(a)gmail.com> --- board/beacon/imx8mm/imx8mm_beacon.env | 19 ++++++++++ configs/imx8mm_beacon_defconfig | 1 + include/configs/imx8mm_beacon.h | 50 --------------------------- 3 files changed, 20 insertions(+), 50 deletions(-) create mode 100644 board/beacon/imx8mm/imx8mm_beacon.env diff --git a/board/beacon/imx8mm/imx8mm_beacon.env b/board/beacon/imx8mm/imx8mm_beacon.env new file mode 100644 index 0000000000..00bf67edd5 --- /dev/null +++ b/board/beacon/imx8mm/imx8mm_beacon.env @@ -0,0 +1,19 @@ +boot_fit=try +bootscript=echo Running bootscript from mmc ...; source +console=ttymxc1 +fdt_addr=0x45000000 +fdt_file=imx8mm-beacon-kit.dtb +finduuid=part uuid mmc ${mmcdev}:2 uuid +image=Image +initrd_addr=0x46000000 +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +mmcargs=setenv bootargs console=${console},${baudrate} root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs} +mmcautodetect=yes +mmcboot=echo Booting from mmc ...; run finduuid; run mmcargs; if run loadfdt; then booti ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +mmcdev=1 +mmcpart=1 +netboot=echo Booting from net ...; run netargs; if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; ${get_cmd} ${loadaddr} ${image}; if test ${boot_fit} = yes || test ${boot_fit} = try; then bootm ${loadaddr}; else if ${get_cmd} ${fdt_addr} ${fdt_file}; then booti ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi; fi; +script=boot.scr diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 597fe256d0..c049db32c1 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SOURCE_FILE="imx8mm_beacon" CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index d85ae21e23..c8dab91f61 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -19,56 +19,6 @@ #endif -/* Initial environment variables */ -#define CFG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=Image\0" \ - "console=ttymxc1,115200\0" \ - "fdt_addr=0x43000000\0" \ - "boot_fit=try\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "initrd_addr=0x43800000\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate}" \ - " root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \ - "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \ - " ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ - "run mmcargs; " \ - "if run loadfdt; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "netargs=setenv bootargs console=${console} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${loadaddr} ${image}; " \ - "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ - "bootm ${loadaddr}; " \ - "else " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi;\0" - /* Link Definitions */ #define CFG_SYS_INIT_RAM_ADDR 0x40000000 -- 2.39.2

3 12

[PATCH] video: rockchip: Add support for RK3399 to dw-mipi-dsi bridge
by Ondřej Jirman 17 Jul '23

17 Jul '23

From: Ondrej Jirman <megi(a)xff.cz> This just needs some extra clocks enabled, and different registers configured. Copied from Linux, just like the original submitter of this driver did for rk3568. Tested on Pinephone Pro. Signed-off-by: Ondrej Jirman <megi(a)xff.cz> Cc: Anatolij Gustschin <agust(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Philipp Tomsich <philipp.tomsich(a)vrull.eu> Cc: Kever Yang <kever.yang(a)rock-chips.com> Cc: Chris Morgan <macromorgan(a)hotmail.com> --- drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 99 +++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c index 1bb1c7c67d07..9ec3a48bf2a5 100644 --- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c +++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c @@ -134,6 +134,32 @@ #define HS_RX_CONTROL_OF_LANE_2 0x84 #define HS_RX_CONTROL_OF_LANE_3 0x94 +#define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) +#define DW_MIPI_NEEDS_GRF_CLK BIT(1) + +#define RK3399_GRF_SOC_CON20 0x6250 +#define RK3399_DSI0_LCDC_SEL BIT(0) +#define RK3399_DSI1_LCDC_SEL BIT(4) + +#define RK3399_GRF_SOC_CON22 0x6258 +#define RK3399_DSI0_TURNREQUEST (0xf << 12) +#define RK3399_DSI0_TURNDISABLE (0xf << 8) +#define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4) +#define RK3399_DSI0_FORCERXMODE (0xf << 0) + +#define RK3399_GRF_SOC_CON23 0x625c +#define RK3399_DSI1_TURNDISABLE (0xf << 12) +#define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8) +#define RK3399_DSI1_FORCERXMODE (0xf << 4) +#define RK3399_DSI1_ENABLE (0xf << 0) + +#define RK3399_GRF_SOC_CON24 0x6260 +#define RK3399_TXRX_MASTERSLAVEZ BIT(7) +#define RK3399_TXRX_ENABLECLK BIT(6) +#define RK3399_TXRX_BASEDIR BIT(5) +#define RK3399_TXRX_SRC_SEL_ISP0 BIT(4) +#define RK3399_TXRX_TURNREQUEST GENMASK(3, 0) + #define RK3568_GRF_VO_CON2 0x0368 #define RK3568_DSI0_SKEWCALHS (0x1f << 11) #define RK3568_DSI0_FORCETXSTOPMODE (0xf << 4) @@ -209,6 +235,8 @@ struct dw_rockchip_dsi_priv { struct clk *pclk; struct clk *ref; + struct clk *grf_clk; + struct clk *phy_cfg_clk; struct reset_ctl *rst; unsigned int lane_mbps; /* per lane */ u16 input_div; @@ -844,6 +872,28 @@ static int dw_mipi_dsi_rockchip_probe(struct udevice *dev) } } + if (cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { + priv->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); + if (IS_ERR(priv->phy_cfg_clk)) { + ret = PTR_ERR(priv->phy_cfg_clk); + dev_err(dev, "phy_cfg_clk clock get error %d\n", ret); + return ret; + } + + clk_enable(priv->phy_cfg_clk); + } + + if (cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { + priv->grf_clk = devm_clk_get(dev, "grf"); + if (IS_ERR(priv->grf_clk)) { + ret = PTR_ERR(priv->grf_clk); + dev_err(dev, "grf_clk clock get error %d\n", ret); + return ret; + } + + clk_enable(priv->grf_clk); + } + priv->rst = devm_reset_control_get_by_index(device->dev, 0); if (IS_ERR(priv->rst)) { ret = PTR_ERR(priv->rst); @@ -864,6 +914,52 @@ struct video_bridge_ops dw_mipi_dsi_rockchip_ops = { .set_backlight = dw_mipi_dsi_rockchip_set_bl, }; +static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { + { + .reg = 0xff960000, + .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, + .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL), + .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL, + RK3399_DSI0_LCDC_SEL), + + .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22, + .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST | + RK3399_DSI0_TURNDISABLE | + RK3399_DSI0_FORCETXSTOPMODE | + RK3399_DSI0_FORCERXMODE), + + .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, + .max_data_lanes = 4, + }, + { + .reg = 0xff968000, + .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, + .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL), + .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL, + RK3399_DSI1_LCDC_SEL), + + .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23, + .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE | + RK3399_DSI1_FORCETXSTOPMODE | + RK3399_DSI1_FORCERXMODE | + RK3399_DSI1_ENABLE), + + .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24, + .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ | + RK3399_TXRX_ENABLECLK, + RK3399_TXRX_MASTERSLAVEZ | + RK3399_TXRX_ENABLECLK | + RK3399_TXRX_BASEDIR), + + .enable_grf_reg = RK3399_GRF_SOC_CON23, + .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE), + + .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, + .max_data_lanes = 4, + }, + { /* sentinel */ } +}; + static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { { .reg = 0xfe060000, @@ -887,6 +983,9 @@ static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { }; static const struct udevice_id dw_mipi_dsi_rockchip_dt_ids[] = { + { .compatible = "rockchip,rk3399-mipi-dsi", + .data = (long)&rk3399_chip_data, + }, { .compatible = "rockchip,rk3568-mipi-dsi", .data = (long)&rk3568_chip_data, }, -- 2.40.1

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[PATCH] video: console: Fix default font selection
by Ondřej Jirman 17 Jul '23

17 Jul '23

From: Ondrej Jirman <megi(a)xff.cz> Some callers expect to call this with NULL font name to select the default font (eg. boot/scene.c). Without handling the NULL condition U-Boot crashes instead of displaying a bootflow GUI menu. Signed-off-by: Ondrej Jirman <megi(a)xff.cz> Cc: Anatolij Gustschin <agust(a)denx.de> --- drivers/video/console_core.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/video/console_core.c b/drivers/video/console_core.c index 1f93b1b85fa5..b5d0e3dceca3 100644 --- a/drivers/video/console_core.c +++ b/drivers/video/console_core.c @@ -201,6 +201,12 @@ int console_simple_select_font(struct udevice *dev, const char *name, uint size) { struct video_fontdata *font; + if (!name) { + if (fonts->name) + console_set_font(dev, fonts); + return 0; + } + for (font = fonts; font->name; font++) { if (!strcmp(name, font->name)) { console_set_font(dev, font); -- 2.40.1

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[PATCH] video: hx8394: Add panel driver for hannstar,hsd060bhw4
by Ondřej Jirman 17 Jul '23

17 Jul '23

From: Ondrej Jirman <megi(a)xff.cz> The driver is for panels based on the Himax HX8394 controller, such as the HannStar HSD060BHW4 720x1440 TFT LCD panel that uses a MIPI-DSI interface. This panel is used in Pinephone Pro. Signed-off-by: Ondrej Jirman <megi(a)xff.cz> Cc: Anatolij Gustschin <agust(a)denx.de> --- drivers/video/Kconfig | 8 ++ drivers/video/Makefile | 1 + drivers/video/himax-hx8394.c | 237 +++++++++++++++++++++++++++++++++++ 3 files changed, 246 insertions(+) create mode 100644 drivers/video/himax-hx8394.c diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 1e2f4e6de4a5..9efe69361ca6 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -477,6 +477,14 @@ config VIDEO_LCD_ENDEAVORU using the same DSI command sequence. The panel has a 720x1280 resolution and uses 24 bit RGB per pixel. +config VIDEO_LCD_HIMAX_HX8394 + bool "Himax HX8394 DSI LCD panel support" + depends on PANEL && BACKLIGHT + select VIDEO_MIPI_DSI + help + Say Y here if you want to enable support for Himax HX8394 + dsi 4dl panel. + config VIDEO_LCD_ORISETECH_OTM8009A bool "OTM8009A DSI LCD panel support" select VIDEO_MIPI_DSI diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 9a53cd141875..5dcc3fea08cb 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_VIDEO_IPUV3) += imx/ obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o obj-$(CONFIG_VIDEO_LCD_ENDEAVORU) += endeavoru-panel.o +obj-$(CONFIG_VIDEO_LCD_HIMAX_HX8394) += himax-hx8394.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o diff --git a/drivers/video/himax-hx8394.c b/drivers/video/himax-hx8394.c new file mode 100644 index 000000000000..63637b4db022 --- /dev/null +++ b/drivers/video/himax-hx8394.c @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Ondrej Jirman <megi(a)xff.cz> + */ +#include <common.h> +#include <backlight.h> +#include <dm.h> +#include <mipi_dsi.h> +#include <panel.h> +#include <asm/gpio.h> +#include <dm/device_compat.h> +#include <linux/delay.h> +#include <power/regulator.h> + +struct hx8394_panel_priv { + struct udevice *reg_vcc; + struct udevice *reg_iovcc; + struct gpio_desc reset; + struct udevice *backlight; +}; + +static const struct display_timing default_timing = { + .pixelclock.typ = 74250000, + .hactive.typ = 720, + .hfront_porch.typ = 40, + .hback_porch.typ = 40, + .hsync_len.typ = 46, + .vactive.typ = 1440, + .vfront_porch.typ = 7, + .vback_porch.typ = 9, + .vsync_len.typ = 7, + .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, +}; + +#define dsi_dcs_write_seq(device, seq...) do { \ + static const u8 d[] = { seq }; \ + int ret; \ + ret = mipi_dsi_dcs_write_buffer(device, d, ARRAY_SIZE(d)); \ + if (ret < 0) \ + return ret; \ + } while (0) + +static int hx8394_init_sequence(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *device = plat->device; + int ret; + + dsi_dcs_write_seq(device, 0xb9, 0xff, 0x83, 0x94); + dsi_dcs_write_seq(device, 0xb1, 0x48, 0x11, 0x71, 0x09, 0x32, 0x24, + 0x71, 0x31, 0x55, 0x30); + dsi_dcs_write_seq(device, 0xba, 0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0); + dsi_dcs_write_seq(device, 0xb2, 0x00, 0x80, 0x78, 0x0c, 0x07); + dsi_dcs_write_seq(device, 0xb4, 0x12, 0x63, 0x12, 0x63, 0x12, 0x63, + 0x01, 0x0c, 0x7c, 0x55, 0x00, 0x3f, 0x12, 0x6b, 0x12, + 0x6b, 0x12, 0x6b, 0x01, 0x0c, 0x7c); + dsi_dcs_write_seq(device, 0xd3, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x1c, + 0x00, 0x00, 0x32, 0x10, 0x09, 0x00, 0x09, 0x32, 0x15, + 0xad, 0x05, 0xad, 0x32, 0x00, 0x00, 0x00, 0x00, 0x37, + 0x03, 0x0b, 0x0b, 0x37, 0x00, 0x00, 0x00, 0x0c, 0x40); + dsi_dcs_write_seq(device, 0xd5, 0x19, 0x19, 0x18, 0x18, 0x1b, 0x1b, + 0x1a, 0x1a, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, + 0x07, 0x20, 0x21, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x24, 0x25, 0x18, + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0x18, 0x18); + dsi_dcs_write_seq(device, 0xd6, 0x18, 0x18, 0x19, 0x19, 0x1b, 0x1b, + 0x1a, 0x1a, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, + 0x00, 0x25, 0x24, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x21, 0x20, 0x18, + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0x18, 0x18); + dsi_dcs_write_seq(device, 0xe0, 0x00, 0x04, 0x0c, 0x12, 0x14, 0x18, + 0x1a, 0x18, 0x31, 0x3f, 0x4d, 0x4c, 0x54, 0x65, 0x6b, + 0x70, 0x7f, 0x82, 0x7e, 0x8a, 0x99, 0x4a, 0x48, 0x49, + 0x4b, 0x4a, 0x4c, 0x4b, 0x7f, 0x00, 0x04, 0x0c, 0x11, + 0x13, 0x17, 0x1a, 0x18, 0x31, 0x3f, 0x4d, 0x4c, 0x54, + 0x65, 0x6b, 0x70, 0x7f, 0x82, 0x7e, 0x8a, 0x99, 0x4a, + 0x48, 0x49, 0x4b, 0x4a, 0x4c, 0x4b, 0x7f); + dsi_dcs_write_seq(device, 0xcc, 0x0b); + dsi_dcs_write_seq(device, 0xc0, 0x1f, 0x31); + dsi_dcs_write_seq(device, 0xb6, 0x7d, 0x7d); + dsi_dcs_write_seq(device, 0xd4, 0x02); + dsi_dcs_write_seq(device, 0xbd, 0x01); + dsi_dcs_write_seq(device, 0xb1, 0x00); + dsi_dcs_write_seq(device, 0xbd, 0x00); + dsi_dcs_write_seq(device, 0xc6, 0xed); + + ret = mipi_dsi_dcs_exit_sleep_mode(device); + if (ret) + return ret; + + /* Panel is operational 120 msec after reset */ + mdelay(120); + + ret = mipi_dsi_dcs_set_display_on(device); + if (ret) + return ret; + + return 0; +} + +static int hx8394_panel_enable_backlight(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *device = plat->device; + struct hx8394_panel_priv *priv = dev_get_priv(dev); + int ret; + + ret = mipi_dsi_attach(device); + if (ret < 0) { + printf("mipi_dsi_attach failed %d\n", ret); + return ret; + } + + ret = hx8394_init_sequence(dev); + if (ret) { + printf("hx8394_init_sequence failed %d\n", ret); + return ret; + } + + if (priv->backlight) { + ret = backlight_enable(priv->backlight); + if (ret) { + printf("backlight enabled failed %d\n", ret); + return ret; + } + + backlight_set_brightness(priv->backlight, 60); + } + + mdelay(10); + + return 0; +} + +static int hx8394_panel_get_display_timing(struct udevice *dev, + struct display_timing *timings) +{ + memcpy(timings, &default_timing, sizeof(*timings)); + + return 0; +} + +static int hx8394_panel_of_to_plat(struct udevice *dev) +{ + struct hx8394_panel_priv *priv = dev_get_priv(dev); + int ret; + + if (CONFIG_IS_ENABLED(DM_REGULATOR)) { + ret = device_get_supply_regulator(dev, "vcc-supply", + &priv->reg_vcc); + if (ret && ret != -ENOENT) { + dev_err(dev, "Warning: cannot get vcc supply\n"); + return ret; + } + + ret = device_get_supply_regulator(dev, "iovcc-supply", + &priv->reg_iovcc); + if (ret && ret != -ENOENT) { + dev_err(dev, "Warning: cannot get iovcc supply\n"); + return ret; + } + } + + ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, + "backlight", &priv->backlight); + if (ret) + dev_warn(dev, "failed to get backlight\n"); + + ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset, + GPIOD_IS_OUT); + if (ret) { + dev_err(dev, "warning: cannot get reset GPIO (%d)\n", ret); + if (ret != -ENOENT) + return ret; + } + + return 0; +} + +static int hx8394_panel_probe(struct udevice *dev) +{ + struct hx8394_panel_priv *priv = dev_get_priv(dev); + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + int ret; + + dm_gpio_set_value(&priv->reset, true); + + if (CONFIG_IS_ENABLED(DM_REGULATOR)) { + dev_dbg(dev, "enable vcc '%s'\n", priv->reg_vcc->name); + ret = regulator_set_enable(priv->reg_vcc, true); + if (ret) + return ret; + + dev_dbg(dev, "enable iovcc '%s'\n", priv->reg_iovcc->name); + ret = regulator_set_enable(priv->reg_iovcc, true); + if (ret) { + regulator_set_enable(priv->reg_vcc, false); + return ret; + } + } + + mdelay(5); + dm_gpio_set_value(&priv->reset, false); + + mdelay(180); + + /* fill characteristics of DSI data link */ + plat->lanes = 4; + plat->format = MIPI_DSI_FMT_RGB888; + plat->mode_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_BURST; + + return 0; +} + +static const struct panel_ops hx8394_panel_ops = { + .enable_backlight = hx8394_panel_enable_backlight, + .get_display_timing = hx8394_panel_get_display_timing, +}; + +static const struct udevice_id hx8394_panel_ids[] = { + { .compatible = "hannstar,hsd060bhw4" }, + { } +}; + +U_BOOT_DRIVER(hx8394_panel) = { + .name = "hx8394_panel", + .id = UCLASS_PANEL, + .of_match = hx8394_panel_ids, + .ops = &hx8394_panel_ops, + .of_to_plat = hx8394_panel_of_to_plat, + .probe = hx8394_panel_probe, + .plat_auto = sizeof(struct mipi_dsi_panel_plat), + .priv_auto = sizeof(struct hx8394_panel_priv), +}; -- 2.40.1

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[PATCH v2 0/9] rockchip: Fix PCIe and NVMe support on RK3568
by Jonas Karlman 15 Jul '23

15 Jul '23

This series fixes and enables PCIe and NVMe support on RK3568. Patch 1 adds a dev_read_addr_size_index_ptr function. Patch 2-3 fixes main issue in the driver to be usable on RK3568. Patch 4 fixes a long wait time during probe when no device is attached. Patch 5 hides BARs of the root complex that could claim the entire memory region during PCI autoconfig. Patch 6 adds support for the gpios prop to the fixed regulators driver. Patch 7 adds a missing clock to the clock driver. Patch 8 enables PCIe and NVMe support on rk3568-rock-3a. Patch 9 updates the device tree with new reg and ranges values. For a clean apply of patch 8, the series at [1] may be needed. I have tested that a Samsung 970 EVO NVMe is detected on a ROCK 3A, BusDevFun VendorId DeviceId Device Class Sub-Class 00.00.00 0x1d87 0x3566 Bridge device 0x04 01.00.00 0x144d 0xa808 Mass storage controller 0x08 and I have also verified that the network controller continues to be detected on a ROCK 5B. BusDevFun VendorId DeviceId Device Class Sub-Class 00.00.00 0x1d87 0x3588 Bridge device 0x04 01.00.00 0x10ec 0x8125 Network controller 0x00 Changes in v2: - Rebased on custodians/u-boot-rockchip master branch and the defconfig and spi v2 series at [1]. - Drop dependency on basic reference counting of gpio regulators series, pcie2x1 is disabled for rk3568-rock-3a to avoid a system freeze due to disable of a shared vpcie3v3-supply regulator while in use by pcie3x2. - Add and use dev_read_addr_size_index_ptr function. - Update commit messages. - Collect r-b tags. This series can also be found at [2]. [1] https://patchwork.ozlabs.org/project/uboot/cover/20230517182624.1765359-1-j… [2] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3568-pcie-v2 Jonas Karlman (9): core: read: add dev_read_addr_size_index_ptr function pci: pcie_dw_rockchip: Get config region from reg prop pci: pcie_dw_rockchip: Use regulator_set_enable_if_allowed pci: pcie_dw_rockchip: Speed up link probe pci: pcie_dw_rockchip: Hide BARs of the root complex regulator: fixed: Add support for gpios prop rockchip: clk: clk_rk3568: Add CLK_PCIEPHY2_REF support rockchip: rk3568-rock-3a: Enable PCIe and NVMe support rockchip: rk356x: Update PCIe config, IO and memory regions arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 16 ++++ arch/arm/dts/rk3568.dtsi | 14 +-- arch/arm/dts/rk356x.dtsi | 7 +- configs/rock-3a-rk3568_defconfig | 4 + drivers/clk/rockchip/clk_rk3568.c | 1 + drivers/core/read.c | 11 +++ drivers/pci/pcie_dw_common.c | 10 +- drivers/pci/pcie_dw_rockchip.c | 120 +++++++++++++++--------- drivers/power/regulator/fixed.c | 5 +- include/dm/read.h | 21 +++++ 10 files changed, 153 insertions(+), 56 deletions(-) -- 2.40.1

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