April 2023 - U-Boot

command segmentation fault
by harry_lockyer＠tutanota.com 26 Apr '23

26 Apr '23

Hello, this is my first time reporting anything. I found a segmentation fault can be triggered when using the binary after compiling it for sandbox mode. Example:$ sudo make sandbox_defconfig$ sudo make $. /u-boot -c ⧵0xef⧵0xbf⧵0xbd U-Boot 2023.04-rc1-00507-gc34009d5a9-dirty (Apr 25 2023 - 17:09:16 -0400) DRAM: 256 MiB Core: 26 devices, 14 uclasses, devicetree: board MMC: Loading Environment from nowhere... OK Warning: device tree node '/config/environment' not found In: serial Out: serial Err: serial Net: No ethernet found. zsh: segmentation fault ./u-boot -c ⧵0xef⧵0xbf⧵0xbd All the best, Harry -- Sent with Tutanota, enjoy secure & ad-free emails.

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[PATCH V2 0/3] spi: cadence_qspi: Fixes for DTR ops and improve STIG support
by Dhruva Gole 26 Apr '23

26 Apr '23

This series aims to address some critical bugs in the cadence qspi driver like the need to Flush the CMDCTRL reg after the execution due to a hardware limitation and also fixes the check conditions for DTR ops. previously posted: https://lore.kernel.org/u-boot/20230323164408.1043725-1-d-gole@ti.com/ Changelog: * Preserve Apurva's authorship * Split the cmdctrl reg clearing patch into a seperate one * Address few other comments from Pratyush on the previous series Logs (on AM62x SK EVM): ... U-Boot 2023.04-rc5-00589-g1a9171bfbc66 (Apr 12 2023 - 16:16:19 +0530) SoC: AM62X SR1.0 HS-FS Model: Texas Instruments AM625 SK DRAM: 2 GiB Core: 50 devices, 20 uclasses, devicetree: separate MMC: mmc@fa10000: 0, mmc@fa00000: 1, mmc@fa20000: 2 Loading Environment from nowhere... OK In: serial@2800000 Out: serial@2800000 Err: serial@2800000 Net: eth0: ethernet@8000000port@1 Hit any key to stop autoboot: 0 => => sf probe SF: Detected s28hs512t with page size 256 Bytes, erase size 256 KiB, total 64 MiB => random $loadaddr 0x200000 2097152 bytes filled with random data => sf update $loadaddr 0x0 0x200000 device 0 offset 0x0, size 0x200000 2097152 bytes written, 0 bytes skipped in 13.365s, speed 160643 B/s => sf read 0x90000000 0x0 0x200000 device 0 offset 0x0, size 0x200000 SF: 2097152 bytes @ 0x0 Read: OK => cmp.b $loadaddr 0x90000000 0x200000 Total of 2097152 byte(s) were the same local git log: ... 1a9171bfbc66 (HEAD -> next) spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completion f60c2702c9df spi: cadence-quadspi: Use STIG mode for all ops with small payload f84f1b610f90 spi: cadence-quadspi: Fix check condition for DTR ops a25dcda452bf (origin/next) Revert "disk: Use a helper function to reduce duplication" ... Apurva Nandan (2): spi: cadence-quadspi: Fix check condition for DTR ops spi: cadence-quadspi: Use STIG mode for all ops with small payload Dhruva Gole (1): spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completion drivers/spi/cadence_qspi.c | 16 +++++++--- drivers/spi/cadence_qspi_apb.c | 56 +++++++++++++++++++++------------- 2 files changed, 46 insertions(+), 26 deletions(-) -- 2.25.1

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[PATCH V2 00/53] NXP-IMX pending patches
by Peng Fan (OSS) 26 Apr '23

26 Apr '23

From: Peng Fan <peng.fan(a)nxp.com> V2: Rebased on Stefano's imx/master Resolve conflicts. CI: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/12881 V1: This is to resend the pending patches [1,2,3] for Stefano to pick Patchset base: fc97ff2695d6d7fbea7d5fda7b080f405d6ee744 (origin/master, origin/HEAD, imx/master) Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi Rebased patches to avoid buid break. 1. https://patchwork.ozlabs.org/project/uboot/patch/20220711071853.9299-1-peng… 2. https://patchwork.ozlabs.org/project/uboot/cover/20220705060644.4509-1-peng… 3. https://patchwork.ozlabs.org/project/uboot/cover/20220627034130.5892-1-peng… CI: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/12806 THere is one error is arm32 build exceed 1 hour fail, which i think not because of this patchset. Alice Guo (3): misc: imx8ulp: move fuse.c from imx8ulp to sentinel misc: fuse: support to access fuse on i.MX93 misc: fuse: update the code for accessing fuse of i.MX93 Jian Li (1): imx: imx9: Add function to initialize timer Peng Fan (35): spl: imx8mm: enlarge SPL_MAX_SIZE arm: makefile: cleanup mach-imx usage imx: simplify dependency with SPL_BOOTROM_SUPPORT imx: move get_boot_device to common header imx: move get_boot_device to common file imx: add USB2_BOOT type imx: add basic i.MX9 support fsl_lpuart: add i.MX9 support gpio: pca953x: support pcal6524 imx: pinctrl: add pinctrl and pinfunc file for i.MX93 imx: imx9: Add CCM and clock API support mmc: fsl_esdhc_imx: Support i.MX9 spl: Use SPL_FIT_IMAGE_TINY for iMX9 imx: imx9: support romapi misc: s4mu: Support iMX93 with Sentinel MU misc: S400_API: New API for FW status and chip info misc: s400_api: introduce ahab_release_m33_trout imx: imx9: Get the chip revision through S400 API imx: imx9: Add MIX power init imx: imx9: Add M33 release prepare function imx: imx9: Support booting m33 from Acore arm: dts: Add i.MX93 SoC DTSi file imx: imx93_evk: Add basic board support imx: imx93_evk: Set ARM clock to 1.7Ghz net: fec_mxc: support i.MX93 net: dwc_eth_qos: fix build break when CLK not enabled net: dwc_eth_qos: public some functions net: dwc_eth_qos: move i.MX code out net: dwc_eth_qos: introduce eqos hook eqos_get_enetaddr board: freescale: imx93_evk: support ethernet tools: image: support i.MX93 arm: dts: imx8m: update binman ddr firmware node name ddr: imx8m: helper: load ddr firmware according to binman symbols arm: dts: imx8m: shrink ddr firmware size to actual file size imx: imx8mm-icore: migrate to use BINMAN Ye Li (14): imx: Change USB boot device type imx: spl: Allow iMX7/8/8M to overwrite spl_board_boot_device imx: imx9: disable watchdog misc: imx: S400_API: Move S400 MU and API to a common place misc: S400_API: Update release RDC API imx: imx9: Add TRDC driver for TRDC init imx: imx9: Add AHAB boot support misc: S400_API: Rename imx8ulp_s400_msg to sentinel_msg imx: imx9: Add gpio registers structure imx: imx9: Support multiple env storages at runtime imx: imx9: clock: Add DDR clock support ddr: imx: Add i.MX9 DDR controller driver ddr: imx9: enable Performance monitor counter net: eqos: add function to get phy node and address arch/arm/Kconfig | 16 + arch/arm/Makefile | 12 +- arch/arm/dts/Makefile | 3 + arch/arm/dts/imx8mm-u-boot.dtsi | 16 +- arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi | 20 +- .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 8 +- arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 20 +- arch/arm/dts/imx8mn-evk-u-boot.dtsi | 20 +- .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 16 +- arch/arm/dts/imx8mn-venice-u-boot.dtsi | 16 +- arch/arm/dts/imx8mp-u-boot.dtsi | 20 +- arch/arm/dts/imx8mq-cm-u-boot.dtsi | 20 +- arch/arm/dts/imx8mq-u-boot.dtsi | 16 +- arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 157 ++ arch/arm/dts/imx93-11x11-evk.dts | 527 ++++++ arch/arm/dts/imx93-pinfunc.h | 625 +++++++ arch/arm/dts/imx93.dtsi | 688 ++++++++ arch/arm/include/asm/arch-imx/cpu.h | 2 + arch/arm/include/asm/arch-imx8/sys_proto.h | 1 - arch/arm/include/asm/arch-imx8m/ddr.h | 6 +- arch/arm/include/asm/arch-imx8m/sys_proto.h | 2 +- arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 5 - arch/arm/include/asm/arch-imx9/ccm_regs.h | 266 +++ arch/arm/include/asm/arch-imx9/clock.h | 244 +++ arch/arm/include/asm/arch-imx9/ddr.h | 126 ++ arch/arm/include/asm/arch-imx9/gpio.h | 20 + arch/arm/include/asm/arch-imx9/imx-regs.h | 234 +++ arch/arm/include/asm/arch-imx9/imx93_pins.h | 729 ++++++++ arch/arm/include/asm/arch-imx9/sys_proto.h | 14 + arch/arm/include/asm/arch-imx9/trdc.h | 19 + arch/arm/include/asm/arch-mx7/sys_proto.h | 1 - arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 1 - arch/arm/include/asm/global_data.h | 5 +- arch/arm/include/asm/mach-imx/boot_mode.h | 1 + arch/arm/include/asm/mach-imx/iomux-v3.h | 11 +- .../asm/{arch-imx8ulp => mach-imx}/mu_hal.h | 4 +- .../asm/{arch-imx8ulp => mach-imx}/s400_api.h | 18 +- arch/arm/include/asm/mach-imx/sys_proto.h | 12 +- arch/arm/mach-imx/Kconfig | 5 +- arch/arm/mach-imx/Makefile | 9 +- arch/arm/mach-imx/imx8m/Kconfig | 1 + .../mach-imx/imx8m/imximage-8mm-lpddr4.cfg | 10 +- arch/arm/mach-imx/imx8m/soc.c | 44 - arch/arm/mach-imx/imx8ulp/ahab.c | 345 ++++ arch/arm/mach-imx/imx8ulp/rdc.c | 6 +- arch/arm/mach-imx/imx8ulp/soc.c | 45 +- arch/arm/mach-imx/imx9/Kconfig | 34 + arch/arm/mach-imx/imx9/Makefile | 11 + arch/arm/mach-imx/imx9/ahab.c | 346 ++++ arch/arm/mach-imx/imx9/clock.c | 844 ++++++++++ arch/arm/mach-imx/imx9/clock_root.c | 438 +++++ arch/arm/mach-imx/imx9/imx_bootaux.c | 133 ++ arch/arm/mach-imx/imx9/lowlevel_init.S | 26 + arch/arm/mach-imx/imx9/soc.c | 473 ++++++ arch/arm/mach-imx/imx9/trdc.c | 581 +++++++ arch/arm/mach-imx/romapi.c | 47 + arch/arm/mach-imx/spl.c | 82 +- board/freescale/common/Makefile | 2 +- board/freescale/imx8ulp_evk/spl.c | 2 +- board/freescale/imx93_evk/Kconfig | 19 + board/freescale/imx93_evk/MAINTAINERS | 6 + board/freescale/imx93_evk/Makefile | 12 + board/freescale/imx93_evk/imx93_evk.c | 90 + board/freescale/imx93_evk/lpddr4x_timing.c | 1486 +++++++++++++++++ board/freescale/imx93_evk/spl.c | 129 ++ common/spl/Kconfig | 3 +- configs/imx8mm-cl-iot-gate-optee_defconfig | 1 - configs/imx8mm-cl-iot-gate_defconfig | 1 - configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 3 +- configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 3 +- configs/imx8mm-mx8menlo_defconfig | 1 - configs/imx8mm_beacon_defconfig | 1 - configs/imx8mm_data_modul_edm_sbc_defconfig | 1 - configs/imx8mm_evk_defconfig | 1 - configs/imx8mm_venice_defconfig | 1 - configs/imx93_11x11_evk_defconfig | 117 ++ configs/kontron-sl-mx8mm_defconfig | 1 - configs/phycore-imx8mm_defconfig | 1 - configs/verdin-imx8mm_defconfig | 1 - drivers/Makefile | 1 + drivers/ddr/imx/Kconfig | 2 + drivers/ddr/imx/imx8m/Kconfig | 1 + drivers/ddr/imx/imx8m/Makefile | 3 +- drivers/ddr/imx/imx8m/ddr_init.c | 219 +++ drivers/ddr/imx/imx9/Kconfig | 27 + drivers/ddr/imx/imx9/Makefile | 10 + drivers/ddr/imx/imx9/ddr_init.c | 489 ++++++ drivers/ddr/imx/phy/Kconfig | 4 + drivers/ddr/imx/phy/Makefile | 9 + drivers/ddr/imx/{imx8m => phy}/ddrphy_csr.c | 0 drivers/ddr/imx/{imx8m => phy}/ddrphy_train.c | 1 - drivers/ddr/imx/phy/ddrphy_utils.c | 169 ++ drivers/ddr/imx/{imx8m => phy}/helper.c | 92 +- drivers/gpio/pca953x_gpio.c | 4 + drivers/misc/Kconfig | 7 + drivers/misc/Makefile | 2 +- drivers/misc/{imx8ulp => sentinel}/Makefile | 2 +- drivers/misc/{imx8ulp => sentinel}/fuse.c | 96 +- drivers/misc/{imx8ulp => sentinel}/s400_api.c | 149 +- .../{imx8ulp/imx8ulp_mu.c => sentinel/s4mu.c} | 11 +- drivers/mmc/Kconfig | 2 +- drivers/net/Kconfig | 2 +- drivers/net/Makefile | 1 + drivers/net/dwc_eth_qos.c | 406 +---- drivers/net/dwc_eth_qos.h | 284 ++++ drivers/net/dwc_eth_qos_imx.c | 131 ++ drivers/net/fec_mxc.c | 4 +- drivers/pinctrl/nxp/Kconfig | 13 + drivers/pinctrl/nxp/Makefile | 1 + drivers/pinctrl/nxp/pinctrl-imx93.c | 37 + include/configs/imx93_evk.h | 145 ++ include/dt-bindings/clock/imx93-clock.h | 203 +++ include/dt-bindings/power/imx93-power.h | 12 + include/fsl_lpuart.h | 2 +- include/imx8image.h | 15 +- include/imx_sip.h | 1 + tools/imx8image.c | 79 +- 117 files changed, 11194 insertions(+), 725 deletions(-) create mode 100644 arch/arm/dts/imx93-11x11-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx93-11x11-evk.dts create mode 100644 arch/arm/dts/imx93-pinfunc.h create mode 100644 arch/arm/dts/imx93.dtsi create mode 100644 arch/arm/include/asm/arch-imx9/ccm_regs.h create mode 100644 arch/arm/include/asm/arch-imx9/clock.h create mode 100644 arch/arm/include/asm/arch-imx9/ddr.h create mode 100644 arch/arm/include/asm/arch-imx9/gpio.h create mode 100644 arch/arm/include/asm/arch-imx9/imx-regs.h create mode 100644 arch/arm/include/asm/arch-imx9/imx93_pins.h create mode 100644 arch/arm/include/asm/arch-imx9/sys_proto.h create mode 100644 arch/arm/include/asm/arch-imx9/trdc.h rename arch/arm/include/asm/{arch-imx8ulp => mach-imx}/mu_hal.h (79%) rename arch/arm/include/asm/{arch-imx8ulp => mach-imx}/s400_api.h (75%) create mode 100644 arch/arm/mach-imx/imx8ulp/ahab.c create mode 100644 arch/arm/mach-imx/imx9/Kconfig create mode 100644 arch/arm/mach-imx/imx9/Makefile create mode 100644 arch/arm/mach-imx/imx9/ahab.c create mode 100644 arch/arm/mach-imx/imx9/clock.c create mode 100644 arch/arm/mach-imx/imx9/clock_root.c create mode 100644 arch/arm/mach-imx/imx9/imx_bootaux.c create mode 100644 arch/arm/mach-imx/imx9/lowlevel_init.S create mode 100644 arch/arm/mach-imx/imx9/soc.c create mode 100644 arch/arm/mach-imx/imx9/trdc.c create mode 100644 board/freescale/imx93_evk/Kconfig create mode 100644 board/freescale/imx93_evk/MAINTAINERS create mode 100644 board/freescale/imx93_evk/Makefile create mode 100644 board/freescale/imx93_evk/imx93_evk.c create mode 100644 board/freescale/imx93_evk/lpddr4x_timing.c create mode 100644 board/freescale/imx93_evk/spl.c create mode 100644 configs/imx93_11x11_evk_defconfig create mode 100644 drivers/ddr/imx/imx9/Kconfig create mode 100644 drivers/ddr/imx/imx9/Makefile create mode 100644 drivers/ddr/imx/imx9/ddr_init.c create mode 100644 drivers/ddr/imx/phy/Kconfig create mode 100644 drivers/ddr/imx/phy/Makefile rename drivers/ddr/imx/{imx8m => phy}/ddrphy_csr.c (100%) rename drivers/ddr/imx/{imx8m => phy}/ddrphy_train.c (98%) create mode 100644 drivers/ddr/imx/phy/ddrphy_utils.c rename drivers/ddr/imx/{imx8m => phy}/helper.c (61%) rename drivers/misc/{imx8ulp => sentinel}/Makefile (67%) rename drivers/misc/{imx8ulp => sentinel}/fuse.c (69%) rename drivers/misc/{imx8ulp => sentinel}/s400_api.c (69%) rename drivers/misc/{imx8ulp/imx8ulp_mu.c => sentinel/s4mu.c} (94%) create mode 100644 drivers/net/dwc_eth_qos.h create mode 100644 drivers/net/dwc_eth_qos_imx.c create mode 100644 drivers/pinctrl/nxp/pinctrl-imx93.c create mode 100644 include/configs/imx93_evk.h create mode 100644 include/dt-bindings/clock/imx93-clock.h create mode 100644 include/dt-bindings/power/imx93-power.h -- 2.36.0

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[PATCH 0/2] net: phy: Make phy_interface_is_sgmii|rgmii a switch statement
by Nishanth Menon 25 Apr '23

25 Apr '23

Originally reported by Tom[1], turned out to be that recent commit 75d28899e3e9 ("net: phy: Synchronize PHY interface modes with Linux") reordered the enum definitions which in turn broke the range checks. we are left with two options: a) check against explicit values to help reuse as much as possible and let compiler optimize where applicable or b) be very explicit in phy drivers and drop these helpers. I have chosen to go with (a) approach. Tested on am64x, though the dp83867 is used elsewhere as well. Nishanth Menon (2): net: phy: Make phy_interface_is_sgmii a switch statement net: phy: Make phy_interface_is_rgmii a switch statement include/phy.h | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) -- 2.40.0

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[PATCH] common/Kconfig: fix comments syntax error
by Hugo Villeneuve 25 Apr '23

25 Apr '23

From: Hugo Villeneuve <hvilleneuve(a)dimonoff.com> Fix comments error in EVENT_DEBUG description: usefui -> useful Signed-off-by: Hugo Villeneuve <hvilleneuve(a)dimonoff.com> --- common/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/Kconfig b/common/Kconfig index f2783ee65d..8c5b672cdf 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -626,7 +626,7 @@ config EVENT_DEBUG bool "Enable event debugging assistance" default y if SANDBOX help - Enable this get usefui features for seeing what is happening with + Enable this get useful features for seeing what is happening with events, such as event-type names. This adds to the code size of U-Boot so can be turned off for production builds. -- 2.30.2

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[PATCH 0/6] virtio: Use bounce buffers when VIRTIO_F_IOMMU_PLATFORM set
by Ying-Chun Liu (PaulLiu) 25 Apr '23

25 Apr '23

These patches will use bounce buffers when VIRTIO_F_IOMMU_PLATFORM feature is in a virtio device. This feature can be tested with qemu with -device virtio-iommu-pci. So that when a -device virtio-blk-pci with iommu_platform=true, it will uses the bounce buffer instead. Will Deacon (6): virtio: Expose VIRTIO_F_IOMMU_PLATFORM in device features virtio: pci: Tear down VQs in virtio_pci_reset() virtio: Allocate virtqueue in page-size units virtio: Add helper functions to attach/detach vring descriptors virtio: Allocate bounce buffers for devices with VIRTIO_F_IOMMU_PLATFORM virtio: Use bounce buffers when VIRTIO_F_IOMMU_PLATFORM is set drivers/virtio/virtio-uclass.c | 2 +- drivers/virtio/virtio_pci_modern.c | 38 +++++------ drivers/virtio/virtio_ring.c | 101 ++++++++++++++++++++++++++--- include/virtio_ring.h | 21 +++--- 4 files changed, 125 insertions(+), 37 deletions(-) -- 2.39.2

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[PATCH] mtd: spi-nor-core: Add fixups for s25fs512s
by Marek Vasut 25 Apr '23

25 Apr '23

From: Takahiro Kuwano <Takahiro.Kuwano(a)infineon.com> This patch adds fixups for s25fs512s to address the following issues from reading SFDP: - Non-uniform sectors by factory default. The setting needs to be checked and assign erase hook as needed. - Page size is wrongly advertised in SFDP. - READ_1_1_2 (3Bh/3Ch), READ_1_1_4 (6Bh/6Ch), and PP_1_1_4 (32h/34h) are not supported. - Bank Address Register (BAR) is not supported. In addition, volatile version of Quad Enable is used for safety. Based on patch by Takahiro Kuwano with s25fs_s_post_bfpt_fixup() updated to use 4-byte address commands instead of extended address mode and the page_size is fixed to 256 For future use, manufacturer code should be moved out from framework code as same as in Linux. Reviewed-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano(a)infineon.com> Signed-off-by: Hai Pham <hai.pham.ud(a)renesas.com> Signed-off-by: Cong Dang <cong.dang.xn(a)renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- Cc: Jagan Teki <jagan(a)amarulasolutions.com> Cc: Takahiro Kuwano <Takahiro.Kuwano(a)infineon.com> Cc: Vignesh R <vigneshr(a)ti.com> --- drivers/mtd/spi/spi-nor-core.c | 85 ++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 2c3116ee530..a107f71df80 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3199,6 +3199,87 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, /* Use ID byte 4 to distinguish S25FS256T and S25Hx-T */ #define S25FS256T_ID4 (0x08) +/* Number of dummy cycle for Read Any Register (RDAR) op. */ +#define S25FS_S_RDAR_DUMMY 8 + +static int s25fs_s_quad_enable(struct spi_nor *nor) +{ + return spansion_quad_enable_volatile(nor, 0, S25FS_S_RDAR_DUMMY); +} + +static int s25fs_s_erase_non_uniform(struct spi_nor *nor, loff_t addr) +{ + /* Support 8 x 4KB sectors at bottom */ + return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0, SZ_32K); +} + +static int s25fs_s_setup(struct spi_nor *nor, const struct flash_info *info, + const struct spi_nor_flash_parameter *params) +{ + int ret; + u8 cfr3v; + + /* Bank Address Register is not supported */ + if (CONFIG_IS_ENABLED(SPI_FLASH_BAR)) + return -EOPNOTSUPP; + + /* + * Read CR3V to check if uniform sector is selected. If not, assign an + * erase hook that supports non-uniform erase. + */ + ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, + S25FS_S_RDAR_DUMMY, &cfr3v); + if (ret) + return ret; + if (!(cfr3v & CFR3V_UNHYSA)) + nor->erase = s25fs_s_erase_non_uniform; + + return spi_nor_default_setup(nor, info, params); +} + +static void s25fs_s_default_init(struct spi_nor *nor) +{ + nor->setup = s25fs_s_setup; +} + +static int s25fs_s_post_bfpt_fixup(struct spi_nor *nor, + const struct sfdp_parameter_header *header, + const struct sfdp_bfpt *bfpt, + struct spi_nor_flash_parameter *params) +{ + /* The erase size is set to 4K from BFPT, but it's wrong. Fix it. */ + nor->erase_opcode = SPINOR_OP_SE; + nor->mtd.erasesize = nor->info->sector_size; + + /* The S25FS-S chip family reports 512-byte pages in BFPT but + * in reality the write buffer still wraps at the safe default + * of 256 bytes. Overwrite the page size advertised by BFPT + * to get the writes working. + */ + params->page_size = 256; + + return 0; +} + +static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) +{ + /* READ_1_1_2 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2; + /* READ_1_1_4 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4; + /* PP_1_1_4 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; + /* Use volatile register to enable quad */ + params->quad_enable = s25fs_s_quad_enable; +} + +static struct spi_nor_fixups s25fs_s_fixups = { + .default_init = s25fs_s_default_init, + .post_bfpt = s25fs_s_post_bfpt_fixup, + .post_sfdp = s25fs_s_post_sfdp_fixup, +}; + static int s25_mdp_ready(struct spi_nor *nor) { u32 addr; @@ -3897,6 +3978,10 @@ void spi_nor_set_fixups(struct spi_nor *nor) if (CONFIG_IS_ENABLED(SPI_FLASH_BAR) && !strcmp(nor->info->name, "s25fl256l")) nor->fixups = &s25fl256l_fixups; + + /* For FS-S (family ID = 0x81) */ + if (JEDEC_MFR(nor->info) == SNOR_MFR_SPANSION && nor->info->id[5] == 0x81) + nor->fixups = &s25fs_s_fixups; #endif #ifdef CONFIG_SPI_FLASH_MT35XU -- 2.39.2

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[PATCH v2] cmd: sf/nand: Print and return failure when 0 length is passed
by Ashok Reddy Soma 25 Apr '23

25 Apr '23

For sf commands, when '0' length is passed for erase, update, write or read, there might be undesired results. Ideally '0' length means nothing to do. So print 'ERROR: Invalid size 0' and return cmd failure when length '0' is passed to sf commands. Same thing applies for nand commands also. Example: ZynqMP> sf erase 0 0 ERROR: Invalid size 0 ZynqMP> sf write 10000 0 0 ERROR: Invalid size 0 ZynqMP> sf read 10000 0 0 ERROR: Invalid size 0 ZynqMP> sf update 1000 10000 0 ERROR: Invalid size 0 ZynqMP> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma(a)amd.com> --- Changes in v2: - Changed print from 'size is 0' to Invalid size 0 without quites. - Modified description to be imperative - Fixed typo in description from "samething" to "same thing" cmd/legacy-mtd-utils.c | 5 +++++ cmd/sf.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/cmd/legacy-mtd-utils.c b/cmd/legacy-mtd-utils.c index ac7139f84d..61987918a4 100644 --- a/cmd/legacy-mtd-utils.c +++ b/cmd/legacy-mtd-utils.c @@ -88,6 +88,11 @@ int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off, return -1; } + if (*size == 0) { + printf("ERROR: Invalid size 0\n"); + return -1; + } + print: printf("device %d ", *idx); if (*size == chipsize) diff --git a/cmd/sf.c b/cmd/sf.c index 11b9c25896..a6aadc2b00 100644 --- a/cmd/sf.c +++ b/cmd/sf.c @@ -353,6 +353,11 @@ static int do_spi_flash_erase(int argc, char *const argv[]) if (ret != 1) return CMD_RET_USAGE; + if (size == 0) { + printf("ERROR: Invalid size 0\n"); + return CMD_RET_FAILURE; + } + /* Consistency checking */ if (offset + size > flash->size) { printf("ERROR: attempting %s past flash size (%#x)\n", -- 2.17.1

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[PATCH] spi: synquacer: Silence unused variable warnings
by Ilias Apalodimas 25 Apr '23

25 Apr '23

When building with clang, the compiler compains with drivers/spi/spi-synquacer.c:212:11: warning: variable 'bus_width' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized] else if (priv->mode & SPI_TX_OCTAL) ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/spi/spi-synquacer.c:276:11: note: uninitialized use occurs here val |= ((bus_width >> 1) << BUS_WIDTH); ^~~~~~~~~ drivers/spi/spi-synquacer.c:212:7: note: remove the 'if' if its condition is always true else if (priv->mode & SPI_TX_OCTAL) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/spi/spi-synquacer.c:189:25: note: initialize the variable 'bus_width' to silence this warning So initialize bus_width to 1 and add a warning if none of the configured modes matches Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- drivers/spi/spi-synquacer.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index 0cae3dfc778f..0f5d0a30c39d 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -186,7 +186,7 @@ static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx) struct udevice *bus = dev->parent; struct synquacer_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); - u32 val, div, bus_width; + u32 val, div, bus_width = 1; int rwflag; rwflag = (rx ? 1 : 0) | (tx ? 2 : 0); @@ -211,6 +211,8 @@ static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx) bus_width = 4; else if (priv->mode & SPI_TX_OCTAL) bus_width = 8; + else + log_warning("SPI mode not configured, setting to byte mode\n"); div = DIV_ROUND_UP(125000000, priv->speed); -- 2.39.2

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[PATCH 1/1] mtd: spi-nor: missing fallthrough in set_4byte()
by Heinrich Schuchardt 25 Apr '23

25 Apr '23

Add a missing fallthrough macro to avoid a -Wimplicit-fallthrough warning. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- drivers/mtd/spi/spi-nor-core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 2c3116ee53..31ca278128 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -669,6 +669,7 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info, case SNOR_MFR_MICRON: /* Some Micron need WREN command; all will accept it */ need_wren = true; + fallthrough; case SNOR_MFR_ISSI: case SNOR_MFR_MACRONIX: case SNOR_MFR_WINBOND: -- 2.39.2

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