April 2023 - U-Boot

[PATCH 1/1] cmd/sbi: display new extensions
by Heinrich Schuchardt 28 Apr '23

28 Apr '23

OpenSBI already implements some extensions that are not ratified yet: * Debug Console Extension (DBCN) * System Suspend Extension (SUSP) * Collaborative Processor Performance Control Extension (CPPC) Allow the sbi command to display these. Provide the FID definitions of the Debug Console Extension. We can use that extension for an early debug console driver. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- arch/riscv/include/asm/sbi.h | 9 +++++++++ cmd/riscv/sbi.c | 3 +++ 2 files changed, 12 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 81fcfe0b36..769369997d 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -28,6 +28,9 @@ enum sbi_ext_id { SBI_EXT_HSM = 0x48534D, SBI_EXT_SRST = 0x53525354, SBI_EXT_PMU = 0x504D55, + SBI_EXT_DBCN = 0x4442434E, + SBI_EXT_SUSP = 0x53555350, + SBI_EXT_CPPC = 0x43505043, }; enum sbi_ext_base_fid { @@ -89,6 +92,12 @@ enum sbi_srst_reset_reason { SBI_SRST_RESET_REASON_SYS_FAILURE, }; +enum sbi_ext_dbcn_fid { + SBI_EXT_DBCN_CONSOLE_WRITE = 0, + SBI_EXT_DBCN_CONSOLE_READ, + SBI_EXT_DBCN_CONSOLE_WRITE_BYTE, +}; + #ifdef CONFIG_SBI_V01 #define SBI_EXT_SET_TIMER SBI_EXT_0_1_SET_TIMER #define SBI_FID_SET_TIMER 0 diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index 6f2cad4e7e..c4707fe520 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -46,6 +46,9 @@ static struct sbi_ext extensions[] = { { SBI_EXT_HSM, "Hart State Management Extension" }, { SBI_EXT_SRST, "System Reset Extension" }, { SBI_EXT_PMU, "Performance Monitoring Unit Extension" }, + { SBI_EXT_DBCN, "Debug Console Extension" }, + { SBI_EXT_SUSP, "System Suspend Extension" }, + { SBI_EXT_CPPC, "Collaborative Processor Performance Control Extension" }, }; static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, -- 2.39.2

2 1

[PATCH] board: starfive: Fixed errors reported when executing get_maintainer.pl
by Yanhong Wang 28 Apr '23

28 Apr '23

Fixed errors reported when executing 'scripts/get_maintainer.pl -f configs/starfive_visionfive2_defconfig'. Invalid MAINTAINERS address: 'startfive' Signed-off-by: Yanhong Wang <yanhong.wang(a)starfivetech.com> --- board/starfive/visionfive2/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS index c5369086d8..600ff9575b 100644 --- a/board/starfive/visionfive2/MAINTAINERS +++ b/board/starfive/visionfive2/MAINTAINERS @@ -1,5 +1,5 @@ STARFIVE JH7110 VISIONFIVE2 BOARD -M: startfive +M: Yanhong Wang <yanhong.wang(a)starfivetech.com> S: Maintained F: arch/riscv/include/asm/arch-jh7110/ F: board/starfive/visionfive2/ -- 2.17.1

2 1

[PATCH] doc:fix typo in 'mmc write' example
by Alexander Shirokov 28 Apr '23

28 Apr '23

In the 'mmc write' command example, it writes 16 blocks (0x10). But the output contains 256 (0x100) blocks. This patch fixes the mismatch. Signed-off-by: Alexander Shirokov <shirokovalexs(a)gmail.com> --- doc/usage/cmd/mmc.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/usage/cmd/mmc.rst b/doc/usage/cmd/mmc.rst index 55e3f9cf98..41005b18ef 100644 --- a/doc/usage/cmd/mmc.rst +++ b/doc/usage/cmd/mmc.rst @@ -216,7 +216,7 @@ The raw data can be read/written via 'mmc read/write' command: => mmc read 0x40000000 0x5000 0x100 MMC read: dev # 0, block # 20480, count 256 ... 256 blocks read: OK - => mmc write 0x40000000 0x5000 0x10 + => mmc write 0x40000000 0x5000 0x100 MMC write: dev # 0, block # 20480, count 256 ... 256 blocks written: OK The partition list can be shown via 'mmc part' command: -- 2.40.0

4 12

[PATCH 1/1] doc: Indicate required OpenSBI release for VisionFive 2
by Heinrich Schuchardt 28 Apr '23

28 Apr '23

Support for the VisionFive 2 board is not contained in the most recent OpenSBI release (v1.2). Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- doc/board/starfive/visionfive2.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/board/starfive/visionfive2.rst b/doc/board/starfive/visionfive2.rst index 22d2a31ff5..dc9eb368c6 100644 --- a/doc/board/starfive/visionfive2.rst +++ b/doc/board/starfive/visionfive2.rst @@ -51,6 +51,8 @@ cloned and built for JH7110 as below: cd opensbi make PLATFORM=generic FW_TEXT_START=0x40000000 FW_OPTIONS=0 +The VisionFive 2 support for OpenSBI was introduced after the v1.2 release. + More detailed description of steps required to build FW_DYNAMIC firmware is beyond the scope of this document. Please refer OpenSBI documenation. (Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git) -- 2.39.2

2 1

[PATCH v1] arm64: dts: rockchip: Add Radxa ROCK 4C Plus support
by Denis 'GNUtoo' Carikli 28 Apr '23

28 Apr '23

rk3399-rock-4c-plus.dts and rk3399-t-opp.dtsi were imported from Linux 6.3. Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)cyberdimension.org> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 6 + arch/arm/dts/rk3399-rock-4c-plus.dts | 709 +++++++++++++++++++ arch/arm/dts/rk3399-t-opp.dtsi | 114 +++ board/rockchip/evb_rk3399/MAINTAINERS | 2 + configs/rock-4c-plus-rk3399_defconfig | 97 +++ doc/board/rockchip/rockchip.rst | 1 + 7 files changed, 930 insertions(+) create mode 100644 arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rock-4c-plus.dts create mode 100644 arch/arm/dts/rk3399-t-opp.dtsi create mode 100644 configs/rock-4c-plus-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3385948d22..c4db3753bb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -160,6 +160,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-rock-pi-4a.dtb \ rk3399-rock-pi-4b.dtb \ rk3399-rock-pi-4c.dtb \ + rk3399-rock-4c-plus.dtb \ rk3399-rock960.dtb \ rk3399-rockpro64.dtb \ rk3399pro-rock-pi-n10.dtb diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi new file mode 100644 index 0000000000..85ee5770ad --- /dev/null +++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki <jagan(a)amarulasolutions.com> + */ + +#include "rk3399-rock-pi-4-u-boot.dtsi" diff --git a/arch/arm/dts/rk3399-rock-4c-plus.dts b/arch/arm/dts/rk3399-rock-4c-plus.dts new file mode 100644 index 0000000000..028eb508ae --- /dev/null +++ b/arch/arm/dts/rk3399-rock-4c-plus.dts @@ -0,0 +1,709 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Radxa Limited + * Copyright (c) 2022 Amarula Solutions(India) + */ + +/dts-v1/; +#include <dt-bindings/leds/common.h> +#include "rk3399.dtsi" +#include "rk3399-t-opp.dtsi" + +/ { + model = "Radxa ROCK 4C+"; + compatible = "radxa,rock-4c-plus", "rockchip,rk3399"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led1 &user_led2>; + + /* USER_LED1 */ + led-0 { + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + /* USER_LED2 */ + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + vcc_3v3: vcc-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_phy1: vcc3v3-phy1-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_phy1"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc5v0_host1: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host1"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_host0_s0>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_typec: vcc5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec0_en>; + regulator-name = "vcc5v0_typec"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_log: vdd-log-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc3v3_phy1>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x2a>; + rx_delay = <0x21>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vcc_0v9_s0>; + avdd-1v8-supply = <&vcc_1v8_s0>; + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + i2c-scl-falling-time-ns = <30>; + i2c-scl-rising-time-ns = <180>; + clock-frequency = <400000>; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5_s3>; + vcc6-supply = <&vcc_buck5_s3>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_center"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5_s3: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_buck5_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_0v9_s3: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vcc_0v9_s3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_0v9_s0: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vcc_0v9_s0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_1v8_s0: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_mipi: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_mipi"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5_s0: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0_s0: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sdio_s0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_sdio_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_cam: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_cam"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_host0_s0: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_host0_s0"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + lcd_3v3: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "lcd_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + regulator-initial-mode = <1>; /* 1:force PWM 2:auto */ + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + audio-supply = <&vcc_1v8_s0>; + bt656-supply = <&vcc_3v0_s0>; + gpio1830-supply = <&vcc_3v0_s0>; + sdmmc-supply = <&vcc_sdio_s0>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + user_led1: user-led1 { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led2: user-led2 { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdmmc { + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <4 8 1 &pcfg_pull_up_8ma>, + <4 9 1 &pcfg_pull_up_8ma>, + <4 10 1 &pcfg_pull_up_8ma>, + <4 11 1 &pcfg_pull_up_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <4 12 1 &pcfg_pull_none_18ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <4 13 1 &pcfg_pull_up_8ma>; + }; + }; + + usb-typec { + vcc5v0_typec0_en: vcc5v0-typec-en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0_s0>; + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s3>; +}; + +&sdhci { + max-frequency = <150000000>; + bus-width = <8>; + mmc-hs400-1_8v; + non-removable; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdio0 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <800>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + vqmmc-supply = <&vcc_sdio_s0>; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host1>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host1>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8_s3>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + extcon = <&u2phy0>; + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "host"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-t-opp.dtsi b/arch/arm/dts/rk3399-t-opp.dtsi new file mode 100644 index 0000000000..1ababadda9 --- /dev/null +++ b/arch/arm/dts/rk3399-t-opp.dtsi @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2022 Radxa Limited + */ + +/ { + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <875000 875000 1250000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <875000 875000 1250000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <900000 900000 1250000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <975000 975000 1250000>; + }; + }; + + cluster1_opp: opp-table-1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <875000 875000 1250000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <875000 875000 1250000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <875000 875000 1250000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <925000 925000 1250000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1000000 1000000 1250000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1075000 1075000 1250000>; + }; + opp06 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1150000 1150000 1250000>; + }; + }; + + gpu_opp_table: opp-table-2 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <875000 875000 1150000>; + }; + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <875000 875000 1150000>; + }; + opp02 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <875000 875000 1150000>; + }; + opp03 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000 975000 1150000>; + }; + }; +}; + +&cpu_l0 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l1 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l2 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l3 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_b0 { + operating-points-v2 = <&cluster1_opp>; +}; + +&cpu_b1 { + operating-points-v2 = <&cluster1_opp>; +}; + +&gpu { + operating-points-v2 = <&gpu_opp_table>; +}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 5be58f80f9..4bfc25fae0 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -88,6 +88,8 @@ F: configs/rock-pi-4-rk3399_defconfig F: arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi F: configs/rock-pi-4c-rk3399_defconfig F: arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi +F: configs/rock-4c-plus-rk3399_defconfig +F: arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi ROCK-PI-N10 M: Jagan Teki <jagan(a)amarulasolutions.com> diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig new file mode 100644 index 0000000000..97693166d9 --- /dev/null +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -0,0 +1,97 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00200000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4c-plus" +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4c-plus.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DFU_MMC=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 1dccb17d72..3b6f1aad8f 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -84,6 +84,7 @@ List of mainline supported Rockchip boards: - Orange Pi RK3399 (orangepi-rk3399) - Pine64 RockPro64 (rockpro64-rk3399) - Radxa ROCK Pi 4 (rock-pi-4-rk3399) + - Radxa ROCK Pi Plus (rk3399-rock-4c-plus) - Rockchip Evb-RK3399 (evb_rk3399) - Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399) base-commit: c9c2c95d4cd27fe0cd41fe13a863899d268f973c -- 2.39.1

1 0

[PATCH] Kconfig: Remove an impossible condition
by Samuel Holland 28 Apr '23

28 Apr '23

ARCH_SUNXI selects BINMAN, so the condition "!BINMAN && ARCH_SUNXI" is impossible to satisfy. Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Kconfig b/Kconfig index a75cce7e28..f810646e8a 100644 --- a/Kconfig +++ b/Kconfig @@ -459,7 +459,7 @@ config BUILD_TARGET default "u-boot-with-spl.kwb" if ARMADA_32BIT && SPL default "u-boot-elf.srec" if RCAR_GEN3 default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \ - ARCH_SUNXI || RISCV || ARCH_ZYNQMP) + RISCV || ARCH_ZYNQMP) default "u-boot.kwb" if (ARCH_KIRKWOOD || ARMADA_32BIT) && !SPL default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT -- 2.37.4

2 1

[PATCH 0/3] power: Model X-Powers PMIC VBUS detection using the driver model
by Samuel Holland 28 Apr '23

28 Apr '23

This is the next step, after basic regulator support[1], of converting the X-Powers AXPxxx PMIC to use the driver model. This series creates a regulator driver to represent the VBUS detection function, which is used by the sun4i USB PHY driver. The USB PHY driver has already been updated to use this regulator device when present[2]. The net result is removing some ugly hacks from a couple of GPIO drivers. [1]: https://lore.kernel.org/u-boot/20230121231307.42628-1-samuel@sholland.org/ [2]: commit 6fa41cdd19b9 ("phy: sun4i-usb: Support VBUS detection via power supply") Samuel Holland (3): power: regulator: Add a driver for the AXP USB power supply sunxi: Switch to PMIC USB power supply VBUS detection gpio: axp/sunxi: Remove virtual VBUS detection GPIO arch/arm/include/asm/arch-sunxi/gpio.h | 1 - configs/A33-OLinuXino_defconfig | 2 +- configs/Ainol_AW1_defconfig | 2 +- configs/Cubieboard4_defconfig | 3 +- configs/Cubietruck_plus_defconfig | 2 +- configs/MSI_Primo81_defconfig | 2 +- configs/Merrii_A80_Optimus_defconfig | 3 +- .../Nintendo_NES_Classic_Edition_defconfig | 2 +- configs/Sinovoip_BPI_M3_defconfig | 2 +- configs/Wexler_TAB7200_defconfig | 2 +- configs/Yones_Toptech_BD1078_defconfig | 2 +- configs/Yones_Toptech_BS1078_V2_defconfig | 2 +- configs/colorfly_e708_q1_defconfig | 2 +- configs/ga10h_v1_1_defconfig | 2 +- configs/gt90h_v4_defconfig | 2 +- configs/iNet_D978_rev2_defconfig | 2 +- configs/inet86dz_defconfig | 2 +- configs/inet_q972_defconfig | 2 +- configs/polaroid_mid2407pxe03_defconfig | 2 +- configs/polaroid_mid2809pxe04_defconfig | 2 +- configs/q8_a23_tablet_800x480_defconfig | 2 +- configs/q8_a33_tablet_1024x600_defconfig | 2 +- configs/q8_a33_tablet_800x480_defconfig | 2 +- configs/tbs_a711_defconfig | 2 +- drivers/gpio/axp_gpio.c | 21 ++------ drivers/gpio/sunxi_gpio.c | 6 +-- drivers/power/regulator/Kconfig | 7 +++ drivers/power/regulator/Makefile | 1 + drivers/power/regulator/axp_usb_power.c | 49 +++++++++++++++++++ include/axp209.h | 1 - include/axp221.h | 1 - include/axp809.h | 1 - include/axp818.h | 1 - 33 files changed, 87 insertions(+), 50 deletions(-) create mode 100644 drivers/power/regulator/axp_usb_power.c -- 2.37.4

2 6

Question regarding CONFIG_SPL_OF_PLATDATA_INST usage
by Lukasz Majewski 28 Apr '23

28 Apr '23

Hi Simon, I'm trying to convert imx28 based XEA board to use CONFIG_DM_SERIAL. This board uses SPL_OF_PLATDATA to have as small SPL as possible. It looks like the 'duart' description/driver is properly instantiated, but serial console is configured too early -> apparently serial_find_console_or_panic() from serial_init() at serial-uclass.c is called before DM is setup in SPL. To fix this problem - in the commit (SHA1: 5a1b25c2011) the CONFIG_SPL_OF_PLATDATA_INST has been introduced; without it (after commit SHA1: 1e9ced28f18ed75bef96df08e47baad27dd51829) uclass_get() returns -EDEADLOCK. Grepping the sources show that only two "boards" use it: 1. arch/x86/cpu/apollolake/Kconfig -> TPL_OF_PLATDATA_INST (configs/chromebook_coral_defconfig and corresponding ./arch/x86/dts/chromebook_coral.dts) 2. configs/sandbox_spl_defconfig -> CONFIG_SPL_OF_PLATDATA_INST=y I would like to ask if: - Anybody managed to use CONFIG_SPL_OF_PLATDATA_INST=y on real HW? - Is it on purpose, that dtoc tool is not extracting structures definitions from *.c files ? - Is the "coral" board (from point 1 above) using any extra coral*-u-boot.dtsi to specify which parts of dts shall be included to the in-TPL DTS? Or is it just using full-blown DTS support ins TPL? I'm using cutting-edge mainline u-boot - SHA1: 6a11fdf0536e02ac9cd4a3da0535a271c694715f Thanks in advance for any help. Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma(a)denx.de

2 1

[PATCH v1 0/6] introduce NVM XIP block storage emulation
by abdellatif.elkhlifi＠arm.com 28 Apr '23

28 Apr '23

From: Abdellatif El Khlifi <abdellatif.elkhlifi(a)arm.com> Adding block storage emulation for NVM XIP flash devices. Some paltforms such as Corstone-1000 need to see NVM XIP raw flash as a block storage device with read only capability. Here NVM flash devices are devices with addressable memory (e.g: QSPI NOR flash). The NVM XIP block storage emulation provides the following features: - Emulate NVM XIP raw flash as a block storage device with read only capability - Being generic by design and can be used by any platform - Device tree node - Platforms can use multiple NVM XIP devices at the same time by defining a DT node for each one of them - A generic NVMXIP block driver allowing to read from the XIP flash - A generic NVMXIP QSPI driver - Implemented on top of memory-mapped IO (using readq macro) - Enabling NVMXIP in sandbox64 - A sandbox test case - Enabling NVMXIP in Corstone1000 platform as a use case For more details please refer to the readme [A]. [A]: doc/develop/driver-model/nvmxip.rst Cheers, Abdellatif Cc: Tom Rini <trini(a)konsulko.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Drew Reed <Drew.Reed(a)arm.com> Cc: Xueliang Zhong <Xueliang.Zhong(a)arm.com> Abdellatif El Khlifi (6): drivers/nvmxip: introduce NVM XIP block storage emulation sandbox64: fix: return unsigned long in readq() sandbox64: add support for NVMXIP QSPI corstone1000: add NVM XIP QSPI device tree node corstone1000: enable NVM XIP QSPI flash sandbox64: add a test case for UCLASS_NVMXIP MAINTAINERS | 8 ++ arch/arm/dts/corstone1000.dtsi | 9 +- arch/sandbox/cpu/cpu.c | 2 +- arch/sandbox/dts/sandbox64.dts | 13 ++ arch/sandbox/dts/test.dts | 14 +++ arch/sandbox/include/asm/io.h | 2 +- configs/corstone1000_defconfig | 1 + configs/sandbox64_defconfig | 1 + doc/develop/driver-model/index.rst | 1 + doc/develop/driver-model/nvmxip.rst | 70 +++++++++++ doc/device-tree-bindings/nvmxip/nvmxip.txt | 56 +++++++++ drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/block/blk-uclass.c | 1 + drivers/nvmxip/Kconfig | 19 +++ drivers/nvmxip/Makefile | 8 ++ drivers/nvmxip/nvmxip-uclass.c | 15 +++ drivers/nvmxip/nvmxip.c | 133 +++++++++++++++++++++ drivers/nvmxip/nvmxip.h | 51 ++++++++ drivers/nvmxip/nvmxip_qspi.c | 67 +++++++++++ include/dm/uclass-id.h | 1 + test/dm/Makefile | 5 + test/dm/nvmxip.c | 117 ++++++++++++++++++ 23 files changed, 594 insertions(+), 3 deletions(-) create mode 100644 doc/develop/driver-model/nvmxip.rst create mode 100644 doc/device-tree-bindings/nvmxip/nvmxip.txt create mode 100644 drivers/nvmxip/Kconfig create mode 100644 drivers/nvmxip/Makefile create mode 100644 drivers/nvmxip/nvmxip-uclass.c create mode 100644 drivers/nvmxip/nvmxip.c create mode 100644 drivers/nvmxip/nvmxip.h create mode 100644 drivers/nvmxip/nvmxip_qspi.c create mode 100644 test/dm/nvmxip.c -- 2.17.1

4 26

[PATCH v2 00/30] ide: Clean up code and fix a few bugs
by Simon Glass 27 Apr '23

27 Apr '23

This code was converted to driver model a long time again but it was a pretty rough conversion. It introduced a few minor bugs, e.g. the device capacity is incorrect and some flags are lost (such as lba48). This series tidies up the code and fixes these bugs. This involves quite a bit of refactoring, so it is done one patch at a time for easier review. Changes in v2: - Drop [] in patch subject - Rebase to master Simon Glass (30): ide: Move ATA_CURR_BASE to C file ide: Use mdelay() for long delays ide: Drop CONFIG_START_IDE ide: Drop init for not using BLK ide: Move ide_init() into probing ide: Drop ide_device_present() ide: Move a few functions further up the file ide: Drop weak functions ide: Create a prototype for ide_set_reset() ide: Correct use of ATAPI ide: Make function static ide: Change the retries variable ide: Refactor confusing loop code ide: Simplify success condition ide: Avoid preprocessor for CONFIG_ATAPI ide: Avoid preprocessor for CONFIG_LBA48 ide: Move bus init into a function ide: Make ide_bus_ok a local variable ide: Move setting of vendor strings into ide_probe() ide: Move ide_init() entirely within ide_probe() ide: Combine the two loops in ide_probe() ide: Use desc consistently for struct blk_desc ide: Make ide_ident() return an error code ide: Move all blk_desc init into ide_ident() ide: Use a single local blk_desc for ide_ident() ide: Correct LBA setting ide: Tidy up ide_reset() ide: Convert to use log_debug() ide: Simplify expressions and hex values ide: Make use of U-Boot types cmd/ide.c | 22 +- common/board_r.c | 17 - drivers/block/ide.c | 841 ++++++++++++++++++++------------------------ include/blk.h | 5 +- include/ide.h | 48 +-- test/boot/bootdev.c | 2 - 6 files changed, 415 insertions(+), 520 deletions(-) -- 2.40.0.634.g4ca3ef3211-goog

2 31