March 2023 - U-Boot

[PATCH] clk: renesas: Pack reset identifier before look up
by Marek Vasut 19 Mar '23

19 Mar '23

The reset identifier must be processed via MOD_CLK_PACK() before it is used to look up register and bit within reset_regs or reset_clear_regs arrays, otherwise completely bogus register and bit is picked from the arrays, one which may even be out of range. Fixes: 326e05c5e21 ("clk: renesas: Add and enable CPG reset driver") Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- drivers/clk/renesas/clk-rcar-gen3.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index d778db6569d..c121d82de7e 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -479,8 +479,9 @@ static int gen3_reset_assert(struct reset_ctl *reset_ctl) { struct udevice *cdev = (struct udevice *)dev_get_driver_data(reset_ctl->dev); struct gen3_clk_priv *priv = dev_get_priv(cdev); - unsigned int reg = reset_ctl->id / 32; - unsigned int bit = reset_ctl->id % 32; + unsigned int packed_id = MOD_CLK_PACK(reset_ctl->id); + unsigned int reg = packed_id / 32; + unsigned int bit = packed_id % 32; u32 bitmask = BIT(bit); writel(bitmask, priv->base + priv->info->reset_regs[reg]); @@ -492,8 +493,9 @@ static int gen3_reset_deassert(struct reset_ctl *reset_ctl) { struct udevice *cdev = (struct udevice *)dev_get_driver_data(reset_ctl->dev); struct gen3_clk_priv *priv = dev_get_priv(cdev); - unsigned int reg = reset_ctl->id / 32; - unsigned int bit = reset_ctl->id % 32; + unsigned int packed_id = MOD_CLK_PACK(reset_ctl->id); + unsigned int reg = packed_id / 32; + unsigned int bit = packed_id % 32; u32 bitmask = BIT(bit); writel(bitmask, priv->base + priv->info->reset_clear_regs[reg]); -- 2.39.2

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[PATCH 00/12] rockchip: Fixes for RK3568 and RK3588 and cleanup
by Jonas Karlman 19 Mar '23

19 Mar '23

This series includes fixes mainly targeted at RK3568 and RK3588: Patch 1 reverts early use of new bootph props in master branch. Patch 2-3 fixes emmc boot on rk3568-rock-3a. Patch 4 fixes reset handler on rk3568. Patch 5 fixes missing return value in rk3588 clk driver. Patch 6-7 fixes sdmmc boot on rk3588-rock-5b. Patch 8 fixes building of tinker-rk3288 with USB or NET disabled. Remaining patches does not fix a real issue and mainly contains cleanup and converts RK35xx to use standard boot. Patch 9 improves return value used when clk_set_rate fails. Patch 10-11 remove dangling comments and an unused define. Patch 12 converts RK3568 and RK3588 to use standard boot. This series builds on top of "rockchip: Use an external TPL binary on RK3588" at [1] that fixes generation of bootable RK3588 firmware images. [1] https://patchwork.ozlabs.org/project/uboot/patch/20230228213822.3583989-1-j… Jonas Karlman (11): rockchip: Fix early use of bootph props rockchip: rk3568: Fix boot device detection rockchip: rk3568-rock-3a: Sync device tree from linux clk: rockchip: rk3588: Fix clk_aux16m in clock driver rockchip: rk3588-rock-5b: Fix sdmmc boot rockchip: rk3588: Add boot device detection rockchip: tinker-rk3288: Use common BOOT_TARGET_DEVICES mmc: rockchip_dw_mmc: Fix get_mmc_clk return value rockchip: include: configs: Remove dangling comments rockchip: include: configs: Remove unused SDRAM_BANK_SIZE rockchip: Convert rk35xx to use standard boot Peter Geis (1): clk: rockchip: rk3568: Fix reset handler arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi | 2 +- arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 2 +- arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 12 +- arch/arm/dts/rk3568-rock-3a.dts | 261 +++++++++++++++++- arch/arm/dts/rk356x-u-boot.dtsi | 2 +- .../dts/rk3588-edgeble-neu6a-io-u-boot.dtsi | 2 +- arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 3 +- arch/arm/dts/rk3588s-u-boot.dtsi | 14 +- arch/arm/mach-rockchip/Kconfig | 6 + arch/arm/mach-rockchip/rk3568/rk3568.c | 2 +- arch/arm/mach-rockchip/rk3588/rk3588.c | 7 + configs/rock5b-rk3588_defconfig | 1 - drivers/clk/rockchip/clk_rk3568.c | 2 + drivers/clk/rockchip/clk_rk3588.c | 4 +- drivers/mmc/rockchip_dw_mmc.c | 2 +- include/configs/evb_rk3328.h | 2 - include/configs/evb_rk3399.h | 2 - include/configs/pinebook-pro-rk3399.h | 2 - include/configs/pinephone-pro-rk3399.h | 2 - include/configs/puma_rk3399.h | 2 - include/configs/px30_common.h | 1 - include/configs/rk3128_common.h | 4 - include/configs/rk3188_common.h | 6 - include/configs/rk322x_common.h | 1 - include/configs/rk3288_common.h | 3 - include/configs/rk3308_common.h | 1 - include/configs/rk3328_common.h | 1 - include/configs/rk3399_common.h | 1 - include/configs/rk3568_common.h | 9 +- include/configs/rk3588_common.h | 9 +- include/configs/roc-pc-rk3399.h | 2 - include/configs/rock960_rk3399.h | 1 - include/configs/rockchip-common.h | 2 - include/configs/rockpro64_rk3399.h | 1 - include/configs/rv1108_common.h | 2 - include/configs/tinker_rk3288.h | 9 - include/configs/vyasa-rk3288.h | 6 - 37 files changed, 309 insertions(+), 82 deletions(-) -- 2.39.2

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[PATCH] rockchip: sdhci: rk3568: fix clock setting logic
by Vasily Khoruzhick 19 Mar '23

19 Mar '23

mmc->tran_speed is max clock, but currently rk3568_sdhci_set_ios_post uses it if its != 0, regardless of mmc->clock value, and it breaks eMMC controller. Without this patch 'mmc dev 0; mmc dev 1; mmc dev 0' is enough for breaking eMMC, since first initialization sets mmc->mmc_tran speed to non-zero value (26MHz in my case), and on subsequent re-init when mmc layer asks for 400KHz it sets 26MHz instead. Fix it by using MAX(mmc->tran_speed, mmc->clock) Signed-off-by: Vasily Khoruzhick <anarsoul(a)gmail.com> --- drivers/mmc/rockchip_sdhci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 9608770d4e..1ac95f32b3 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -394,11 +394,11 @@ static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host) static int rk3568_sdhci_set_ios_post(struct sdhci_host *host) { struct mmc *mmc = host->mmc; - uint clock = mmc->tran_speed; + uint clock = mmc->clock; u32 reg, vendor_reg; - if (!clock) - clock = mmc->clock; + if (mmc->tran_speed && mmc->clock > mmc->tran_speed) + clock = mmc->tran_speed; rk3568_sdhci_emmc_set_clock(host, clock); -- 2.39.2

2 1

[PATCH] pinctrl: rockchip: Fix IO mux selection on RK3568
by Jonas Karlman 19 Mar '23

19 Mar '23

IO mux selection is not working correctly for all pins. Sync mux route data from linux to add any missing and update wrong trigger pins to fix this. Also apply the pull-up fix needed for GPIO0 D3-D6. Fixes: 1977d746aa54 ("rockchip: rk3568: add rk3568 pinctrl driver") Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- drivers/pinctrl/rockchip/pinctrl-rk3568.c | 66 +++++++++++++---------- 1 file changed, 38 insertions(+), 28 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c index 935aed9efc62..314edb5a6064 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3568.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c @@ -13,6 +13,12 @@ #include "pinctrl-rockchip.h" static struct rockchip_mux_route_data rk3568_mux_route_data[] = { + MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(1, 0, 0)), /* PWM0 IO mux selection M0 */ + MR_PMUGRF(RK_GPIO0, RK_PC7, RK_FUNC_2, 0x0110, RK_GENMASK_VAL(1, 0, 1)), /* PWM0 IO mux selection M1 */ + MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(3, 2, 0)), /* PWM1 IO mux selection M0 */ + MR_PMUGRF(RK_GPIO0, RK_PB5, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(3, 2, 1)), /* PWM1 IO mux selection M1 */ + MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(5, 4, 0)), /* PWM2 IO mux selection M0 */ + MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(5, 4, 1)), /* PWM2 IO mux selection M1 */ MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */ MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */ MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */ @@ -33,30 +39,22 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = { MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */ MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */ MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)), /* PWM4 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)), /* PWM4 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)), /* PWM5 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)), /* PWM5 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)), /* PWM6 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)), /* PWM6 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)), /* PWM7 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)), /* PWM7 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_5, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO1, RK_PD6, RK_FUNC_4, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC0, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC6, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */ MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */ MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */ @@ -68,7 +66,7 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = { MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */ MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */ MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */ MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */ MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */ @@ -81,7 +79,7 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = { MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */ MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */ MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */ + MR_TOPGRF(RK_GPIO4, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */ MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */ MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */ MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */ @@ -94,8 +92,11 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = { MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */ MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)), /* PDM IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)), /* PDM IO mux selection M1 */ + MR_TOPGRF(RK_GPIO1, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */ + MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */ + MR_TOPGRF(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 2)), /* PDM IO mux selection M2 */ MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */ MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */ MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */ @@ -237,6 +238,15 @@ static int rk3568_set_pull(struct rockchip_pin_bank *bank, return ret; } + /* + * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, + * where that pull up value becomes 3. + */ + if (bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { + if (ret == 1) + ret = 3; + } + /* enable the write to the equivalent lower bits */ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); -- 2.40.0

1 0

mkimage for Windows?
by Simon Glass 18 Mar '23

18 Mar '23

Hi, Does anyone know how to build mkimage (or other tools) on a Windows host, or at least with a Windows target? Regards, SImon

2 2

[PATCH 1/1] dm: simplify uclass_pre_remove_device
by Heinrich Schuchardt 18 Mar '23

18 Mar '23

Remove a superfluous logical constraint. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- drivers/core/uclass.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index 1762a0796d..dce5b46fc7 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -789,14 +789,10 @@ int uclass_post_probe_device(struct udevice *dev) int uclass_pre_remove_device(struct udevice *dev) { struct uclass *uc; - int ret; uc = dev->uclass; - if (uc->uc_drv->pre_remove) { - ret = uc->uc_drv->pre_remove(dev); - if (ret) - return ret; - } + if (uc->uc_drv->pre_remove) + return uc->uc_drv->pre_remove(dev); return 0; } -- 2.39.2

2 1

[PATCH 0/2] max313xx RTC driver
by Chris Packham 18 Mar '23

18 Mar '23

This series is based on the in-flight linux patch that is adding support for this family of RTCs to linux[1]. The u-boot driver is a bit different due to some of the differences between Linux and u-boot and I've dropped the support for hwmon and clock source functions. Where possible I've tried to keep things such that the U-Boot and Linux versions can be compared and kept in sync. [1] - https://lore.kernel.org/all/20221108122254.1185-2-Ibrahim.Tilki@analog.com/ Chris Packham (2): include: kernel.h: port find_closest() from Linux drivers: rtc: add max313xx series rtc driver drivers/rtc/Kconfig | 8 + drivers/rtc/Makefile | 1 + drivers/rtc/max313xx.c | 442 +++++++++++++++++++++++++++++++++++++++++ include/linux/kernel.h | 24 +++ 4 files changed, 475 insertions(+) create mode 100644 drivers/rtc/max313xx.c -- 2.40.0

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[PATCH 0/9] Enable splash screen
by Nikhil M Jain 18 Mar '23

18 Mar '23

To enable splash screen at SPL stage move video driver and splash screen framework at SPL, which will bring up image on display very quickly and thus have early display support in SPL. Nikhil M Jain (9): drivers: video: Kconfig: Necessary configs for video at SPL drivers: video: tidss: Kconfig: Configs to enable TIDSS at SPL cmd: Kconfig: Add necessary configs for splash screen at SPL drivers: video: Makefile: Compile video driver files at SPL drivers: video: tidss: Makefile: Add condition to compile TIDSS at SPL cmd: Makefile: Add rules to build bmp.c and read.c at SPL common: splash: Enable splash_display at SPL stage drivers: video: video-uclass: Disable u-boot logo at SPL board: ti: am62x: evm: OSPI support for splash screen board/ti/am62x/evm.c | 6 ++++++ cmd/Kconfig | 17 +++++++++++++++++ cmd/Makefile | 2 ++ common/splash.c | 2 +- drivers/video/Kconfig | 32 ++++++++++++++++++++++++++++---- drivers/video/Makefile | 6 ++++++ drivers/video/tidss/Kconfig | 6 ++++++ drivers/video/tidss/Makefile | 1 + drivers/video/video-uclass.c | 2 +- include/splash.h | 2 +- 10 files changed, 69 insertions(+), 7 deletions(-) -- 2.34.1

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[BUG] Devices of uclass BLK are not listed on x86
by Detlev Casanova 18 Mar '23

18 Mar '23

Hello, We have been having an issue with IDE and SCSI drives not being usable on the x86 architecture. After bisecting, it looks like commit f2ebaaa9f38dddddefaf2e616a9fc489fe8b4021 (pci: Handle failed calloc in decode_regions()) is the culprit. Indeed, it was working when decode_regions() was not returning an error. But now that it does, no blk devices get registered anymore. The decode_regions() function fails because it calls "ofnode_get_property", which fails on systems that do not use a device tree Would it make sense to remove calls to anything related to device trees for the x86 platform ? Regards, Detlev.

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[PATCH v2 1/8] rockchip: Drop bootstage stash in TPL and SPL for rockpro64
by Simon Glass 17 Mar '23

17 Mar '23

Unfortunately the IRAM used to stash the bootstage records in TPL becomes inaccessible after SPL runs. Presumably this is because of ATF taking it over. We could move the stash to another address in SPL, before passing it to U-Boot proper. But it seems easier to wait until we have support for standard passage[1] which should not be too far away. For now, disable it in TPL and SPL. [1] https://patchwork.ozlabs.org/project/uboot/cover/ 20220117150428.1580273-1-sjg(a)chromium.org/ Signed-off-by: Simon Glass <sjg(a)chromium.org> Tested-by: Vagrant Cascadian <vagrant(a)debian.org> --- Changes in v2: - Fix 'accessible' typo configs/rockpro64-rk3399_defconfig | 5 ----- 1 file changed, 5 deletions(-) diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index dd67f9dff64..49614236819 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_ROCKPRO64_RK3399=y CONFIG_SPL_STACK=0x400000 -CONFIG_BOOTSTAGE_STASH_ADDR=0xff8e0000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -21,11 +20,7 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_BOOTSTAGE=y -CONFIG_SPL_BOOTSTAGE=y -CONFIG_TPL_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y -CONFIG_SPL_BOOTSTAGE_RECORD_COUNT=10 -CONFIG_BOOTSTAGE_STASH=y CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -- 2.40.0.rc0.216.gc4246ad0f0-goog

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