December 2023 - U-Boot

[PATCH v2 1/6] andes: csr.h: Clean up CSR definition
by Leo Yu-Chi Liang 26 Dec '23

26 Dec '23

Signed-off-by: Leo Yu-Chi Liang <ycliang(a)andestech.com> --- arch/riscv/include/asm/arch-andes/csr.h | 20 ++++++++------------ arch/riscv/include/asm/csr.h | 1 + 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h index 393d51c6dd..12d5eb6f6c 100644 --- a/arch/riscv/include/asm/arch-andes/csr.h +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -12,20 +12,16 @@ #define CSR_MCACHE_CTL 0x7ca #define CSR_MMISC_CTL 0x7d0 -#define CSR_MARCHID 0xf12 #define CSR_MCCTLCOMMAND 0x7cc -#define MCACHE_CTL_IC_EN_OFFSET 0 -#define MCACHE_CTL_DC_EN_OFFSET 1 -#define MCACHE_CTL_CCTL_SUEN_OFFSET 8 -#define MCACHE_CTL_DC_COHEN_OFFSET 19 -#define MCACHE_CTL_DC_COHSTA_OFFSET 20 - -#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET) -#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET) -#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET) -#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET) -#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET) +/* mcache_ctl register */ + +#define MCACHE_CTL_IC_EN BIT(0) +#define MCACHE_CTL_DC_EN BIT(1) +#define MCACHE_CTL_CCTL_SUEN BIT(8) +#define MCACHE_CTL_DC_COHEN BIT(19) +#define MCACHE_CTL_DC_COHSTA BIT(20) + #define CCTL_L1D_WBINVAL_ALL 6 diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 1a15089cae..986f951c31 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -142,6 +142,7 @@ #define CSR_CYCLEH 0xc80 #define CSR_TIMEH 0xc81 #define CSR_INSTRETH 0xc82 +#define CSR_MARCHID 0xf12 #define CSR_MHARTID 0xf14 #ifndef __ASSEMBLY__ -- 2.34.1

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[PATCH 0/2] fix auto-generated boot options
by Masahisa Kojima 26 Dec '23

26 Dec '23

This series aims to get aligned to the EDK II reference implementation for auto-generated boot options, and tries to address the following issue. https://source.denx.de/u-boot/custodians/u-boot-efi/-/issues/13 This series is based on the efi-next-20231217 tag. Masahisa Kojima (2): efi_loader: auto-generate boot option for each blkio device efi_loader: auto-generate removable media boot option first lib/efi_loader/efi_bootmgr.c | 123 +++++++++++++++++++++++++++-------- 1 file changed, 96 insertions(+), 27 deletions(-) -- 2.34.1

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[PATCH v1] reset: npcm: Add support for Nuvoton NPCM BMC family
by Jim Liu 26 Dec '23

26 Dec '23

Add reset controller driver for Nuvoton BMCs. The npcm reset driver not only supports reset each module reset but setting initial value of reset Control Registers. And The driver support each module reset. Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> --- drivers/reset/Kconfig | 7 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-npcm.c | 133 +++++++++++++++++++++++++++++++++++++ 3 files changed, 141 insertions(+) create mode 100644 drivers/reset/reset-npcm.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 73bbd30692..ccd4182682 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -114,6 +114,13 @@ config RESET_MESON help Support for reset controller on Amlogic Meson SoC. +config RESET_NPCM + bool "Reset controller driver for Nuvoton BMCs" + depends on DM_RESET && ARCH_NPCM + default y + help + Support for reset controller on Nuvotom BMCs. + config RESET_SOCFPGA bool "Reset controller driver for SoCFPGA" depends on DM_RESET && ARCH_SOCFPGA diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index e2239a250a..8cc947fc34 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3588.o obj-$(CONFIG_RESET_MESON) += reset-meson.o +obj-$(CONFIG_RESET_NPCM) += reset-npcm.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o diff --git a/drivers/reset/reset-npcm.c b/drivers/reset/reset-npcm.c new file mode 100644 index 0000000000..d8d629b28e --- /dev/null +++ b/drivers/reset/reset-npcm.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2023 Nuvoton Technology Corp. + */ + +#include <dm.h> +#include <reset-uclass.h> +#include <asm/io.h> +#include <dm/device_compat.h> + +struct npcm_reset_priv { + void __iomem *base; +}; + +static int npcm_reset_request(struct reset_ctl *rst) +{ + return 0; +} + +static int npcm_reset_free(struct reset_ctl *rst) +{ + return 0; +} + +static int npcm_reset_assert(struct reset_ctl *rst) +{ + struct npcm_reset_priv *priv = dev_get_priv(rst->dev); + u32 val; + + debug("%s: id 0x%lx, data %ld\n", __func__, rst->id, rst->data); + val = readl(priv->base + rst->id); + val |= BIT(rst->data); + writel(val, priv->base + rst->id); + + return 0; +} + +static int npcm_reset_deassert(struct reset_ctl *rst) +{ + struct npcm_reset_priv *priv = dev_get_priv(rst->dev); + u32 val; + + debug("%s: id 0x%lx, data %ld\n", __func__, rst->id, rst->data); + val = readl(priv->base + rst->id); + val &= ~BIT(rst->data); + writel(val, priv->base + rst->id); + + return 0; +} + +static int npcm_reset_xlate(struct reset_ctl *rst, + struct ofnode_phandle_args *args) +{ + if (args->args_count != 2) { + dev_err(rst->dev, "Invalid args_count: %d\n", args->args_count); + return -EINVAL; + } + + /* Use id field as register offset and data field as reset bit positiion */ + rst->id = args->args[0]; + rst->data = args->args[1]; + + return 0; +} + +static int npcm_reset_bind(struct udevice *dev) +{ + struct npcm_reset_priv *priv = dev_get_priv(dev); + u32 *rcr_values; + int num_fields; + u32 reg, val; + int ret, i; + + priv->base = dev_remap_addr(dev); + if (!priv->base) + return -EINVAL; + + /* + * Set RCR initial value + * The rcr-initial-values cell is <reg_offset val> + */ + num_fields = dev_read_size(dev, "rcr-initial-values"); + if (num_fields < 2) + return 0; + + num_fields /= sizeof(u32); + if (num_fields % 2) + return -EINVAL; + + num_fields = num_fields / 2; + rcr_values = malloc(num_fields * 2 * sizeof(u32)); + if (!rcr_values) + return -ENOMEM; + + ret = dev_read_u32_array(dev, "rcr-initial-values", rcr_values, + num_fields * 2); + if (ret < 0) { + free(rcr_values); + return -EINVAL; + } + + for (i = 0; i < num_fields; i++) { + reg = rcr_values[2 * i]; + val = rcr_values[2 * i + 1]; + writel(val, priv->base + reg); + } + free(rcr_values); + + return 0; +} + +static const struct udevice_id npcm_reset_ids[] = { + { .compatible = "nuvoton,npcm845-reset" }, + { .compatible = "nuvoton,npcm750-reset" }, + { } +}; + +struct reset_ops npcm_reset_ops = { + .request = npcm_reset_request, + .rfree = npcm_reset_free, + .rst_assert = npcm_reset_assert, + .rst_deassert = npcm_reset_deassert, + .of_xlate = npcm_reset_xlate, +}; + +U_BOOT_DRIVER(npcm_reset) = { + .name = "npcm_reset", + .id = UCLASS_RESET, + .of_match = npcm_reset_ids, + .bind = npcm_reset_bind, + .ops = &npcm_reset_ops, + .priv_auto = sizeof(struct npcm_reset_priv), +}; -- 2.25.1

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[PATCH RFC] dt-bindings: nvmem: u-boot, env: add any-name MAC cells compatible
by Rafał Miłecki 25 Dec '23

25 Dec '23

From: Rafał Miłecki <rafal(a)milecki.pl> So far we had a property for "ethaddr" NVMEM cell containing base Ethernet MAC address. The problem is vendors often pick non-standard names for storing MAC(s) (other than "ethaddr"). A few names were noticed over years: 1. "wanaddr" (Edimax, ELECOM, EnGenius, I-O DATA, Sitecom) 2. "et1macaddr" (ASUS) 3. "eth1addr" (Buffalo) 4. "athaddr" (EnGenius) 5. "baseMAC" (Netgear) 6. "mac" (Netgear) 7. "mac_addr" (Moxa) and more ("HW_LAN_MAC", "HW_WAN_MAC", "INIC_MAC_ADDR", "LAN_MAC_ADDR", "RADIOADDR0", "RADIOADDR1", "WAN_MAC_ADDR", "lan1_mac_addr", "wanmac", "wmac1", "wmac2"). It doesn't make sense to add property for every possible MAC cell name. Instead allow specifying cells with "mac" compatible. Signed-off-by: Rafał Miłecki <rafal(a)milecki.pl> --- List of devices and their U-Boot MAC variables: alphanetworks,asl56026) wanmac asus,rt-ac65p) et1macaddr asus,rt-ac85p) et1macaddr belkin,f9k1109v1) HW_WAN_MAC + HW_LAN_MAC buffalo,ls220de) eth1addr buffalo,ls421de) eth1addr checkpoint,l-50) lan1_mac_addr dovado,tiny-ac) INIC_MAC_ADDR dovado,tiny-ac) LAN_MAC_ADDR + WAN_MAC_ADDR edimax,ra21s) wanaddr edimax,rg21s) wanaddr elecom,wrc-2533ghbk-i) wanaddr elecom,wrc-2533ghbk2-t) wanaddr engenius,ecb1200) athaddr engenius,ecb1750) athaddr engenius,epg5000) wanaddr engenius,epg600) wanaddr engenius,esr1200) wanaddr engenius,esr1750) wanaddr engenius,esr600) wanaddr engenius,esr600h) wanaddr engenius,esr900) wanaddr enterasys,ws-ap3705i) RADIOADDR0 + RADIOADDR1 iodata,wn-ac1167dgr) wanaddr iodata,wn-ac1167gr) wanaddr iodata,wn-ac1600dgr) wanaddr iodata,wn-ac1600dgr2) wanaddr iodata,wn-ac733gr3) wanaddr iodata,wn-ag300dgr) wanaddr iodata,wnpr2600g) wanaddr moxa,awk-1137c) mac_addr netgear,wax220) mac netgear,wndap620) baseMAC netgear,wndap660) baseMAC ocedo,panda) wmac1 + wmac2 sitecom,wlr-7100) wanaddr sitecom,wlr-8100) wanaddr .../devicetree/bindings/nvmem/u-boot,env.yaml | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/Documentation/devicetree/bindings/nvmem/u-boot,env.yaml b/Documentation/devicetree/bindings/nvmem/u-boot,env.yaml index 0006f022d0af..68214b96f5c9 100644 --- a/Documentation/devicetree/bindings/nvmem/u-boot,env.yaml +++ b/Documentation/devicetree/bindings/nvmem/u-boot,env.yaml @@ -67,6 +67,34 @@ properties: description: The first argument is a MAC address offset. const: 1 +patternProperties: + ".*": + allOf: + - if: + type: object + then: + properties: + compatible: + enum: + - mac + - if: + properties: + compatible: + contains: + const: mac + then: + description: + Ethernet interfaces base MAC address. + + properties: + compatible: true + + "#nvmem-cell-cells": + description: The first argument is a MAC address offset. + const: 1 + + additionalProperties: false + additionalProperties: false examples: @@ -90,6 +118,11 @@ examples: mac: ethaddr { #nvmem-cell-cells = <1>; }; + + wanaddr { + compatible = "mac"; + #nvmem-cell-cells = <1>; + }; }; }; - | -- 2.35.3

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[PATCH 1/5] andes: csr.h: Clean up CSR definition
by Leo Yu-Chi Liang 25 Dec '23

25 Dec '23

Signed-off-by: Leo Yu-Chi Liang <ycliang(a)andestech.com> --- arch/riscv/include/asm/arch-andes/csr.h | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h index 393d51c6dd..93aa8b2343 100644 --- a/arch/riscv/include/asm/arch-andes/csr.h +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -15,17 +15,14 @@ #define CSR_MARCHID 0xf12 #define CSR_MCCTLCOMMAND 0x7cc -#define MCACHE_CTL_IC_EN_OFFSET 0 -#define MCACHE_CTL_DC_EN_OFFSET 1 -#define MCACHE_CTL_CCTL_SUEN_OFFSET 8 -#define MCACHE_CTL_DC_COHEN_OFFSET 19 -#define MCACHE_CTL_DC_COHSTA_OFFSET 20 - -#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET) -#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET) -#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET) -#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET) -#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET) +/* mcache_ctl register */ + +#define MCACHE_CTL_IC_EN BIT(0) +#define MCACHE_CTL_DC_EN BIT(1) +#define MCACHE_CTL_CCTL_SUEN BIT(8) +#define MCACHE_CTL_DC_COHEN BIT(19) +#define MCACHE_CTL_DC_COHSTA BIT(20) + #define CCTL_L1D_WBINVAL_ALL 6 -- 2.34.1

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[PATCH v4 0/1] efi: Minor improvements for the EFI app
by Simon Glass 25 Dec '23

25 Dec '23

This series collects a few fixes and improvements useful when booting U-Boot as an EFI app. Changes in v4: - Create a new file inside lib/efi instead of board/ Changes in v2: - Drop duplicate acpi_xsdt patch - Put the board_early_init_r code into board/ Simon Glass (1): efi: Avoid using dm_scan_other() configs/efi-x86_app64_defconfig | 1 + lib/efi/Makefile | 2 +- lib/efi/efi_app.c | 187 ----------------------------- lib/efi/efi_app_init.c | 205 ++++++++++++++++++++++++++++++++ 4 files changed, 207 insertions(+), 188 deletions(-) create mode 100644 lib/efi/efi_app_init.c -- 2.43.0.472.g3155946c3a-goog

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[PATCH] rockchip: rk35xx: expand space for decompressed kernel
by Hugh Cole-Baker 23 Dec '23

23 Dec '23

An uncompressed 6.7.0-rc1 Linux kernel Image built with the arm64 defconfig is about 40MB. This does not fit in to the space between kernel_comp_addr_r and fdt_addr_r, so when uncompressing an Image.gz to this size, the FDT will be overwritten. Move fdt_addr_r and ramdisk_addr_r higher in memory to allow 96MB for uncompressing kernels. Signed-off-by: Hugh Cole-Baker <sigmaris(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Philipp Tomsich <philipp.tomsich(a)vrull.eu> Cc: Kever Yang <kever.yang(a)rock-chips.com> Cc: Jonas Karlman <jonas(a)kwiboo.se> --- include/configs/rk3568_common.h | 4 ++-- include/configs/rk3588_common.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index 1b7d3437b1..da5b38803e 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -20,10 +20,10 @@ "script_offset_f=0xffe000\0" \ "script_size_f=0x2000\0" \ "pxefile_addr_r=0x00e00000\0" \ - "fdt_addr_r=0x0a100000\0" \ + "fdt_addr_r=0x0e000000\0" \ "fdtoverlay_addr_r=0x02000000\0" \ "kernel_addr_r=0x02080000\0" \ - "ramdisk_addr_r=0x0a200000\0" \ + "ramdisk_addr_r=0x0e100000\0" \ "kernel_comp_addr_r=0x08000000\0" \ "kernel_comp_size=0x2000000\0" diff --git a/include/configs/rk3588_common.h b/include/configs/rk3588_common.h index 46389d087d..5fdbdb6fd7 100644 --- a/include/configs/rk3588_common.h +++ b/include/configs/rk3588_common.h @@ -19,10 +19,10 @@ "script_offset_f=0xffe000\0" \ "script_size_f=0x2000\0" \ "pxefile_addr_r=0x00e00000\0" \ - "fdt_addr_r=0x0a100000\0" \ + "fdt_addr_r=0x0e000000\0" \ "fdtoverlay_addr_r=0x02000000\0" \ "kernel_addr_r=0x02080000\0" \ - "ramdisk_addr_r=0x0a200000\0" \ + "ramdisk_addr_r=0x0e100000\0" \ "kernel_comp_addr_r=0x08000000\0" \ "kernel_comp_size=0x2000000\0" -- 2.39.3 (Apple Git-145)

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[PATCH v1 0/3] Revive TEGRA_SUPPORT_NON_SECURE
by Svyatoslav Ryhel 23 Dec '23

23 Dec '23

Revive TEGRA_SUPPORT_NON_SECURE used for T124 and adapt it to be used on T114 as well. Nonsecure state detection used on T124 works on T114 as well, tested by me personally on tegratab. Svyatoslav Ryhel (3): ARM: tegra124: convert TEGRA_SUPPORT_NON_SECURE into Kconfig ARM: tegra114: expand MC register map ARM: tegra114: support nonsecure state detection README | 7 ------ arch/arm/include/asm/arch-tegra114/mc.h | 29 +++++++++++++++++++++++-- arch/arm/mach-tegra/Kconfig | 7 ++++++ arch/arm/mach-tegra/board.c | 3 --- 4 files changed, 34 insertions(+), 12 deletions(-) -- 2.40.1

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[PATCH 00/14] pxe: Allow extlinux booting without CMDLINE enabled
by Simon Glass 23 Dec '23

23 Dec '23

This series is the culmanation of the current line of refactoring series. It adjusts pxe to call the booting functionality directly rather than going through the command-line interface. With this is is possible to boot using the extlinux bootmeth without the command line enabled. It also updates fastboot to do a similar thing. This is cmdf (part f of CMDLINE refactoring) It depends on dm/cmde-working which depends on dm/cmdd-working which depends on dm/bootstda-working which depends on dm/cmdc-working Simon Glass (14): boot: Reorder FIT and BOOTSTD to be first bootm: Add a Kconfig option for bootm functionality bootm: Make OS booting dependent on BOOTM treewide: Make arch-specific bootm code depend on BOOTM boot: Update SYS_BOOTM_LEN to depend on BOOTM fastboot: Change fastboot_buf_addr to an address bootm: Make cmdline optional with bootm_boot_start() fastboot: Remove dependencies on CMDLINE pxe: Refactor to reduce the size of label_boot() pxe: Refactor to avoid over-using bootm_argv pxe: Move calculation of FDT file into a function pxe: Allow booting without CMDLINE for bootm methods pxe: Allow booting without CMDLINE for the zboot method x86: Drop message about features being missing with 64-bit arch/arc/lib/Makefile | 2 +- arch/arm/lib/Makefile | 2 +- arch/m68k/lib/Makefile | 2 +- arch/microblaze/lib/Makefile | 2 +- arch/mips/lib/Makefile | 2 +- arch/nios2/lib/Makefile | 2 +- arch/powerpc/lib/Makefile | 2 +- arch/riscv/lib/Makefile | 2 +- arch/sandbox/lib/Makefile | 2 +- arch/sh/lib/Makefile | 2 +- arch/x86/lib/Makefile | 2 +- arch/x86/lib/spl.c | 2 +- arch/xtensa/lib/Makefile | 2 +- boot/Kconfig | 99 ++++- boot/Makefile | 2 +- boot/bootm.c | 10 +- boot/pxe_utils.c | 361 ++++++++++-------- cmd/Kconfig | 50 +-- cmd/fastboot.c | 2 +- configs/colibri_vf_defconfig | 2 +- configs/iot_devkit_defconfig | 2 +- configs/mx6memcal_defconfig | 2 +- configs/tools-only_defconfig | 2 +- configs/xilinx_versal_mini_defconfig | 2 +- configs/xilinx_versal_mini_emmc0_defconfig | 2 +- configs/xilinx_versal_mini_emmc1_defconfig | 2 +- configs/xilinx_versal_mini_ospi_defconfig | 2 +- configs/xilinx_versal_mini_qspi_defconfig | 2 +- configs/xilinx_versal_net_mini_defconfig | 2 +- configs/xilinx_versal_net_mini_emmc_defconfig | 2 +- configs/xilinx_versal_net_mini_ospi_defconfig | 2 +- configs/xilinx_versal_net_mini_qspi_defconfig | 2 +- configs/xilinx_zynqmp_mini_defconfig | 2 +- configs/xilinx_zynqmp_mini_emmc0_defconfig | 2 +- configs/xilinx_zynqmp_mini_emmc1_defconfig | 2 +- configs/xilinx_zynqmp_mini_nand_defconfig | 2 +- .../xilinx_zynqmp_mini_nand_single_defconfig | 2 +- configs/xilinx_zynqmp_mini_qspi_defconfig | 2 +- configs/zynq_cse_nand_defconfig | 2 +- configs/zynq_cse_nor_defconfig | 2 +- configs/zynq_cse_qspi_defconfig | 2 +- doc/board/emulation/qemu-x86.rst | 2 +- drivers/fastboot/Kconfig | 1 - drivers/fastboot/fb_command.c | 13 +- drivers/fastboot/fb_common.c | 37 +- include/bootm.h | 2 +- include/fastboot-internal.h | 2 +- include/fastboot.h | 6 +- 48 files changed, 352 insertions(+), 305 deletions(-) -- 2.43.0.rc2.451.g8631bc7472-goog

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[PATCH v4] arch: arm: Kconfig: Enable BOOTSTD_FULL for Rockchip SoCs
by Shantur Rathore 23 Dec '23

23 Dec '23

Rockchip SoCs can support wide range of bootflows. Without full bootflow commands, it can be difficult to figure out issues if any, hence enable by default. Reviewed-by: Simon Glass <sjg(a)chromium.org> Signed-off-by: Shantur Rathore <i(a)shantur.com> --- Changes in v4: - Replace BOOTSTD_DEFAULT with BOOTSTD_FULL as previous version didn't work on next arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d812685c98..a0265b36ad 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1985,7 +1985,7 @@ config ARCH_ROCKCHIP imply ADC imply CMD_DM imply DEBUG_UART_BOARD_INIT - imply BOOTSTD_DEFAULTS + imply BOOTSTD_FULL imply FAT_WRITE imply SARADC_ROCKCHIP imply SPL_SYSRESET -- 2.40.1

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