December 2023 - U-Boot

[PATCH] sbp1: Add support for IBM SBP1 board
by Naresh Solanki 03 Jan '24

03 Jan '24

From: Patrick Rudolph <patrick.rudolph(a)9elements.com> Add defconfig & devicetree for IBM SBP1 board BMC based on AST2600 SoC. Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- Changes: - Update MAINTAINERS --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/ast2600-sbp1.dts | 96 ++++++++++++++++++++ board/aspeed/evb_ast2600/MAINTAINERS | 1 + configs/ibm-sbp1_defconfig | 126 +++++++++++++++++++++++++++ 4 files changed, 226 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/ast2600-sbp1.dts create mode 100644 configs/ibm-sbp1_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1be08c5fdc..85514fb8ba 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1353,7 +1353,9 @@ dtb-$(CONFIG_BCM6878) += \ bcm96878.dtb dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb -dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb +dtb-$(CONFIG_ASPEED_AST2600) += \ + ast2600-evb.dtb \ + ast2600-sbp1.dtb dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb diff --git a/arch/arm/dts/ast2600-sbp1.dts b/arch/arm/dts/ast2600-sbp1.dts new file mode 100644 index 0000000000..5c862e2c1c --- /dev/null +++ b/arch/arm/dts/ast2600-sbp1.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "ast2600-evb.dts" + +/ { + model = "IBM SBP1"; + compatible = "ibm,sbp1-bmc", "aspeed,ast2600"; + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + chosen { + stdout-path = &uart1; + }; + + aliases { + mmc0 = &emmc; + mmc1 = &sdhci0; + mmc2 = &sdhci1; + ethernet0 = &mac2; + ethernet1 = &mac3; + }; + + cpus { + cpu@0 { + clock-frequency = <1200000000>; + }; + cpu@1 { + clock-frequency = <1200000000>; + }; + }; + +}; + +&uart1 { + bootph-all; + status = "okay"; +}; + +&uart5 { + status = "disabled"; +}; + +&mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio3_default &pinctrl_mdio4_default>; +}; + +&mac0 { + status = "disabled"; +}; + +&mac1 { + status = "disabled"; +}; + +&gpio0 { + status = "okay"; + line_50 { + gpio-hog; + gpios = <50 GPIO_ACTIVE_LOW>; + output-low; + line-name = "BMC_MAC1_RESET_N"; + }; + line_175 { + gpio-hog; + gpios = <175 GPIO_ACTIVE_LOW>; + output-low; + line-name = "BMC_MAC0_RESET_N"; + }; +}; + +&spi1 { + status = "disabled"; +}; + +&spi2 { + status = "disabled"; +}; + +&emmc { + status = "disabled"; +}; + +&sdhci0 { + status = "disabled"; +}; + +&sdhci1 { + status = "disabled"; +}; diff --git a/board/aspeed/evb_ast2600/MAINTAINERS b/board/aspeed/evb_ast2600/MAINTAINERS index e83aae5d6a..5368e8ee5f 100644 --- a/board/aspeed/evb_ast2600/MAINTAINERS +++ b/board/aspeed/evb_ast2600/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/aspeed/evb_ast2600/ F: include/configs/evb_ast2600.h F: configs/evb-ast2600_defconfig +F: configs/ibm-sbp1_defconfig diff --git a/configs/ibm-sbp1_defconfig b/configs/ibm-sbp1_defconfig new file mode 100644 index 0000000000..cf667217cc --- /dev/null +++ b/configs/ibm-sbp1_defconfig @@ -0,0 +1,126 @@ +CONFIG_ARM=y +CONFIG_SYS_DCACHE_OFF=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_SPL_SYS_THUMB_BUILD=y +CONFIG_ARCH_ASPEED=y +CONFIG_TEXT_BASE=0x80000000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x800 +CONFIG_ASPEED_AST2600=y +CONFIG_TARGET_EVB_AST2600=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_LDSCRIPT="arch/arm/mach-aspeed/ast2600/u-boot-spl.lds" +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0xe0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="ast2600-sbp1" +CONFIG_DM_RESET=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x83000000 +CONFIG_SPL_SIZE_LIMIT=0x10000 +CONFIG_SPL=y +# CONFIG_ARMV7_NONSEC is not set +CONFIG_SYS_LOAD_ADDR=0x83000000 +CONFIG_SPL_PAYLOAD="u-boot.img" +CONFIG_BUILD_TARGET="u-boot-with-spl.bin" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_FIT=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200n8 root=/dev/ram rw earlycon" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run bootspi" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x83000000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000000 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_FIT_IMAGE_TINY=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_BOOTP_BOOTFILESIZE=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_NCSI=y +CONFIG_CMD_EXT4=y +CONFIG_DOS_PARTITION=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SECT_SIZE_AUTO=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ASPEED_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_ASPEED=y +CONFIG_I2C_EEPROM=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ASPEED=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_REALTEK=y +CONFIG_PHY_NCSI=y +CONFIG_DM_MDIO=y +CONFIG_FTGMAC100=y +CONFIG_ASPEED_MDIO=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SPI_DIRMAP=y +CONFIG_SPI_ASPEED_SMC=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_WDT=y +CONFIG_SHA384=y +CONFIG_SPL_CRC32=y +CONFIG_HEXDUMP=y +# CONFIG_EFI_LOADER is not set +CONFIG_PHANDLE_CHECK_SEQ=y -- 2.41.0

3 5

Setting up boot chain ACPI on ARM with STM32MPU
by Ba Gia Bao Phan 02 Jan '24

02 Jan '24

Hello everyone, I am a trainee at STMicroelectronics France. I am working on a project "Setting up a boot chain ACPI" for STM32MPU, which is based on ARM Cortex-A . The objective of my project is to add a way of booting (with ACPI) besides Device Tree available on STM32MPU. I found that ACPI was enabled on some x86 platforms but I don't know whether it was set up on ARM or not. I found a PATCH that discussed* Enabling ACPI booting on ARM with Raspberry Pi 4 <https://lore.kernel.org/all/20211201160315.2203099-1-sjg@chromium.org/T/#m3…> *but I don't know if it functioned or not. Did anyone here succeed in setting up ACPI on ARM by U-boot? What are the differences between x86 and ARM platforms when enabling ACPI? The architecture of my board STM32PMU is ARM so can I apply the technique used on platform x86 for my board?

4 8

[PATCH 0/7] Add SE HMBSC board support
by Sumit Garg 02 Jan '24

02 Jan '24

SE HMIBSC board is based on Qcom APQ8016 SoC. One of the major difference from db410c is serial port where HMIBSC board uses UART1 as the debug console with an RS232 port, patch #1 - #3 adds corresponding driver support. Patch #4 adds main HMIBSC board specific bits, features: - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306) - 2GiB RAM - 64GiB eMMC, SD slot - WiFi and Bluetooth - 2x Host, 1x Device USB port - HDMI - Discrete TPM2 chip over SPI Patch #5 - #7 enables specific board features like RAUC support, environment protection and USB networking support. This patch series is based on top of Qcom maintainer tree [1] + the latest PMIC patch-set [2]. Feedback is very much welcome. [1] https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/u-boot… [2] https://patchwork.ozlabs.org/project/uboot/list/?series=385322 Sumit Garg (7): clk: apq8016: Add support for UART1 clocks serial_msm: Add support for RS232 GPIOs serial_msm: Enable RS232 flow control board: Add SE HMIBSC board support hmibsc: Enable RAUC support hmibsc: enable U-Boot Environment variables protection hmibsc: Enable LAN75XX USB ethernet driver arch/arm/dts/Makefile | 1 + arch/arm/dts/hmibsc-uboot.dtsi | 43 +++++++ arch/arm/dts/hmibsc.dts | 188 +++++++++++++++++++++++++++++ arch/arm/mach-snapdragon/Kconfig | 18 +++ arch/arm/mach-snapdragon/Makefile | 1 + board/schneider/hmibsc/Kconfig | 15 +++ board/schneider/hmibsc/MAINTAINERS | 6 + board/schneider/hmibsc/Makefile | 5 + board/schneider/hmibsc/hmibsc.c | 179 +++++++++++++++++++++++++++ board/schneider/hmibsc/hmibsc.env | 11 ++ configs/hmibsc_defconfig | 79 ++++++++++++ drivers/clk/qcom/clock-apq8016.c | 44 ++++++- drivers/serial/serial_msm.c | 23 +++- drivers/usb/host/Kconfig | 1 + include/configs/hmibsc.h | 59 +++++++++ 15 files changed, 665 insertions(+), 8 deletions(-) create mode 100644 arch/arm/dts/hmibsc-uboot.dtsi create mode 100644 arch/arm/dts/hmibsc.dts create mode 100644 board/schneider/hmibsc/Kconfig create mode 100644 board/schneider/hmibsc/MAINTAINERS create mode 100644 board/schneider/hmibsc/Makefile create mode 100644 board/schneider/hmibsc/hmibsc.c create mode 100644 board/schneider/hmibsc/hmibsc.env create mode 100644 configs/hmibsc_defconfig create mode 100644 include/configs/hmibsc.h -- 2.34.1

3 19

[PATCH v1] arm: dts: rockchip: rk3288: move to 64 bit reg size
by Johan Jonker 02 Jan '24

02 Jan '24

To make automatic Rockchip DT syncing possible from Linux to U-boot prepare rk3288.dtsi by moving to 64 bit reg size. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- arch/arm/dts/rk3288-evb.dtsi | 2 +- arch/arm/dts/rk3288-firefly.dtsi | 2 +- arch/arm/dts/rk3288-miqi.dtsi | 2 +- arch/arm/dts/rk3288-phycore-som.dtsi | 2 +- arch/arm/dts/rk3288-popmetal.dtsi | 2 +- arch/arm/dts/rk3288-rock2-som.dtsi | 2 +- arch/arm/dts/rk3288-tinker.dtsi | 2 +- arch/arm/dts/rk3288-u-boot.dtsi | 14 +- arch/arm/dts/rk3288-veyron.dtsi | 2 +- arch/arm/dts/rk3288.dtsi | 259 +++++++++++++++------------ arch/arm/mach-rockchip/Kconfig | 1 + 11 files changed, 165 insertions(+), 125 deletions(-) diff --git a/arch/arm/dts/rk3288-evb.dtsi b/arch/arm/dts/rk3288-evb.dtsi index 72da8847344c..0e347beb154d 100644 --- a/arch/arm/dts/rk3288-evb.dtsi +++ b/arch/arm/dts/rk3288-evb.dtsi @@ -7,7 +7,7 @@ / { memory { - reg = <0 0x80000000>; + reg = <0x0 0x0 0x0 0x80000000>; }; ext_gmac: external-gmac-clock { diff --git a/arch/arm/dts/rk3288-firefly.dtsi b/arch/arm/dts/rk3288-firefly.dtsi index 1117d3913ed7..0824b19ee642 100644 --- a/arch/arm/dts/rk3288-firefly.dtsi +++ b/arch/arm/dts/rk3288-firefly.dtsi @@ -7,7 +7,7 @@ / { memory { - reg = <0 0x80000000>; + reg = <0x0 0x0 0x0 0x80000000>; }; ext_gmac: external-gmac-clock { diff --git a/arch/arm/dts/rk3288-miqi.dtsi b/arch/arm/dts/rk3288-miqi.dtsi index 00c8613d6d73..c56e1109e3ac 100644 --- a/arch/arm/dts/rk3288-miqi.dtsi +++ b/arch/arm/dts/rk3288-miqi.dtsi @@ -8,7 +8,7 @@ / { memory { device_type = "memory"; - reg = <0 0x80000000>; + reg = <0x0 0x0 0x0 0x80000000>; }; ext_gmac: external-gmac-clock { diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi index 70c00308d736..bde5910ff625 100644 --- a/arch/arm/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/dts/rk3288-phycore-som.dtsi @@ -55,7 +55,7 @@ */ memory { device_type = "memory"; - reg = <0 0x8000000>; + reg = <0x0 0x0 0x0 0x80000000>; }; aliases { diff --git a/arch/arm/dts/rk3288-popmetal.dtsi b/arch/arm/dts/rk3288-popmetal.dtsi index d732a70678ba..ecff641b1099 100644 --- a/arch/arm/dts/rk3288-popmetal.dtsi +++ b/arch/arm/dts/rk3288-popmetal.dtsi @@ -44,7 +44,7 @@ / { memory{ device_type = "memory"; - reg = <0 0x80000000>; + reg = <0x0 0x0 0x0 0x80000000>; }; ext_gmac: external-gmac-clock { diff --git a/arch/arm/dts/rk3288-rock2-som.dtsi b/arch/arm/dts/rk3288-rock2-som.dtsi index 1ece66f3e162..58e32fbb80f6 100644 --- a/arch/arm/dts/rk3288-rock2-som.dtsi +++ b/arch/arm/dts/rk3288-rock2-som.dtsi @@ -43,7 +43,7 @@ / { memory { - reg = <0x0 0x80000000>; + reg = <0x0 0x0 0x0 0x80000000>; device_type = "memory"; }; diff --git a/arch/arm/dts/rk3288-tinker.dtsi b/arch/arm/dts/rk3288-tinker.dtsi index 46460ae455e2..62b4beb25100 100644 --- a/arch/arm/dts/rk3288-tinker.dtsi +++ b/arch/arm/dts/rk3288-tinker.dtsi @@ -44,7 +44,7 @@ / { memory { device_type = "memory"; - reg = <0x0 0x80000000>; + reg = <0x0 0x0 0x0 0x80000000>; }; ext_gmac: external-gmac-clock { diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index c4c5a2d225c4..a43d320ade7b 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -29,10 +29,10 @@ dmc: dmc@ff610000 { compatible = "rockchip,rk3288-dmc", "syscon"; - reg = <0xff610000 0x3fc - 0xff620000 0x294 - 0xff630000 0x3fc - 0xff640000 0x294>; + reg = <0x0 0xff610000 0x0 0x3fc + 0x0 0xff620000 0x0 0x294 + 0x0 0xff630000 0x0 0x3fc + 0x0 0xff640000 0x0 0x294>; clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>, <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>, <&cru ARMCLK>; @@ -50,7 +50,7 @@ noc: syscon@ffac0000 { compatible = "rockchip,rk3288-noc", "syscon"; - reg = <0xffac0000 0x2000>; + reg = <0x0 0xffac0000 0x0 0x2000>; bootph-all; }; }; @@ -134,3 +134,7 @@ &vopl { bootph-all; }; + +&xin24m { + bootph-all; +}; diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi index 434b0d494e5e..99406151bf59 100644 --- a/arch/arm/dts/rk3288-veyron.dtsi +++ b/arch/arm/dts/rk3288-veyron.dtsi @@ -11,7 +11,7 @@ / { memory { - reg = <0x0 0x80000000>; + reg = <0x0 0x0 0x0 0x80000000>; }; chosen { diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index dd1d989793fd..ead343dc3df1 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -10,8 +10,8 @@ #include <dt-bindings/soc/rockchip,boot-mode.h> / { - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; compatible = "rockchip,rk3288"; @@ -19,6 +19,15 @@ aliases { ethernet0 = &gmac; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + gpio8 = &gpio8; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -155,8 +164,8 @@ }; reserved-memory { - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; /* @@ -170,7 +179,7 @@ * is found. */ dma-unusable@fe000000 { - reg = <0xfe000000 0x1000000>; + reg = <0x0 0xfe000000 0x0 0x1000000>; }; }; @@ -213,7 +222,7 @@ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xff0c0000 0x4000>; + reg = <0x0 0xff0c0000 0x0 0x4000>; resets = <&cru SRST_MMC0>; reset-names = "reset"; status = "disabled"; @@ -227,7 +236,7 @@ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xff0d0000 0x4000>; + reg = <0x0 0xff0d0000 0x0 0x4000>; resets = <&cru SRST_SDIO0>; reset-names = "reset"; status = "disabled"; @@ -241,7 +250,7 @@ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xff0e0000 0x4000>; + reg = <0x0 0xff0e0000 0x0 0x4000>; resets = <&cru SRST_SDIO1>; reset-names = "reset"; status = "disabled"; @@ -255,7 +264,7 @@ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xff0f0000 0x4000>; + reg = <0x0 0xff0f0000 0x0 0x4000>; resets = <&cru SRST_EMMC>; reset-names = "reset"; status = "disabled"; @@ -263,7 +272,7 @@ saradc: saradc@ff100000 { compatible = "rockchip,saradc"; - reg = <0xff100000 0x100>; + reg = <0x0 0xff100000 0x0 0x100>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; @@ -282,7 +291,7 @@ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; - reg = <0xff110000 0x1000>; + reg = <0x0 0xff110000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -297,7 +306,7 @@ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; - reg = <0xff120000 0x1000>; + reg = <0x0 0xff120000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -312,7 +321,7 @@ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; - reg = <0xff130000 0x1000>; + reg = <0x0 0xff130000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -320,7 +329,7 @@ i2c1: i2c@ff140000 { compatible = "rockchip,rk3288-i2c"; - reg = <0xff140000 0x1000>; + reg = <0x0 0xff140000 0x0 0x1000>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -333,7 +342,7 @@ i2c3: i2c@ff150000 { compatible = "rockchip,rk3288-i2c"; - reg = <0xff150000 0x1000>; + reg = <0x0 0xff150000 0x0 0x1000>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -346,7 +355,7 @@ i2c4: i2c@ff160000 { compatible = "rockchip,rk3288-i2c"; - reg = <0xff160000 0x1000>; + reg = <0x0 0xff160000 0x0 0x1000>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -359,7 +368,7 @@ i2c5: i2c@ff170000 { compatible = "rockchip,rk3288-i2c"; - reg = <0xff170000 0x1000>; + reg = <0x0 0xff170000 0x0 0x1000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -372,7 +381,7 @@ uart0: serial@ff180000 { compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0xff180000 0x100>; + reg = <0x0 0xff180000 0x0 0x100>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; @@ -387,7 +396,7 @@ uart1: serial@ff190000 { compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0xff190000 0x100>; + reg = <0x0 0xff190000 0x0 0x100>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; @@ -402,7 +411,7 @@ uart2: serial@ff690000 { compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0xff690000 0x100>; + reg = <0x0 0xff690000 0x0 0x100>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; @@ -415,7 +424,7 @@ uart3: serial@ff1b0000 { compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0xff1b0000 0x100>; + reg = <0x0 0xff1b0000 0x0 0x100>; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; @@ -430,7 +439,7 @@ uart4: serial@ff1c0000 { compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0xff1c0000 0x100>; + reg = <0x0 0xff1c0000 0x0 0x100>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; @@ -445,7 +454,7 @@ dmac_peri: dma-controller@ff250000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0xff250000 0x4000>; + reg = <0x0 0xff250000 0x0 0x4000>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; @@ -455,7 +464,7 @@ clock-names = "apb_pclk"; }; - thermal: thermal-zones { + thermal-zones { reserve_thermal: reserve-thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <5000>; /* milliseconds */ @@ -538,24 +547,28 @@ tsadc: tsadc@ff280000 { compatible = "rockchip,rk3288-tsadc"; - reg = <0xff280000 0x100>; + reg = <0x0 0xff280000 0x0 0x100>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; clock-names = "tsadc", "apb_pclk"; resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; - pinctrl-names = "otp_out"; - pinctrl-0 = <&otp_out>; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_pin>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_pin>; #thermal-sensor-cells = <1>; - hw-shut-temp = <125000>; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <95000>; status = "disabled"; }; gmac: ethernet@ff290000 { compatible = "rockchip,rk3288-gmac"; - reg = <0xff290000 0x10000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; + reg = <0x0 0xff290000 0x0 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; rockchip,grf = <&grf>; clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, @@ -567,14 +580,14 @@ "aclk_mac", "pclk_mac"; resets = <&cru SRST_MAC>; reset-names = "stmmaceth"; + status = "disabled"; }; usb_host0_ehci: usb@ff500000 { compatible = "generic-ehci"; - reg = <0xff500000 0x100>; + reg = <0x0 0xff500000 0x0 0x100>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_USBHOST0>; - clock-names = "usbhost"; phys = <&usbphy1>; phy-names = "usb"; status = "disabled"; @@ -594,7 +607,7 @@ usb_host1: usb@ff540000 { compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2"; - reg = <0xff540000 0x40000>; + reg = <0x0 0xff540000 0x0 0x40000>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_USBHOST1>; clock-names = "otg"; @@ -608,7 +621,7 @@ usb_otg: usb@ff580000 { compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2"; - reg = <0xff580000 0x40000>; + reg = <0x0 0xff580000 0x0 0x40000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_OTG0>; clock-names = "otg"; @@ -623,16 +636,15 @@ usb_hsic: usb@ff5c0000 { compatible = "generic-ehci"; - reg = <0xff5c0000 0x100>; + reg = <0x0 0xff5c0000 0x0 0x100>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_HSIC>; - clock-names = "usbhost"; status = "disabled"; }; dmac_bus_ns: dma-controller@ff600000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0xff600000 0x4000>; + reg = <0x0 0xff600000 0x0 0x4000>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; @@ -645,7 +657,7 @@ i2c0: i2c@ff650000 { compatible = "rockchip,rk3288-i2c"; - reg = <0xff650000 0x1000>; + reg = <0x0 0xff650000 0x0 0x1000>; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -658,7 +670,7 @@ i2c2: i2c@ff660000 { compatible = "rockchip,rk3288-i2c"; - reg = <0xff660000 0x1000>; + reg = <0x0 0xff660000 0x0 0x1000>; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -671,7 +683,7 @@ pwm0: pwm@ff680000 { compatible = "rockchip,rk3288-pwm"; - reg = <0xff680000 0x10>; + reg = <0x0 0xff680000 0x0 0x10>; #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; @@ -681,7 +693,7 @@ pwm1: pwm@ff680010 { compatible = "rockchip,rk3288-pwm"; - reg = <0xff680010 0x10>; + reg = <0x0 0xff680010 0x0 0x10>; #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pwm1_pin>; @@ -691,7 +703,7 @@ pwm2: pwm@ff680020 { compatible = "rockchip,rk3288-pwm"; - reg = <0xff680020 0x10>; + reg = <0x0 0xff680020 0x0 0x10>; #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pwm2_pin>; @@ -701,7 +713,7 @@ pwm3: pwm@ff680030 { compatible = "rockchip,rk3288-pwm"; - reg = <0xff680030 0x10>; + reg = <0x0 0xff680030 0x0 0x10>; #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&pwm3_pin>; @@ -711,10 +723,10 @@ bus_intmem: sram@ff700000 { compatible = "mmio-sram"; - reg = <0xff700000 0x18000>; + reg = <0x0 0xff700000 0x0 0x18000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0xff700000 0x18000>; + ranges = <0 0x0 0xff700000 0x18000>; smp-sram@0 { compatible = "rockchip,rk3066-smp-sram"; reg = <0x00 0x10>; @@ -723,12 +735,12 @@ pmu_sram: sram@ff720000 { compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; - reg = <0xff720000 0x1000>; + reg = <0x0 0xff720000 0x0 0x1000>; }; pmu: power-management@ff730000 { compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; - reg = <0xff730000 0x100>; + reg = <0x0 0xff730000 0x0 0x100>; power: power-controller { compatible = "rockchip,rk3288-power-controller"; @@ -853,12 +865,14 @@ sgrf: syscon@ff740000 { compatible = "rockchip,rk3288-sgrf", "syscon"; - reg = <0xff740000 0x1000>; + reg = <0x0 0xff740000 0x0 0x1000>; }; cru: clock-controller@ff760000 { compatible = "rockchip,rk3288-cru"; - reg = <0xff760000 0x1000>; + reg = <0x0 0xff760000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; @@ -876,7 +890,7 @@ grf: syscon@ff770000 { compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; - reg = <0xff770000 0x1000>; + reg = <0x0 0xff770000 0x0 0x1000>; edp_phy: edp-phy { compatible = "rockchip,rk3288-dp-phy"; @@ -931,15 +945,15 @@ wdt: watchdog@ff800000 { compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; - reg = <0xff800000 0x100>; + reg = <0x0 0xff800000 0x0 0x100>; clocks = <&cru PCLK_WDT>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - spdif: sound@ff88b0000 { + spdif: sound@ff8b0000 { compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; - reg = <0xff8b0000 0x10000>; + reg = <0x0 0xff8b0000 0x0 0x10000>; #sound-dai-cells = <0>; clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>; clock-names = "mclk", "hclk"; @@ -954,7 +968,7 @@ i2s: i2s@ff890000 { compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; - reg = <0xff890000 0x10000>; + reg = <0x0 0xff890000 0x0 0x10000>; #sound-dai-cells = <0>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; @@ -970,7 +984,7 @@ crypto: crypto@ff8a0000 { compatible = "rockchip,rk3288-crypto"; - reg = <0xff8a0000 0x4000>; + reg = <0x0 0xff8a0000 0x0 0x4000>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; @@ -981,7 +995,7 @@ iep_mmu: iommu@ff900800 { compatible = "rockchip,iommu"; - reg = <0xff900800 0x40>; + reg = <0x0 0xff900800 0x0 0x40>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; clock-names = "aclk", "iface"; @@ -991,7 +1005,7 @@ isp_mmu: iommu@ff914000 { compatible = "rockchip,iommu"; - reg = <0xff914000 0x100>, <0xff915000 0x100>; + reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; clock-names = "aclk", "iface"; @@ -1002,7 +1016,7 @@ rga: rga@ff920000 { compatible = "rockchip,rk3288-rga"; - reg = <0xff920000 0x180>; + reg = <0x0 0xff920000 0x0 0x180>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; clock-names = "aclk", "hclk", "sclk"; @@ -1013,7 +1027,7 @@ vopb: vop@ff930000 { compatible = "rockchip,rk3288-vop"; - reg = <0xff930000 0x19c>, <0xff931000 0x1000>; + reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; @@ -1051,7 +1065,7 @@ vopb_mmu: iommu@ff930300 { compatible = "rockchip,iommu"; - reg = <0xff930300 0x100>; + reg = <0x0 0xff930300 0x0 0x100>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; clock-names = "aclk", "iface"; @@ -1062,7 +1076,7 @@ vopl: vop@ff940000 { compatible = "rockchip,rk3288-vop"; - reg = <0xff940000 0x19c>, <0xff941000 0x1000>; + reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; @@ -1100,7 +1114,7 @@ vopl_mmu: iommu@ff940300 { compatible = "rockchip,iommu"; - reg = <0xff940300 0x100>; + reg = <0x0 0xff940300 0x0 0x100>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; clock-names = "aclk", "iface"; @@ -1109,9 +1123,9 @@ status = "disabled"; }; - mipi_dsi: mipi@ff960000 { + mipi_dsi: dsi@ff960000 { compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; - reg = <0xff960000 0x4000>; + reg = <0x0 0xff960000 0x0 0x4000>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; clock-names = "ref", "pclk"; @@ -1120,24 +1134,34 @@ status = "disabled"; ports { - mipi_in: port { + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: port@0 { + reg = <0>; #address-cells = <1>; #size-cells = <0>; + mipi_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_mipi>; }; + mipi_in_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl_out_mipi>; }; }; + + mipi_out: port@1 { + reg = <1>; + }; }; }; lvds: lvds@ff96c000 { compatible = "rockchip,rk3288-lvds"; - reg = <0xff96c000 0x4000>; + reg = <0x0 0xff96c000 0x0 0x4000>; clocks = <&cru PCLK_LVDS_PHY>; clock-names = "pclk_lvds"; pinctrl-names = "lcdc"; @@ -1152,7 +1176,6 @@ lvds_in: port@0 { reg = <0>; - #address-cells = <1>; #size-cells = <0>; @@ -1160,17 +1183,22 @@ reg = <0>; remote-endpoint = <&vopb_out_lvds>; }; + lvds_in_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl_out_lvds>; }; }; + + lvds_out: port@1 { + reg = <1>; + }; }; }; edp: dp@ff970000 { compatible = "rockchip,rk3288-dp"; - reg = <0xff970000 0x4000>; + reg = <0x0 0xff970000 0x0 0x4000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; clock-names = "dp", "pclk"; @@ -1185,25 +1213,32 @@ ports { #address-cells = <1>; #size-cells = <0>; + edp_in: port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; + edp_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_edp>; }; + edp_in_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl_out_edp>; }; }; + + edp_out: port@1 { + reg = <1>; + }; }; }; hdmi: hdmi@ff980000 { compatible = "rockchip,rk3288-dw-hdmi"; - reg = <0xff980000 0x20000>; + reg = <0x0 0xff980000 0x0 0x20000>; reg-io-width = <4>; #sound-dai-cells = <0>; rockchip,grf = <&grf>; @@ -1231,7 +1266,7 @@ vpu: video-codec@ff9a0000 { compatible = "rockchip,rk3288-vpu"; - reg = <0xff9a0000 0x800>; + reg = <0x0 0xff9a0000 0x0 0x800>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "vepu", "vdpu"; @@ -1243,7 +1278,7 @@ vpu_mmu: iommu@ff9a0800 { compatible = "rockchip,iommu"; - reg = <0xff9a0800 0x100>; + reg = <0x0 0xff9a0800 0x0 0x100>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; clock-names = "aclk", "iface"; @@ -1253,7 +1288,7 @@ hevc_mmu: iommu@ff9c0440 { compatible = "rockchip,iommu"; - reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>; + reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; clock-names = "aclk", "iface"; @@ -1263,7 +1298,7 @@ gpu: gpu@ffa30000 { compatible = "rockchip,rk3288-mali", "arm,mali-t760"; - reg = <0xffa30000 0x10000>; + reg = <0x0 0xffa30000 0x0 0x10000>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -1302,22 +1337,22 @@ qos_gpu_r: qos@ffaa0000 { compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0xffaa0000 0x20>; + reg = <0x0 0xffaa0000 0x0 0x20>; }; qos_gpu_w: qos@ffaa0080 { compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0xffaa0080 0x20>; + reg = <0x0 0xffaa0080 0x0 0x20>; }; qos_vio1_vop: qos@ffad0000 { compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0xffad0000 0x20>; + reg = <0x0 0xffad0000 0x0 0x20>; }; qos_vio1_isp_w0: qos@ffad0100 { compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0xffad0100 0x20>; + reg = <0x0 0xffad0100 0x0 0x20>; }; qos_vio1_isp_w1: qos@ffad0180 { @@ -1332,47 +1367,47 @@ qos_vio0_vip: qos@ffad0480 { compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0xffad0480 0x20>; + reg = <0x0 0xffad0480 0x0 0x20>; }; qos_vio0_iep: qos@ffad0500 { compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0xffad0500 0x20>; + reg = <0x0 0xffad0500 0x0 0x20>; }; qos_vio2_rga_r: qos@ffad0800 { compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0xffad0800 0x20>; + reg = <0x0 0xffad0800 0x0 0x20>; }; qos_vio2_rga_w: qos@ffad0880 { compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0xffad0880 0x20>; + reg = <0x0 0xffad0880 0x0 0x20>; }; qos_vio1_isp_r: qos@ffad0900 { compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0xffad0900 0x20>; + reg = <0x0 0xffad0900 0x0 0x20>; }; qos_video: qos@ffae0000 { compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0xffae0000 0x20>; + reg = <0x0 0xffae0000 0x0 0x20>; }; qos_hevc_r: qos@ffaf0000 { compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0xffaf0000 0x20>; + reg = <0x0 0xffaf0000 0x0 0x20>; }; qos_hevc_w: qos@ffaf0080 { compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0xffaf0080 0x20>; + reg = <0x0 0xffaf0080 0x0 0x20>; }; dmac_bus_s: dma-controller@ffb20000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0xffb20000 0x4000>; + reg = <0x0 0xffb20000 0x0 0x4000>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; @@ -1384,7 +1419,7 @@ efuse: efuse@ffb40000 { compatible = "rockchip,rk3288-efuse"; - reg = <0xffb40000 0x10000>; + reg = <0x0 0xffb40000 0x0 0x20>; #address-cells = <1>; #size-cells = <1>; clocks = <&cru PCLK_EFUSE256>; @@ -1404,10 +1439,10 @@ #interrupt-cells = <3>; #address-cells = <0>; - reg = <0xffc01000 0x1000>, - <0xffc02000 0x1000>, - <0xffc04000 0x2000>, - <0xffc06000 0x2000>; + reg = <0x0 0xffc01000 0x0 0x1000>, + <0x0 0xffc02000 0x0 0x2000>, + <0x0 0xffc04000 0x0 0x2000>, + <0x0 0xffc06000 0x0 0x2000>; interrupts = <GIC_PPI 9 0xf04>; }; @@ -1415,13 +1450,13 @@ compatible = "rockchip,rk3288-pinctrl"; rockchip,grf = <&grf>; rockchip,pmu = <&pmu>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; - gpio0: gpio0@ff750000 { + gpio0: gpio@ff750000 { compatible = "rockchip,gpio-bank"; - reg = <0xff750000 0x100>; + reg = <0x0 0xff750000 0x0 0x100>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO0>; @@ -1432,9 +1467,9 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@ff780000 { + gpio1: gpio@ff780000 { compatible = "rockchip,gpio-bank"; - reg = <0xff780000 0x100>; + reg = <0x0 0xff780000 0x0 0x100>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO1>; @@ -1445,9 +1480,9 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@ff790000 { + gpio2: gpio@ff790000 { compatible = "rockchip,gpio-bank"; - reg = <0xff790000 0x100>; + reg = <0x0 0xff790000 0x0 0x100>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO2>; @@ -1458,9 +1493,9 @@ #interrupt-cells = <2>; }; - gpio3: gpio3@ff7a0000 { + gpio3: gpio@ff7a0000 { compatible = "rockchip,gpio-bank"; - reg = <0xff7a0000 0x100>; + reg = <0x0 0xff7a0000 0x0 0x100>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO3>; @@ -1471,9 +1506,9 @@ #interrupt-cells = <2>; }; - gpio4: gpio4@ff7b0000 { + gpio4: gpio@ff7b0000 { compatible = "rockchip,gpio-bank"; - reg = <0xff7b0000 0x100>; + reg = <0x0 0xff7b0000 0x0 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO4>; @@ -1484,9 +1519,9 @@ #interrupt-cells = <2>; }; - gpio5: gpio5@ff7c0000 { + gpio5: gpio@ff7c0000 { compatible = "rockchip,gpio-bank"; - reg = <0xff7c0000 0x100>; + reg = <0x0 0xff7c0000 0x0 0x100>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO5>; @@ -1497,9 +1532,9 @@ #interrupt-cells = <2>; }; - gpio6: gpio6@ff7d0000 { + gpio6: gpio@ff7d0000 { compatible = "rockchip,gpio-bank"; - reg = <0xff7d0000 0x100>; + reg = <0x0 0xff7d0000 0x0 0x100>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO6>; @@ -1510,9 +1545,9 @@ #interrupt-cells = <2>; }; - gpio7: gpio7@ff7e0000 { + gpio7: gpio@ff7e0000 { compatible = "rockchip,gpio-bank"; - reg = <0xff7e0000 0x100>; + reg = <0x0 0xff7e0000 0x0 0x100>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO7>; @@ -1523,9 +1558,9 @@ #interrupt-cells = <2>; }; - gpio8: gpio8@ff7f0000 { + gpio8: gpio@ff7f0000 { compatible = "rockchip,gpio-bank"; - reg = <0xff7f0000 0x100>; + reg = <0x0 0xff7f0000 0x0 0x100>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO8>; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index b577a911e789..6ff0aa6911e2 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -125,6 +125,7 @@ config ROCKCHIP_RK3288 select SUPPORT_SPL select SPL select SUPPORT_TPL + select FDT_64BIT imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD imply SPL_ROCKCHIP_COMMON_BOARD -- 2.39.2

2 1

[PATCH 1/1] cmd: fdt: check fdt address
by Heinrich Schuchardt 01 Jan '24

01 Jan '24

Trying to read a device-tree from an illegal address leads to a crash. Check that the parameter passed to 'fdt addr' is within the RAM area and non-zero. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- cmd/fdt.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/cmd/fdt.c b/cmd/fdt.c index 331564c13b..dc954ea7d5 100644 --- a/cmd/fdt.c +++ b/cmd/fdt.c @@ -193,6 +193,11 @@ static int do_fdt(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } addr = hextoul(argv[0], NULL); + if (!addr || addr < gd->ram_base || addr >= gd->ram_top) { + printf("Invalid address\n"); + return CMD_RET_FAILURE; + } + blob = map_sysmem(addr, 0); if ((quiet && fdt_check_header(blob)) || (!quiet && !fdt_valid(&blob))) -- 2.40.1

3 4

[PATCH v5 00/11] Support Firmware Handoff spec via bloblist
by Raymond Mao 01 Jan '24

01 Jan '24

Major changes: Update bloblist to align to Firmware Handoff spec v0.9 (up to commit #3592349 of the spec). (https://github.com/FirmwareHandoff/firmware_handoff). Includes: - Align bloblist tags with the FW handoff spec - Add an explicit alignment field in the header - Update bloblist magic and version - Use a packed format for blob record header - Change the checksum alorigthm - Use a void entry to handle the alignment - Adjust the headers of bloblist and blob record - Align the bloblist record data section start address v3: The implementation from boot arguments to bloblist and how to load the FDT from the bloblist are moved to a forthcoming patch serie. v4: Patch #7 and #14 from v3 are squashed to other patches. v5: Patch #6 from v4 is squashed to #8 Simon Glass (11): bloblist: Update the tag numbering bloblist: Adjust API to align in powers of 2 bloblist: Change the magic value bloblist: Set version to 1 bloblist: Access record hdr_size and tag via a function bloblist: Checksum the entire bloblist bloblist: Handle alignment with a void entry bloblist: Reduce blob-header size bloblist: Adjust the bloblist header bloblist: Add alignment to bloblist_new() bloblist: Update documentation and header comment arch/x86/lib/tables.c | 3 +- common/bloblist.c | 205 ++++++++++++++++++++++++--------------- doc/develop/bloblist.rst | 4 +- include/bloblist.h | 166 ++++++++++++++++++------------- test/bloblist.c | 105 +++++++++++--------- 5 files changed, 287 insertions(+), 196 deletions(-) -- 2.25.1

2 22

[PATCH 1/1] buildman: type cotaining
by Heinrich Schuchardt 01 Jan '24

01 Jan '24

%s/cotaining/containing/ Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- tools/buildman/boards.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/buildman/boards.py b/tools/buildman/boards.py index 341a5056df..3c2822715f 100644 --- a/tools/buildman/boards.py +++ b/tools/buildman/boards.py @@ -119,7 +119,7 @@ class Expr: """Set up a new Expr object. Args: - expr (str): String cotaining regular expression to store + expr (str): String containing regular expression to store """ self._expr = expr self._re = re.compile(expr) -- 2.40.1

2 2

[PATCH 1/1] binman: used-before-assignment in ftest.py
by Heinrich Schuchardt 01 Jan '24

01 Jan '24

Pytest 7.4.3 complains if a variable is used in a finally clause without having been initialized before the try clause. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- tools/binman/ftest.py | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index a273120d9f..a4ac520cbb 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -2842,12 +2842,14 @@ class TestFunctional(unittest.TestCase): fdt_size = entries['section'].GetEntries()['u-boot-dtb'].size fdtmap_offset = entries['fdtmap'].offset + tmpdir = None try: tmpdir, updated_fname = self._SetupImageInTmpdir() with test_util.capture_sys_output() as (stdout, stderr): self._DoBinman('ls', '-i', updated_fname) finally: - shutil.rmtree(tmpdir) + if tmpdir: + shutil.rmtree(tmpdir) lines = stdout.getvalue().splitlines() expected = [ 'Name Image-pos Size Entry-type Offset Uncomp-size', @@ -2868,12 +2870,14 @@ class TestFunctional(unittest.TestCase): def testListCmdFail(self): """Test failing to list an image""" self._DoReadFile('005_simple.dts') + tmpdir = None try: tmpdir, updated_fname = self._SetupImageInTmpdir() with self.assertRaises(ValueError) as e: self._DoBinman('ls', '-i', updated_fname) finally: - shutil.rmtree(tmpdir) + if tmpdir: + shutil.rmtree(tmpdir) self.assertIn("Cannot find FDT map in image", str(e.exception)) def _RunListCmd(self, paths, expected): @@ -3002,13 +3006,15 @@ class TestFunctional(unittest.TestCase): self._CheckLz4() self._DoReadFileRealDtb('130_list_fdtmap.dts') fname = os.path.join(self._indir, 'output.extact') + tmpdir = None try: tmpdir, updated_fname = self._SetupImageInTmpdir() with test_util.capture_sys_output() as (stdout, stderr): self._DoBinman('extract', '-i', updated_fname, 'u-boot', '-f', fname) finally: - shutil.rmtree(tmpdir) + if tmpdir: + shutil.rmtree(tmpdir) data = tools.read_file(fname) self.assertEqual(U_BOOT_DATA, data) @@ -5185,12 +5191,14 @@ fdt fdtmap Extract the devicetree blob from the fdtmap data = self._DoReadFileRealDtb('207_fip_ls.dts') hdr, fents = fip_util.decode_fip(data) + tmpdir = None try: tmpdir, updated_fname = self._SetupImageInTmpdir() with test_util.capture_sys_output() as (stdout, stderr): self._DoBinman('ls', '-i', updated_fname) finally: - shutil.rmtree(tmpdir) + if tmpdir: + shutil.rmtree(tmpdir) lines = stdout.getvalue().splitlines() expected = [ 'Name Image-pos Size Entry-type Offset Uncomp-size', @@ -5395,12 +5403,14 @@ fdt fdtmap Extract the devicetree blob from the fdtmap use_real_dtb=True, extra_indirs=[os.path.join(self._indir, TEST_FDT_SUBDIR)]) + tmpdir = None try: tmpdir, updated_fname = self._SetupImageInTmpdir() with test_util.capture_sys_output() as (stdout, stderr): self._RunBinman('ls', '-i', updated_fname) finally: - shutil.rmtree(tmpdir) + if tmpdir: + shutil.rmtree(tmpdir) def testFitSubentryUsesBintool(self): """Test that binman FIT subentries can use bintools""" -- 2.40.1

2 2

[PATCH v2 10/10] Makefile: Use the fdtgrep -u flag
by Simon Glass 01 Jan '24

01 Jan '24

Use this flag so that the bootph binding is obeyed correctly. Add a comment about what is going on. Signed-off-by: Simon Glass <sjg(a)chromium.org> Fixes: https://source.denx.de/u-boot/custodians/u-boot-dm/-/issues/12 --- Changes in v2: - Add a comment about the fdtgrep operations scripts/Makefile.lib | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 16bbc277a9f1..1ca84195c997 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -635,8 +635,19 @@ else fdtgrep_props := -b bootph-all -b bootph-pre-ram $(migrate_spl) endif endif + +# This rule produces the .dtb for an SPL build. +# +# The first fdtgrep keeps nodes with the above properties (with -u ensuring that +# the properties are implied in all parents of a matching node). The root node +# is always included, along with /chosen and /config nodes. Referenced aliases +# (i.e. properties in /aliases which point to an incldued node) are also +# included. +# +# The second fdtgrep removes all bootph properties along with unused strings +# and any properties in CONFIG_OF_SPL_REMOVE_PROPS quiet_cmd_fdtgrep = FDTGREP $@ - cmd_fdtgrep = $(objtree)/tools/fdtgrep $(fdtgrep_props) -RT $< \ + cmd_fdtgrep = $(objtree)/tools/fdtgrep $(fdtgrep_props) -u -RT $< \ -n /chosen -n /config -O dtb | \ $(objtree)/tools/fdtgrep -r -O dtb - -o $@ \ -P bootph-all -P bootph-pre-ram -P bootph-pre-sram \ -- 2.43.0.472.g3155946c3a-goog

2 2

[PATCH v6] fdt: Allow the devicetree to come from a bloblist
by Simon Glass 31 Dec '23

31 Dec '23

Standard passage provides for a bloblist to be passed from one firmware phase to the next. That can be used to pass the devicetree along as well. Add an option to support this. Tests for this will be added as part of the Universal Payload work. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- The discussion on this was not resolved and is now important due to the bloblist series from Raymond. So I am sending it again since I believe this is a better starting point than building on OF_BOARD Changes in v6: - Don't allow bloblist with OF_EMBED Changes in v5: - Make OF_BLOBLIST default y - Make OF_BLOBLIST optional at runtime Changes in v4: - Rebase to -next common/bloblist.c | 1 + doc/develop/devicetree/control.rst | 3 ++ dts/Kconfig | 13 +++++++++ include/bloblist.h | 5 ++++ include/fdtdec.h | 6 ++-- lib/fdtdec.c | 44 +++++++++++++++++++++++------- 6 files changed, 60 insertions(+), 12 deletions(-) diff --git a/common/bloblist.c b/common/bloblist.c index a22f6c12b0c..b07ede11cfe 100644 --- a/common/bloblist.c +++ b/common/bloblist.c @@ -48,6 +48,7 @@ static struct tag_name { { BLOBLISTT_ACPI_TABLES, "ACPI tables for x86" }, { BLOBLISTT_SMBIOS_TABLES, "SMBIOS tables for x86" }, { BLOBLISTT_VBOOT_CTX, "Chrome OS vboot context" }, + { BLOBLISTT_CONTROL_FDT, "Control FDT" }, /* BLOBLISTT_PROJECT_AREA */ { BLOBLISTT_U_BOOT_SPL_HANDOFF, "SPL hand-off" }, diff --git a/doc/develop/devicetree/control.rst b/doc/develop/devicetree/control.rst index cbb65c9b177..444c55de4e4 100644 --- a/doc/develop/devicetree/control.rst +++ b/doc/develop/devicetree/control.rst @@ -108,6 +108,9 @@ If CONFIG_OF_BOARD is defined, a board-specific routine will provide the devicetree at runtime, for example if an earlier bootloader stage creates it and passes it to U-Boot. +If CONFIG_OF_BLOBLIST is defined, the devicetree comes from a bloblist passed +from a previous stage, if present. + If CONFIG_SANDBOX is defined, then it will be read from a file on startup. Use the -d flag to U-Boot to specify the file to read, -D for the default and -T for the test devicetree, used to run sandbox unit tests. diff --git a/dts/Kconfig b/dts/Kconfig index 00c0aeff893..ae451b9caf7 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -105,6 +105,19 @@ config OF_EMBED endchoice +config OF_BLOBLIST + bool "Provided by a bloblist at runtime" + depends on BLOBLIST && OF_SEPARATE + default y + help + Select this to read the devicetree from the bloblist. This allows + using a bloblist to transfer the devicetree between U-Boot phases. + The devicetree is stored in the bloblist by an early phase so that + U-Boot can read it. + + If the bloblist does not contain a devicetree, then other methods will + be used. + config OF_BOARD bool "Provided by the board (e.g a previous loader) at runtime" default y if SANDBOX || OF_HAS_PRIOR_STAGE diff --git a/include/bloblist.h b/include/bloblist.h index 080cc46a126..e16d122f4fb 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -103,6 +103,11 @@ enum bloblist_tag_t { BLOBLISTT_ACPI_TABLES = 0x104, /* ACPI tables for x86 */ BLOBLISTT_SMBIOS_TABLES = 0x105, /* SMBIOS tables for x86 */ BLOBLISTT_VBOOT_CTX = 0x106, /* Chromium OS verified boot context */ + /* + * Devicetree for use by firmware. On some platforms this is passed to + * the OS also + */ + BLOBLISTT_CONTROL_FDT = 0x107, /* * Project-specific tags are permitted here. Projects can be open source diff --git a/include/fdtdec.h b/include/fdtdec.h index bd1149f46d0..e80de24076c 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -72,7 +72,7 @@ struct bd_info; * U-Boot is packaged as an ELF file, e.g. for debugging purposes * @FDTSRC_ENV: Provided by the fdtcontroladdr environment variable. This should * be used for debugging/development only - * @FDTSRC_NONE: No devicetree at all + * @FDTSRC_BLOBLIST: Provided by a bloblist from an earlier phase */ enum fdt_source_t { FDTSRC_SEPARATE, @@ -80,6 +80,7 @@ enum fdt_source_t { FDTSRC_BOARD, FDTSRC_EMBED, FDTSRC_ENV, + FDTSRC_BLOBLIST, }; /* @@ -1190,7 +1191,8 @@ int fdtdec_resetup(int *rescan); * * The existing devicetree is available at gd->fdt_blob * - * @err internal error code if we fail to setup a DTB + * @err: 0 on success, -EEXIST if the devicetree is already correct, or other + * internal error code if we fail to setup a DTB * @returns new devicetree blob pointer */ void *board_fdt_blob_setup(int *err); diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 4016bf3c113..af3026dd42b 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -7,6 +7,10 @@ */ #ifndef USE_HOSTCC + +#define LOG_CATEGORY LOGC_DT + +#include <bloblist.h> #include <boot_fit.h> #include <display_options.h> #include <dm.h> @@ -86,6 +90,7 @@ static const char *const fdt_src_name[] = { [FDTSRC_BOARD] = "board", [FDTSRC_EMBED] = "embed", [FDTSRC_ENV] = "env", + [FDTSRC_BLOBLIST] = "bloblist", }; const char *fdtdec_get_srcname(void) @@ -1662,23 +1667,42 @@ static void setup_multi_dtb_fit(void) int fdtdec_setup(void) { - int ret; + int ret = -ENOENT; + + /* If allowing a bloblist, check that first */ + if (CONFIG_IS_ENABLED(OF_BLOBLIST)) { + ret = bloblist_maybe_init(); + if (!ret) { + gd->fdt_blob = bloblist_find(BLOBLISTT_CONTROL_FDT, 0); + if (gd->fdt_blob) { + gd->fdt_src = FDTSRC_BLOBLIST; + log_debug("Devicetree is in bloblist at %p\n", + gd->fdt_blob); + } else { + log_debug("No FDT found in bloblist\n"); + ret = -ENOENT; + } + } + } - /* The devicetree is typically appended to U-Boot */ - if (IS_ENABLED(CONFIG_OF_SEPARATE)) { - gd->fdt_blob = fdt_find_separate(); - gd->fdt_src = FDTSRC_SEPARATE; - } else { /* embed dtb in ELF file for testing / development */ - gd->fdt_blob = dtb_dt_embedded(); - gd->fdt_src = FDTSRC_EMBED; + /* Otherwise, the devicetree is typically appended to U-Boot */ + if (ret) { + if (IS_ENABLED(CONFIG_OF_SEPARATE)) { + gd->fdt_blob = fdt_find_separate(); + gd->fdt_src = FDTSRC_SEPARATE; + } else { /* embed dtb in ELF file for testing / development */ + gd->fdt_blob = dtb_dt_embedded(); + gd->fdt_src = FDTSRC_EMBED; + } } /* Allow the board to override the fdt address. */ if (IS_ENABLED(CONFIG_OF_BOARD)) { gd->fdt_blob = board_fdt_blob_setup(&ret); - if (ret) + if (!ret) + gd->fdt_src = FDTSRC_BOARD; + else if (ret != -EEXIST) return ret; - gd->fdt_src = FDTSRC_BOARD; } /* Allow the early environment to override the fdt address */ -- 2.34.1

2 3