December 2023 - U-Boot

[PATCH 0/7] pinctrl: exynos: Prepare for other SoCs support
by Sam Protsenko 13 Dec '23

13 Dec '23

Some Exynos SoCs (not supported by pinctrl-exynos driver yet) have different offsets and widths of pin bank registers (i.e. PIN_CON, PIN_PUD and PIN_DRV registers). Rework pinctrl-exynos driver so it allows for different offsets and widths of those registers by adding the corresponding API. That makes it possible to add the support for new Exynos SoCs in pinctrl-exynos driver. The main patch in this series is: pinctrl: exynos: Support different register types in pin banks Other patches are just related cleanups and refactoring commits, required for the clean implementation of the main patch. Sam Protsenko (7): pinctrl: exynos: Improve coding style pinctrl: exynos: Extract pin parsing code into a separate function pinctrl: exynos: Rework pin_to_bank_base() to obtain data by name pinctrl: exynos: Support different register types in pin banks pinctrl: exynos: Refactor handling the pin related dt properties pinctrl: exynos: Reduce variables scope pinctrl: exynos: Convert to use livetree API for fdt access drivers/pinctrl/exynos/pinctrl-exynos.c | 125 ++++++++++++-------- drivers/pinctrl/exynos/pinctrl-exynos.h | 36 +++++- drivers/pinctrl/exynos/pinctrl-exynos7420.c | 2 + 3 files changed, 108 insertions(+), 55 deletions(-) -- 2.39.2

2 9

[PATCH 0/4] mailbox: zynqmp: support multiple child nodes
by Tanmay Shah 13 Dec '23

13 Dec '23

Current zynqmp_ipi driver is hardcoded to work with only PMU mailbox node. This patch series adds new driver "zynqmp_ipi_dest" to support multiple child node of current "zynqmp-ipi-mailbox" node. It also adds support of SMC calls to TF-A to configure IPI register address space. New driver uses compatible property recently introduced for each child mailbox node. However it is important to maintain backward compatibility for old dts. Previous driver now binds each child node to "zynqmp_ipi_dest" driver which is needed to maintain backward compatibility. Tanmay Shah (4): mailbox: zynqmp: support smc calls to TF-A mailbox: add el3 support only for zynqmp platform mailbox: zynqmp: support mulitple mboxes via device-tree dts: zynqmp: add missing destination mailbox compatible arch/arm/dts/zynqmp.dtsi | 1 + drivers/firmware/firmware-zynqmp.c | 22 ++++ drivers/mailbox/zynqmp-ipi.c | 159 ++++++++++++++++++++++++++--- 3 files changed, 169 insertions(+), 13 deletions(-) base-commit: 5c4e9d0c74a8c2f8d0f4e0ab9cf44959298c2bad -- 2.25.1

2 5

[PATCH v2] timer: starfive: Add Starfive timer support
by Jun Liang Tan 13 Dec '23

13 Dec '23

From: Kuan Lim Lee <kuanlim.lee(a)starfivetech.com> Add timer driver in Starfive SoC. It is an timer that outside of CPU core and inside Starfive SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee(a)starfivetech.com> Signed-off-by: Wei Liang Lim <weiliang.lim(a)starfivetech.com> Changes for v2: - correct driver name, comment, variable --- drivers/timer/starfive-timer.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/timer/starfive-timer.c b/drivers/timer/starfive-timer.c index 816402fdbf..6ac7d7f1d0 100644 --- a/drivers/timer/starfive-timer.c +++ b/drivers/timer/starfive-timer.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2022 StarFive, Inc. All rights reserved. - * Author: Lee Kuan Lim <kuanlim.lee(a)starfivetech.com> + * Author: Kuan Lim Lee <kuanlim.lee(a)starfivetech.com> */ #include <common.h> @@ -48,8 +48,8 @@ static int starfive_probe(struct udevice *dev) int ret; priv->base = dev_read_addr_ptr(dev); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + if (!priv->base) + return -EINVAL; timer_channel = dev_read_u32_default(dev, "channel", 0); priv->base = priv->base + (0x40 * timer_channel); @@ -64,14 +64,16 @@ static int starfive_probe(struct udevice *dev) return ret; uc_priv->clock_rate = clk_get_rate(&clk); - /* Initiate timer, channel 0 */ - /* Unmask Interrupt Mask */ + /* + * Initiate timer, channel 0 + * Unmask Interrupt Mask + */ writel(0, priv->base + STF_TIMER_INT_MASK); /* Single run mode Setting */ if (dev_read_bool(dev, "single-run")) writel(1, priv->base + STF_TIMER_CTL); /* Set Reload value */ - priv->timer_size = dev_read_u32_default(dev, "timer-size", 0xffffffff); + priv->timer_size = dev_read_u32_default(dev, "timer-size", -1U); writel(priv->timer_size, priv->base + STF_TIMER_LOAD); /* Enable to start timer */ writel(1, priv->base + STF_TIMER_ENABLE); @@ -85,7 +87,7 @@ static const struct udevice_id starfive_ids[] = { }; U_BOOT_DRIVER(jh8100_starfive_timer) = { - .name = "jh8100_starfive_timer", + .name = "starfive_timer", .id = UCLASS_TIMER, .of_match = starfive_ids, .probe = starfive_probe, -- 2.25.1

2 1

[PATCH 1/2] riscv: dts: jh7110: Add a gpio-restart node
by Jaehoon Chung 13 Dec '23

13 Dec '23

Add gpio-restart node to do reset. Before applied this patch, System Reset Extension doesn't appear with sbi command. OpenSBI 1.3 Machine: Vendor ID 489 Architecture ID 8000000000000007 Implementation ID 4210427 Extensions: sbi_set_timer sbi_console_putchar ...[snip]... IPI Extension RFENCE Extension Hart State Management Extension Performance Monitoring Unit Extension After applied this patch, System Reset Extension is supported from SBI. OpenSBI 1.3 Machine: Vendor ID 489 Architecture ID 8000000000000007 Implementation ID 4210427 Extensions: sbi_set_timer sbi_console_putchar ...[snip]... IPI Extension RFENCE Extension Hart State Management Extension System Reset Extension Performance Monitoring Unit Extension Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi index e40f57a15080..e94f9fe826a8 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi @@ -34,6 +34,11 @@ device_type = "memory"; reg = <0x0 0x40000000 0x2 0x0>; }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>; + }; }; &osc { -- 2.25.1

3 5

[PATCH V2 1/2] drivers: watchdog: add andes atcwdt200 support
by Randolph 13 Dec '23

13 Dec '23

This patch adds an implementation of the Andes watchdog ATCWDT200 driver. Signed-off-by: CL Wang <cl634(a)andestech.com> Signed-off-by: Randolph <randolph(a)andestech.com> --- drivers/watchdog/Kconfig | 6 + drivers/watchdog/Makefile | 1 + drivers/watchdog/atcwdt200_wdt.c | 220 +++++++++++++++++++++++++++++++ 3 files changed, 227 insertions(+) create mode 100644 drivers/watchdog/atcwdt200_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 07fc4940e9..6b0f77dd3f 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -130,6 +130,12 @@ config WDT_AT91 Select this to enable Microchip watchdog timer, which can be found on some AT91 devices. +config WDT_ATCWDT200 + bool "Andes watchdog timer support" + depends on WDT + help + Select this to enable Andes ATCWDT200 watchdog timer + config WDT_BCM6345 bool "BCM6345 watchdog timer support" depends on WDT && (ARCH_BMIPS || BCM6856 || \ diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index eef786f5e7..1750ebbb1f 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_WDT_ARM_SMC) += arm_smc_wdt.o obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o +obj-$(CONFIG_WDT_ATCWDT200) += atcwdt200_wdt.o obj-$(CONFIG_WDT_BCM2835) += bcm2835_wdt.o obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o diff --git a/drivers/watchdog/atcwdt200_wdt.c b/drivers/watchdog/atcwdt200_wdt.c new file mode 100644 index 0000000000..2a456d7a46 --- /dev/null +++ b/drivers/watchdog/atcwdt200_wdt.c @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation. + * + */ + +#include <asm/io.h> +#include <dm.h> +#include <hang.h> +#include <linux/bitops.h> +#include <wdt.h> + +#define NODE_NOT_FOUND 0xFFFFFFFF + +#define WDT_WP_MAGIC 0x5aa5 +#define WDT_RESTART_MAGIC 0xcafe + +/* Control Register */ +#define REG_WDT_ID 0x00 +#define REG_WDT_CFG 0x10 +#define REG_WDT_RS 0x14 +#define REG_WDT_WE 0x18 +#define REG_WDT_STA 0x1C + +#define RST_TIME_OFF 8 +#define RST_TIME_MSK (0x7 << RST_TIME_OFF) +#define RST_CLK_128 (0 << RST_TIME_OFF) +#define RST_CLK_256 (1 << RST_TIME_OFF) +#define RST_CLK_512 (2 << RST_TIME_OFF) +#define RST_CLK_1024 (3 << RST_TIME_OFF) +#define INT_TIME_OFF 4 +#define INT_TIME_MSK (0xf << INT_TIME_OFF) +#define INT_CLK_2_6 (0 << INT_TIME_OFF) /* clk period*2^6 */ +#define INT_CLK_2_8 (1 << INT_TIME_OFF) /* clk period*2^8 */ +#define INT_CLK_2_10 (2 << INT_TIME_OFF) /* clk period*2^10 */ +#define INT_CLK_2_11 (3 << INT_TIME_OFF) /* clk period*2^11 */ +#define INT_CLK_2_12 (4 << INT_TIME_OFF) /* clk period*2^12 */ +#define INT_CLK_2_13 (5 << INT_TIME_OFF) /* clk period*2^13 */ +#define INT_CLK_2_14 (6 << INT_TIME_OFF) /* clk period*2^14 */ +#define INT_CLK_2_15 (7 << INT_TIME_OFF) /* clk period*2^15 */ +#define INT_CLK_2_17 (8 << INT_TIME_OFF) /* clk period*2^17 */ +#define INT_CLK_2_19 (9 << INT_TIME_OFF) /* clk period*2^19 */ +#define INT_CLK_2_21 (10 << INT_TIME_OFF) /* clk period*2^21 */ +#define INT_CLK_2_23 (11 << INT_TIME_OFF) /* clk period*2^23 */ +#define INT_CLK_2_25 (12 << INT_TIME_OFF) /* clk period*2^25 */ +#define INT_CLK_2_27 (13 << INT_TIME_OFF) /* clk period*2^27 */ +#define INT_CLK_2_29 (14 << INT_TIME_OFF) /* clk period*2^29 */ +#define INT_CLK_2_31 (15 << INT_TIME_OFF) /* clk period*2^31 */ +#define INT_CLK_MIN 0x0 +#define INT_CLK_MAX_16B 0x7 +#define INT_CLK_MAX_32B 0xF +#define RST_EN BIT(3) +#define INT_EN BIT(2) +#define CLK_PCLK BIT(1) +#define WDT_EN BIT(0) +#define INT_EXPIRED BIT(0) + +#define INT_TIME_ARRAY 16 +#define RST_TIME_ARRAY 8 + +struct wdt_priv { + void __iomem *base; + u32 wdt_clk_src; + u32 clk_freq; + u8 max_clk; +}; + +static inline u8 atcwdt_get_2_power_of_n(u8 index, u8 type) +{ + const u8 div_int[INT_TIME_ARRAY] = {6, 8, 10, 11, 12, 13, 14, 15, + 17, 19, 21, 23, 25, 27, 29, 31}; + const u8 div_rst[RST_TIME_ARRAY] = {7, 8, 9, 10, 11, 12, 13, 14}; + u8 *pdiv; + + if (type == RST_TIME_ARRAY) + pdiv = div_rst; + else + pdiv = div_int; + + if (index >= type) + index = type - 1; + + return pdiv[index]; +} + +static u8 atwdt_search_msb(u64 freq_ms, u8 type) +{ + u64 result; + u64 freq_sec; + u8 index; + + freq_sec = freq_ms / 1000; + for (index = 0; index < type; index++) { + result = freq_sec >> atcwdt_get_2_power_of_n(index, type); + + if (result <= 1) + break; + } + + return index; +} + +static int atcwdt_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + struct wdt_priv *priv = dev_get_priv(dev); + u64 rst_max_count; + u32 rst_max_time_ms; + u64 rst_time_ms; + u64 int_time_ms; + u8 rst_time; + u8 int_time; + + rst_max_count = 1 << atcwdt_get_2_power_of_n(RST_TIME_ARRAY, RST_TIME_ARRAY); + rst_max_time_ms = (rst_max_count * 1000) / priv->clk_freq; + + if (timeout > rst_max_time_ms) { + int_time_ms = timeout - rst_max_time_ms; + rst_time_ms = rst_max_time_ms; + } else { + int_time_ms = 0; + rst_time_ms = timeout; + } + + rst_time = atwdt_search_msb(rst_time_ms * priv->clk_freq, RST_TIME_ARRAY); + + if (int_time_ms) { + int_time = atwdt_search_msb(int_time_ms * priv->clk_freq, INT_TIME_ARRAY); + if (int_time > priv->max_clk) + int_time = priv->max_clk; + } else { + int_time = 0; + } + + writel(WDT_WP_MAGIC, priv->base + REG_WDT_WE); + writel(((rst_time << RST_TIME_OFF) & RST_TIME_MSK) | ((int_time << INT_TIME_OFF) & + INT_TIME_MSK) | INT_EN | RST_EN | priv->wdt_clk_src | WDT_EN, + priv->base + REG_WDT_CFG); + + return 0; +} + +static int atcwdt_wdt_stop(struct udevice *dev) +{ + struct wdt_priv *priv = dev_get_priv(dev); + + writel(WDT_WP_MAGIC, priv->base + REG_WDT_WE); + writel(0, priv->base + REG_WDT_CFG); + + return 0; +} + +static int atcwdt_wdt_restart(struct udevice *dev) +{ + struct wdt_priv *priv = dev_get_priv(dev); + + writel(WDT_WP_MAGIC, priv->base + REG_WDT_WE); + writel(WDT_RESTART_MAGIC, priv->base + REG_WDT_RS); + setbits_le32(priv->base + REG_WDT_STA, INT_EXPIRED); + + return 0; +} + +static int atcwdt_wdt_expire_now(struct udevice *dev, ulong flags) +{ + atcwdt_wdt_start(dev, 0, 0); + hang(); + + return 0; +} + +static int atcwdt_wdt_probe(struct udevice *dev) +{ + struct wdt_priv *priv = dev_get_priv(dev); + int timer_16bit; + + priv->base = dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EFAULT; + + priv->wdt_clk_src = dev_read_u32_default(dev, "clock-source", NODE_NOT_FOUND); + if (priv->wdt_clk_src == NODE_NOT_FOUND || priv->wdt_clk_src > 1) + priv->wdt_clk_src = CLK_PCLK; + + timer_16bit = dev_read_u32_default(dev, "16bit_timer", NODE_NOT_FOUND); + if (timer_16bit == 1 || timer_16bit == NODE_NOT_FOUND) + priv->max_clk = INT_CLK_MAX_16B; + else + priv->max_clk = INT_CLK_MAX_32B; + + priv->clk_freq = dev_read_u32_default(dev, "clock-frequency", NODE_NOT_FOUND); + if (priv->clk_freq == NODE_NOT_FOUND) { + printf("atcwdt200: Please provide a valid \"clock-frequency\" in DTB\n"); + return -EINVAL; + } + + atcwdt_wdt_stop(dev); + + return 0; +} + +static const struct wdt_ops atcwdt_wdt_ops = { + .start = atcwdt_wdt_start, + .reset = atcwdt_wdt_restart, + .stop = atcwdt_wdt_stop, + .expire_now = atcwdt_wdt_expire_now, +}; + +static const struct udevice_id atcwdt_wdt_ids[] = { + {.compatible = "andestech,atcwdt200"}, + {} +}; + +U_BOOT_DRIVER(atcwdt) = { + .name = "atc_wdt", + .id = UCLASS_WDT, + .probe = atcwdt_wdt_probe, + .of_match = atcwdt_wdt_ids, + .ops = &atcwdt_wdt_ops, + .priv_auto = sizeof(struct wdt_priv), +}; -- 2.34.1

2 3

Pull request: please pull u-boot-imx-20231212
by Fabio Estevam 12 Dec '23

12 Dec '23

Hi Tom, please pull these fixes from u-boot-imx, thanks. The following changes since commit 65eed687729c28431d38c6c9174da4d878fb107f: test/py: Disable error E0611 in two cases for pylint (2023-12-09 14:58:21 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git tags/u-boot-imx-20231212 for you to fetch changes up to d3977b130a91459592c040c0321479bd206326f9: board: colibri_imx7: fix emmc detection (2023-12-12 09:33:08 -0300) u-boot-imx-20231212 ------------------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/18878 - Fix emmc detection on colibri_imx7 - Fix DDR configuration on tqma6 to improve Ethernet performance - Fix aliases and chosen nodes indentation on imx7s-warp - Convert pico-imx6ul to DM_SERIAL - Convert pico-pi-imx7d to watchdog driver model to fix 'reset' command - Select CONFIG_NET_RANDOM_ETHADDR on imx8mp_evk to fix networking on older boards - Add USBH_EN gpio hog to fix USB host interface not working on some Apalis Toradex carrier boards with Apalis iMX8 SoM - Add PCI fixup for GW73xx-F+ - Fix broken EEPROM read on imx8mn-var-som ---------------------------------------------------------------- Fabio Estevam (4): imx8mp_evk: Select CONFIG_NET_RANDOM_ETHADDR pico-pi-imx7d: Convert to watchdog driver model pico-pi-imx6ul: Connvert to DM_SERIAL imx7s-warp-u-boot: Fix aliases and chosen nodes indentation From: Andrejs Cainikovs (1): apalis-imx8: add USBH_EN gpio hog Hugo Villeneuve (1): arm: dts: imx8mn-var-som: Fix broken EEPROM read Marcel Ziswiler (1): board: colibri_imx7: fix emmc detection Miquel Raynal (1): tqma6: Fix DDR configuration Tim Harvey (1): board: gateworks: venice: add fixup for GW73xx-F+ arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi | 6 ++++++ arch/arm/dts/imx7d-pico-pi-u-boot.dtsi | 10 ++++++++++ arch/arm/dts/imx7s-warp-u-boot.dtsi | 14 +++++++------- arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 6 +++--- board/gateworks/venice/venice.c | 6 +++--- board/toradex/colibri_imx7/colibri_imx7.c | 6 +++--- board/tq/tqma6/tqma6q.cfg | 2 +- configs/apalis-imx8_defconfig | 1 + configs/imx8mp_evk_defconfig | 1 + configs/pico-pi-imx6ul_defconfig | 1 + configs/pico-pi-imx7d_defconfig | 3 +++ include/configs/colibri_imx7.h | 1 - 12 files changed, 39 insertions(+), 18 deletions(-)

2 3

[PATCH 00/21] Qualcomm generic board support
by Caleb Connolly 12 Dec '23

12 Dec '23

Historically, Qualcomm boards in U-Boot have all had their own board/qualcomm/xyz directory, their own CONFIG_TARGET_XYZ option, their own hardcoded sysmap-xyz.c file, and their own U-Boot specific devicetree with little/no compatibility with upstream DT. This series makes a few final prepatory changes, and then replaces almost all of the board specific code with generic alternatives. The end result is that all Qualcomm boards both current and future (with the exception of the db410c and db820c) can be supported by a single U-Boot binary by just providing the correct DT. New boards can be added without introducing any addition mach/ or board/ code or config options. Due to the nature of this change, the patch ("mach-snapdragon: generalise board support") has become pretty big, I tried a few different ways to represent this in git history, but the other methods (e.g. adding a stub "generic" target and removing it again) were more confusing and made for much messier git history. The current patch is mostly atomic, but requires regenerating the config. The QCS404 EVB board had some code to enable the USB VBUS regulator, this is dropped in favour of a adding a new vbus-supply property to the dwc3-generic driver. This will also be used by the dragonboard845c in a future patch. This handles the common case of a board requiring some regulator be enabled for USB host mode. A more detailed description of the changes is below. == Memory map == The memory map was historically hardcoded into U-Boot, this meant that U-Boot had to be built for a specific variant of a device. This is changed to instead read the memory map from the DT /memory node. Additionally, most boards mapped addresss 0x0 as valid, as a result if a null pointer access happens then it will cause a bus stall (and board hang). This is fixed so that null pointer accesses will now correctly throw an exception. == DT loading == Previously, boards used the FDT blob embedded into U-Boot (via OF_SEPARATE). However, most Qualcomm boards run U-Boot as a secondary bootloader, so we can instead rely on the first-stage bootloader to populate some useful FDT properties for us (notably the /memory node and KASLR seed) and fetch the DTB that it provides. Combined with the memory map changes above, this let's us entirely avoid configuring the memory map explicitly. == defconfig == Most of the board defconfigs and config headers were quite similar, to simplify maintenance going forward, all the fully generic boards (sdm845 and qcs404-evb so far) are adapted to use the new qcom_defconfig. Going forward, all new Qualcomm boards should be supported by this defconfig. A notable exception is for specific usecases (like U-Boot as the primary bootloader). == The older dragonboards == The db410c and db820c both have some custom board init code, as a result they aren't yet binary compatible. mach-snapdragon is adjusted so that all the necessary config options (e.g. CONFIG_SYS_BOARD) can be set from their defconfigs, this makes it possible to enable support for new boards without introducing additional config options. The db410c can run U-Boot either chainloaded like the other boards, or as a first-stage bootloader replacing aboot. However it was hardcoded to only build for the latter option. This series introduces a new "chainloaded" defconfig to enable easier testing via fastboot. == dynamic environment variables == This series also introduces runtime-allocated load addresses via the lmb allocator. This allows for booting on boards with vastly different memory layouts without any pre-calculation or macro magic in the config header. This feature is based on similar code in mach-apple. The soc, board, and fdtfile environment variables are also generated automatically. Many Qualcomm boards follow a similar scheme for DTB naming such that the name can often be derived from the root compatible properties. This is intended to cover the most common cases and be a simple solution for booting generic distro images without having to explicitly choose the right DTB. The U-Boot DTS can be tweaked if necessary to produce the correct name, the variable can be overwritten, or a bootloader like GRUB can load the devicetree instead. == Upstream DT == All Qualcomm boards have had their devicetree files rewritten to be based on the upstream SoC/PMIC DTSI files. Previous patch series made the necessary driver adjustments to fully support the upstream DT format. All future Qualcomm boards should use upstream DTS by default. --- I have tested this series on the Dragonboard410c, Dragonboard820c, and Dragonboard845c. I unfortunately don't have access to a QCS404 EVB board to test. This series is based on the qcom-next branch [1] and depends on my PMIC fixes series [2], an integration branch for testing can be found at [3]. The non-qualcomm-specific changes (patches 1, 2, and 3) don't have any dependencies. [1]: https://source.denx.de/u-boot/custodians/u-boot-snapdragon [2]: https://lore.kernel.org/u-boot/20231114-b4-qcom-dt-compat-v3-0-88a92f8f00ba… [3]: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/tree/b4/qcom-c… To: Neil Armstrong <neil.armstrong(a)linaro.org> To: Sumit Garg <sumit.garg(a)linaro.org> To: Ramon Fried <rfried.dev(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> To: Dzmitry Sankouski <dsankouski(a)gmail.com> To: Caleb Connolly <caleb.connolly(a)linaro.org> To: Peng Fan <peng.fan(a)nxp.com> To: Jaehoon Chung <jh80.chung(a)samsung.com> To: Rayagonda Kokatanur <rayagonda.kokatanur(a)broadcom.com> To: Lukasz Majewski <lukma(a)denx.de> To: Sean Anderson <seanga2(a)gmail.com> To: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz(a)gmail.com> To: Stephan Gerhold <stephan(a)gerhold.net> Cc: <u-boot(a)lists.denx.de> --- Caleb Connolly (21): arm: init: export prev_bl_fdt_addr arm: allow CONFIG_LINUX_KERNEL_IMAGE_HEADER to be set in defconfig usb: dwc3-generic: support external vbus regulator mmc: msm_sdhci: use modern clock handling dt-bindings: drop msm_sdhci binding clk/qcom: use upstream compatible properties serial: msm: add debug UART serial: msm: fix clock handling configs: add dragonboard410c_chainloaded_defconfig dts: dragonboard410c: fix compatible and clocks board: dragonboard410c: import board code from mach-snapdragon board: dragonboard820c: use LINUX_KERNEL_IMAGE_HEADER mach-snapdragon: generalise board support mach-snapdragon: dynamic load addresses mach-snapdragon: generate fdtfile automatically doc: board/qualcomm: document generic targets dts: sdm845: import DT from Linux dts: msm8916: import DT from Linux dts: msm8996: import DT from Linux dts: qcs404-evb: import DT from Linux MAINTAINERS: Qualcomm: add some missing paths MAINTAINERS | 16 +- arch/arm/Kconfig | 6 +- arch/arm/dts/Makefile | 9 +- arch/arm/dts/dragonboard410c-uboot.dtsi | 44 - arch/arm/dts/dragonboard410c.dts | 198 +- arch/arm/dts/dragonboard820c-uboot.dtsi | 32 - arch/arm/dts/dragonboard820c.dts | 129 +- arch/arm/dts/dragonboard845c-uboot.dtsi | 26 - arch/arm/dts/dragonboard845c.dts | 23 +- arch/arm/dts/msm8916-pins.dtsi | 582 ++ arch/arm/dts/msm8916-pm8916.dtsi | 76 + arch/arm/dts/msm8916.dtsi | 2194 ++++++++ arch/arm/dts/msm8996.dtsi | 3959 +++++++++++++ arch/arm/dts/pm8916.dtsi | 183 + arch/arm/dts/pm8994.dtsi | 152 + arch/arm/dts/pm8998.dtsi | 130 + arch/arm/dts/pms405.dtsi | 149 + arch/arm/dts/qcs404-evb-uboot.dtsi | 30 - arch/arm/dts/qcs404-evb.dts | 441 +- arch/arm/dts/qcs404.dtsi | 1830 ++++++ arch/arm/dts/sdm845.dtsi | 5850 +++++++++++++++++++- arch/arm/dts/starqltechn-uboot.dtsi | 27 - arch/arm/dts/starqltechn.dts | 34 +- arch/arm/lib/save_prev_bl_data.c | 5 + arch/arm/mach-snapdragon/Kconfig | 95 +- arch/arm/mach-snapdragon/Makefile | 8 +- arch/arm/mach-snapdragon/board.c | 303 + arch/arm/mach-snapdragon/include/mach/dram.h | 12 - arch/arm/mach-snapdragon/init_sdm845.c | 73 - arch/arm/mach-snapdragon/misc.c | 55 - arch/arm/mach-snapdragon/sysmap-apq8016.c | 31 - arch/arm/mach-snapdragon/sysmap-apq8096.c | 31 - arch/arm/mach-snapdragon/sysmap-qcs404.c | 43 - arch/arm/mach-snapdragon/sysmap-sdm845.c | 31 - board/qualcomm/dragonboard410c/Kconfig | 15 - board/qualcomm/dragonboard410c/MAINTAINERS | 1 + board/qualcomm/dragonboard410c/Makefile | 3 +- board/qualcomm/dragonboard410c/dragonboard410c.c | 31 +- .../qualcomm/dragonboard410c/misc.c | 51 +- .../mach => board/qualcomm/dragonboard410c}/misc.h | 1 + board/qualcomm/dragonboard820c/Kconfig | 15 - board/qualcomm/dragonboard820c/Makefile | 1 - board/qualcomm/dragonboard820c/dragonboard820c.c | 39 +- board/qualcomm/dragonboard820c/head.S | 33 - board/qualcomm/dragonboard820c/u-boot.lds | 111 - board/qualcomm/dragonboard845c/Kconfig | 12 - board/qualcomm/qcs404-evb/Kconfig | 15 - board/qualcomm/qcs404-evb/qcs404-evb.c | 21 +- configs/dragonboard410c_chainloaded_defconfig | 72 + configs/dragonboard410c_defconfig | 6 +- configs/dragonboard820c_defconfig | 6 +- configs/dragonboard845c_defconfig | 29 - configs/qcom_defconfig | 71 + configs/qcs404evb_defconfig | 55 - configs/starqltechn_defconfig | 41 - doc/board/qualcomm/board.rst | 119 + doc/board/qualcomm/debugging.rst | 61 + doc/board/qualcomm/index.rst | 4 +- doc/board/qualcomm/qcs404.rst | 79 - doc/board/qualcomm/sdm845.rst | 162 - doc/device-tree-bindings/mmc/msm_sdhci.txt | 25 - doc/device-tree-bindings/usb/ehci-msm.txt | 10 - drivers/clk/qcom/clock-apq8016.c | 9 +- drivers/clk/qcom/clock-apq8096.c | 7 +- drivers/mmc/msm_sdhci.c | 69 +- drivers/phy/qcom/msm8916-usbh-phy.c | 2 +- drivers/pinctrl/qcom/pinctrl-apq8016.c | 2 +- drivers/serial/Kconfig | 8 + drivers/serial/serial_msm.c | 61 +- drivers/usb/dwc3/dwc3-generic.c | 12 + drivers/usb/host/ehci-msm.c | 2 +- include/configs/dragonboard845c.h | 20 - include/configs/qcom.h | 21 + include/configs/qcs404-evb.h | 20 - include/dt-bindings/arm/coresight-cti-dt.h | 37 + include/dt-bindings/clock/qcom,camcc-sdm845.h | 116 + include/dt-bindings/clock/qcom,dispcc-sdm845.h | 56 + include/dt-bindings/clock/qcom,gcc-msm8916.h | 179 + include/dt-bindings/clock/qcom,gcc-msm8996.h | 360 ++ include/dt-bindings/clock/qcom,gcc-qcs404.h | 4 + include/dt-bindings/clock/qcom,gpucc-sdm845.h | 24 + include/dt-bindings/clock/qcom,lpass-sdm845.h | 15 + include/dt-bindings/clock/qcom,mmcc-msm8996.h | 295 + include/dt-bindings/clock/qcom,rpmcc.h | 174 + include/dt-bindings/clock/qcom,rpmh.h | 37 + include/dt-bindings/clock/qcom,turingcc-qcs404.h | 15 + include/dt-bindings/clock/qcom,videocc-sdm845.h | 35 + include/dt-bindings/dma/qcom-gpi.h | 11 + include/dt-bindings/firmware/qcom,scm.h | 18 + include/dt-bindings/iio/qcom,spmi-vadc.h | 300 + include/dt-bindings/interconnect/qcom,msm8916.h | 100 + .../dt-bindings/interconnect/qcom,msm8996-cbf.h | 12 + include/dt-bindings/interconnect/qcom,msm8996.h | 163 + include/dt-bindings/interconnect/qcom,osm-l3.h | 15 + include/dt-bindings/interconnect/qcom,sdm845.h | 150 + include/dt-bindings/phy/phy-qcom-qusb2.h | 37 + include/dt-bindings/pinctrl/qcom,pmic-gpio.h | 164 + include/dt-bindings/power/qcom-rpmpd.h | 412 ++ include/dt-bindings/reset/qcom,gcc-msm8916.h | 100 + include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 + include/dt-bindings/reset/qcom,sdm845-pdc.h | 22 + include/dt-bindings/soc/qcom,apr.h | 28 + include/dt-bindings/soc/qcom,rpmh-rsc.h | 14 + include/init.h | 11 + 104 files changed, 18987 insertions(+), 2063 deletions(-) --- base-commit: 516584b4d50880cb5e2361e55f8c5b4fc6c35901 // Caleb (they/them)

14 90

[PATCH] mtd: spi-nor-core: Implement spi_nor_read_sfdp_dma_unsafe() for sfdp parse
by Vaishnav Achath 12 Dec '23

12 Dec '23

During SFDP header parse and BFPT parse, structures in stack are used to perform spi_nor_read_sfdp() which expects a dma-safe buffer. This commit introduces spi_nor_read_sfdp_dma_unsafe() to wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer which is the same implementation in Linux (drivers/mtd/spi-nor/sfdp.c). Signed-off-by: Vaishnav Achath <vaishnav.a(a)ti.com> --- drivers/mtd/spi/spi-nor-core.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 3b7c817c02..90d05da1d8 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2022,6 +2022,36 @@ read_err: return ret; } +/** + * spi_nor_read_sfdp_dma_unsafe() - read Serial Flash Discoverable Parameters. + * @nor: pointer to a 'struct spi_nor' + * @addr: offset in the SFDP area to start reading data from + * @len: number of bytes to read + * @buf: buffer where the SFDP data are copied into + * + * Wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer as @buf is now not + * guaranteed to be dma-safe. + * + * Return: -ENOMEM if kmalloc() fails, the return code of spi_nor_read_sfdp() + * otherwise. + */ +static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr, + size_t len, void *buf) +{ + void *dma_safe_buf; + int ret; + + dma_safe_buf = kmalloc(len, GFP_KERNEL); + if (!dma_safe_buf) + return -ENOMEM; + + ret = spi_nor_read_sfdp(nor, addr, len, dma_safe_buf); + memcpy(buf, dma_safe_buf, len); + kfree(dma_safe_buf); + + return ret; +} + /* Fast Read settings. */ static void @@ -2195,7 +2225,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, bfpt_header->length * sizeof(u32)); addr = SFDP_PARAM_HEADER_PTP(bfpt_header); memset(&bfpt, 0, sizeof(bfpt)); - err = spi_nor_read_sfdp(nor, addr, len, &bfpt); + err = spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt); if (err < 0) return err; @@ -2480,7 +2510,7 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor, int i, err; /* Get the SFDP header. */ - err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header); + err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(header), &header); if (err < 0) return err; -- 2.17.1

4 4

[PATCH] tqma6: Fix DDR configuration
by Miquel Raynal 12 Dec '23

12 Dec '23

Initially investigating a Linux network issue causing a lot of drop and poor network performances on a custom system based on a TQMA6A module (based on an iMX6Q), [1st link below]. I eventually correlated my observations with a contention at the NIC level when in concurrency with the graphics pipeline. Troubleshooting this in the kernel lead to disabling DMA bursts accesses made by the IPU in order to avoid triggering the QoS at the interconnect level, reducing from 50 to 10% the drop rate on eth0, [2nd link below]. The solution worked on my setup but not on others, which still suffered from abnormally high drop rates even with this "fix". After looking a while into TQ Systems BSP I figured out a number of differences in recent U-Boot out-of-tree patches they had in their repository [3rd link]. Parsing the differences one after the other lead me to this final solution. The reset pad of the DDR controller was apparently misconfigured, Bit 18-19 picturing the "DDR select field". The current value b11 is reserved. The only defined value as of version 6 of the iMX6Q manual was b00 "DDR3 and LPDDR2 mode". In practice no register difference has been spotted after changing this configuration but all issues tracked thus far just vanished. All previous fixes have been proven irrelevant. Just clearing this field solved all our network issues and the drop rate as measured by iperf3 felt back to 0%. Link: https://lore.kernel.org/netdev/20231012193410.3d1812cf@xps-13/ Link: https://lists.freedesktop.org/archives/dri-devel/2023-October/428251.html Link: https://github.com/tq-systems/u-boot-tqmaxx/commit/15eb6abbefbf6916c28467b8… Signed-off-by: Miquel Raynal <miquel.raynal(a)bootlin.com> --- board/tq/tqma6/tqma6q.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/tq/tqma6/tqma6q.cfg b/board/tq/tqma6/tqma6q.cfg index a49489aed3f..a345c4de93d 100644 --- a/board/tq/tqma6/tqma6q.cfg +++ b/board/tq/tqma6/tqma6q.cfg @@ -36,7 +36,7 @@ DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 -DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 +DATA 4, MX6_IOM_DRAM_RESET, 0x00003030 DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 -- 2.34.1

2 4

[PATCH] imx8mp_evk: Select CONFIG_NET_RANDOM_ETHADDR
by Fabio Estevam 12 Dec '23

12 Dec '23

From: Fabio Estevam <festevam(a)denx.de> On an early revision of the imx8mp-evk that I have access to, the MAC addresses fuses are not programmed, causing failure to bring the Ethernet interfaces. Fix this problema by selecting CONFIG_NET_RANDOM_ETHADDR so that random MAC addresses are assigned and the Ethernet ports become functional out of the box. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- configs/imx8mp_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index d538b85c1f8c..08998a63e756 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -74,6 +74,7 @@ CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y -- 2.34.1

1 1