December 2023 - U-Boot

[PATCH] imx8mn-var-som: Simplify FEC initialization
by Hugo Villeneuve 13 Dec '23

13 Dec '23

From: Hugo Villeneuve <hvilleneuve(a)dimonoff.com> With DM enabled, there is no need for board code to initialize the FEC interface. The ethernet PHYs on the symphony carrier board have a dedicated crystal/oscillator. If the SOM has the EC configuration option (onboard ethernet PHY), it also has a dedicated crystal/oscillator. So in all cases, there is no need to enable the RGMII TX clk output. This follows a similar change introduced by Fabio Estevam: Link: https://lore.kernel.org/u-boot/20231019170441.1610453-1-festevam@gmail.com/ Signed-off-by: Hugo Villeneuve <hvilleneuve(a)dimonoff.com> --- board/variscite/imx8mn_var_som/imx8mn_var_som.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c index 61b9455a8f4..994fd4f7058 100644 --- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c +++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c @@ -12,7 +12,6 @@ #include <fdt_support.h> #include <i2c_eeprom.h> #include <malloc.h> -#include <asm/io.h> #include <asm/global_data.h> #include <dt-bindings/gpio/gpio.h> #include <linux/libfdt.h> @@ -46,20 +45,8 @@ struct var_imx8_eeprom_info { u8 partnumber2[5]; /* Part number 2 */ } __packed; -static void setup_fec(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* Use 125M anatop REF_CLK1 for ENET1, not from external */ - clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); -} - int board_init(void) { - if (IS_ENABLED(CONFIG_FEC_MXC)) - setup_fec(); - return 0; } base-commit: 4655b75335384e040358a2e3e478cc42f32a96c9 -- 2.39.2

2 2

[PATCH] imx8mn_var_som: Add myself to MAINTAINERS
by Hugo Villeneuve 13 Dec '23

13 Dec '23

From: Hugo Villeneuve <hvilleneuve(a)dimonoff.com> I would like to help maintaining the imx8mn_var_som symphony board. Add myself to MAINTAINERS. Signed-off-by: Hugo Villeneuve <hvilleneuve(a)dimonoff.com> --- board/variscite/imx8mn_var_som/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/variscite/imx8mn_var_som/MAINTAINERS b/board/variscite/imx8mn_var_som/MAINTAINERS index 068f807ae69..367f72dfe4f 100644 --- a/board/variscite/imx8mn_var_som/MAINTAINERS +++ b/board/variscite/imx8mn_var_som/MAINTAINERS @@ -1,5 +1,6 @@ ARM i.MX8MN VARISCITE VAR-SOM-MX8MN MODULE M: Ariel D'Alessandro <ariel.dalessandro(a)collabora.com> +M: Hugo Villeneuve <hvilleneuve(a)dimonoff.com> S: Maintained F: arch/arm/dts/imx8mn-var-som* F: board/variscite/imx8mn_var_som/ base-commit: 4655b75335384e040358a2e3e478cc42f32a96c9 -- 2.39.2

2 2

[PATCH] clock_imx8mm: Add a stub for imx8mp_fec_interface_init()
by Fabio Estevam 13 Dec '23

13 Dec '23

From: Fabio Estevam <festevam(a)denx.de> When CONFIG_DWC_ETH_QOS_IMX=y and CONFIG_FEC_MXC is not selected, the following warning is seen: arch/arm/mach-imx/imx8m/clock_imx8mm.c: In function 'board_interface_eth_init': arch/arm/mach-imx/imx8m/clock_imx8mm.c:914:24: warning: implicit declaration of function 'imx8mp_fec_interface_init; did you mean 'imx8mp_eqos_interface_init'? [-Wimplicit-function-declaration] Fix it by adding a stub for imx8mp_fec_interface_init() to handle this case. This follows the same approach done on imx8mp_eqos_interface_init(). Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 986870799d36..5cf97a5ea952 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -904,6 +904,13 @@ static int imx8mp_fec_interface_init(struct udevice *dev, return 0; } +#else +static int imx8mp_fec_interface_init(struct udevice *dev, + phy_interface_t interface_type, + bool mx8mp) +{ + return 0; +} #endif int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type) -- 2.34.1

2 2

[PATCH v3 1/2] imx8mp_evk: Simplify Ethernet initialization
by Fabio Estevam 13 Dec '23

13 Dec '23

From: Fabio Estevam <festevam(a)denx.de> With DM enabled, there is no need for board code to initialize the Ethernet interfaces. The RTL8211FDI Ethernet PHYs have 25MHz oscillator, so there is no need to enable the RGMII TX clk output. Also, there is no need for describing the deprecated phy-reset FEC properties, nor passing reset properties to the EQOS interface in u-boot.dtsi. Remove all these unneeded pieces. Tested both Ethernet interfaces after these changes. Signed-off-by: Fabio Estevam <festevam(a)denx.de> Reviewed-by: Hugo Villeneuve <hvilleneuve(a)dimonoff.com> --- Changes since v2: - Only collected Hugo's tag. arch/arm/dts/imx8mp-evk-u-boot.dtsi | 14 ------------- board/freescale/imx8mp_evk/imx8mp_evk.c | 28 +------------------------ 2 files changed, 1 insertion(+), 41 deletions(-) diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 0bf489b46248..51c84383673c 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -137,17 +137,3 @@ &wdog1 { bootph-pre-ram; }; - -&ethphy0 { - reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - reset-delay-us = <15000>; - reset-post-delay-us = <100000>; -}; - -&fec { - phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - phy-reset-duration = <15>; - phy-reset-post-delay = <100>; -}; - - diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c index a24b8c1d8608..42291c958e39 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c @@ -7,8 +7,6 @@ #include <env.h> #include <errno.h> #include <init.h> -#include <miiphy.h> -#include <netdev.h> #include <linux/delay.h> #include <asm/global_data.h> #include <asm/mach-imx/iomux-v3.h> @@ -20,33 +18,9 @@ DECLARE_GLOBAL_DATA_PTR; -static void setup_fec(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* Enable RGMII TX clk output */ - setbits_le32(&gpr->gpr[1], BIT(22)); -} - -#if CONFIG_IS_ENABLED(NET) -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - return 0; -} -#endif - int board_init(void) { - int ret = 0; - - if (IS_ENABLED(CONFIG_FEC_MXC)) { - setup_fec(); - } - - return ret; + return 0; } int board_late_init(void) -- 2.34.1

2 3

[PATCH] phy: phy-imx8mq-usb: Remove .exit operation
by Fabio Estevam 13 Dec '23

13 Dec '23

From: Fabio Estevam <festevam(a)denx.de> Currently, when running "ums 0 mmc 2" and breaking it via CTRL + C, the following message is seen: u-boot=> ums 0 mmc 1 UMS: LUN 0, dev mmc 1, hwpart 0, sector 0x0, count 0x1dacc00 CTRL+C - Operation aborted clk usb_phy_root_clk already disabled The USB PHY clock is disabled twice: first it gets disabled inside imx8mq_usb_phy_power_off(), then it is disabled again inside imx8mq_usb_phy_exit(). Let the USB PHY clock be disabled only once inside imx8mq_usb_phy_power_off() by removing the .exit operation. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- drivers/phy/phy-imx8mq-usb.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/phy/phy-imx8mq-usb.c b/drivers/phy/phy-imx8mq-usb.c index b660eadecf1c..e5e96e77a681 100644 --- a/drivers/phy/phy-imx8mq-usb.c +++ b/drivers/phy/phy-imx8mq-usb.c @@ -231,16 +231,10 @@ static int imx8mq_usb_phy_power_off(struct phy *usb_phy) return 0; } -static int imx8mq_usb_phy_exit(struct phy *usb_phy) -{ - return imx8mq_usb_phy_power_off(usb_phy); -} - struct phy_ops imx8mq_usb_phy_ops = { .init = imx8mpq_usb_phy_init, .power_on = imx8mq_usb_phy_power_on, .power_off = imx8mq_usb_phy_power_off, - .exit = imx8mq_usb_phy_exit, }; int imx8mq_usb_phy_probe(struct udevice *dev) -- 2.34.1

2 2

[PATCH v2 1/3] arm: dts: imx8mm: Sync with linux-next 20231019
by Fabio Estevam 13 Dec '23

13 Dec '23

From: Fabio Estevam <festevam(a)denx.de> Sync imx8mm.dtsi with linux-next 20231019. The motivation for doing this sync was a bug when doing "ums 0 mmc 1" on imx8mm-evk. It worked well for the first time, but after doing a CTRL+C and launching the ums again, the command did not work. Adam Ford suggested to sync imx8mm.dtsi with the Linux dts, as there was a recent USB power domain reorganization there. After syncing the imx8mm.dtsi with Linux, the ums command works without problem after a CTRL+C. Suggested-by: Adam Ford <aford173(a)gmail.com> Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- Changes since v1: - Rebased against latest U-Boot and synced with linux-next 20231019. arch/arm/dts/imx8mm.dtsi | 153 +++++++++++++++++++++++++++++++++------ 1 file changed, 129 insertions(+), 24 deletions(-) diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi index afb90f59c83c..738024baaa57 100644 --- a/arch/arm/dts/imx8mm.dtsi +++ b/arch/arm/dts/imx8mm.dtsi @@ -139,6 +139,7 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; @@ -276,6 +277,7 @@ assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; clock-names = "main_clk"; + power-domains = <&pgc_otg1>; }; usbphynop2: usbphynop2 { @@ -285,6 +287,7 @@ assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; clock-names = "main_clk"; + power-domains = <&pgc_otg2>; }; soc: soc@0 { @@ -396,6 +399,7 @@ "pll8k", "pll11k", "clkext3"; dmas = <&sdma2 24 25 0x80000000>; dma-names = "rx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -493,6 +497,8 @@ compatible = "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; }; @@ -547,8 +553,8 @@ reg = <0x30330000 0x10000>; }; - gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; + gpr: syscon@30340000 { + compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; @@ -560,22 +566,40 @@ #address-cells = <1>; #size-cells = <1>; - imx8mm_uid: unique-id@410 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = <ADDR SIZE>; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x4 0x8> describes fuses 0x410 and + * 0x420). + */ + imx8mm_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - fec_mac_address: mac-address@90 { + tmu_calib: calib@3c { /* 0x4f0 */ + reg = <0x3c 4>; + }; + + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; }; - anatop: anatop@30360000 { - compatible = "fsl,imx8mm-anatop", "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; + #clock-cells = <1>; }; snvs: snvs@30370000 { @@ -674,13 +698,11 @@ pgc_otg1: power-domain@2 { #power-domain-cells = <0>; reg = <IMX8MM_POWER_DOMAIN_OTG1>; - power-domains = <&pgc_hsiomix>; }; pgc_otg2: power-domain@3 { #power-domain-cells = <0>; reg = <IMX8MM_POWER_DOMAIN_OTG2>; - power-domains = <&pgc_hsiomix>; }; pgc_gpumix: power-domain@4 { @@ -1098,6 +1120,61 @@ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + lcdif: lcdif@32e00000 { + compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_AXI>, + <&clk IMX8MM_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, + <&clk IMX8MM_SYS_PLL2_1000M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <594000000>, <500000000>, <200000000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>; + status = "disabled"; + + port { + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: dsi@32e10000 { + compatible = "fsl,imx8mm-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + clock-names = "bus_clk", "sclk_mipi"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <266000000>, <24000000>; + samsung,pll-clock-frequency = <24000000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + }; + csi: csi@32e20000 { compatible = "fsl,imx8mm-csi", "fsl,imx7-csi"; reg = <0x32e20000 0x1000>; @@ -1145,10 +1222,9 @@ compatible = "fsl,imx8mm-mipi-csi2"; reg = <0x32e30000 0x1000>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>, - <&clk IMX8MM_CLK_CSI1_PHY_REF>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>, - <&clk IMX8MM_SYS_PLL2_1000M>; + assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>; + clock-frequency = <333000000>; clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, <&clk IMX8MM_CLK_CSI1_ROOT>, @@ -1177,7 +1253,7 @@ }; usbotg1: usb@32e40000 { - compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x32e40000 0x200>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; @@ -1186,18 +1262,19 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; - power-domains = <&pgc_otg1>; + power-domains = <&pgc_hsiomix>; status = "disabled"; }; usbmisc1: usbmisc@32e40200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; #index-cells = <1>; reg = <0x32e40200 0x200>; }; usbotg2: usb@32e50000 { - compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x32e50000 0x200>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; @@ -1206,12 +1283,13 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop2>; fsl,usbmisc = <&usbmisc2 0>; - power-domains = <&pgc_otg2>; + power-domains = <&pgc_hsiomix>; status = "disabled"; }; usbmisc2: usbmisc@32e50200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; #index-cells = <1>; reg = <0x32e50200 0x200>; }; @@ -1238,16 +1316,15 @@ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; }; - gpmi: nand-controller@33002000{ + gpmi: nand-controller@33002000 { compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; reg = <0x33002000 0x2000>, <0x33004000 0x4000>; reg-names = "gpmi-nand", "bch"; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; @@ -1268,8 +1345,8 @@ #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ - 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ + <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; num-viewport = <4>; interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; @@ -1282,12 +1359,40 @@ <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; linux,pci-domain = <0>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "apps", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + + pcie0_ep: pcie-ep@33800000 { + compatible = "fsl,imx8mm-pcie-ep"; + reg = <0x33800000 0x400000>, + <0x18000000 0x8000000>; + reg-names = "dbi", "addr_space"; + num-lanes = <1>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dma"; + fsl,max-link-speed = <2>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; reset-names = "apps", "turnoff"; phys = <&pcie_phy>; phy-names = "pcie-phy"; + num-ib-windows = <4>; + num-ob-windows = <4>; status = "disabled"; }; -- 2.34.1

2 4

[PATCH 1/2] imx8mp_evk: Convert to DM_PMIC
by Fabio Estevam 13 Dec '23

13 Dec '23

From: Fabio Estevam <festevam(a)denx.de> Currently, the imx8mp_evk uses the non-DM code to initialize the PMIC. Convert to DM_PMIC, which is the recommended way to access the PMIC. While at it, fix multi-line comments style. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- arch/arm/dts/imx8mp-evk-u-boot.dtsi | 18 ++++++++++- board/freescale/imx8mp_evk/spl.c | 50 +++++++++++++++-------------- configs/imx8mp_evk_defconfig | 12 +++---- 3 files changed, 47 insertions(+), 33 deletions(-) diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 9ed62f1bb02d..0bf489b46248 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -13,6 +13,22 @@ }; }; +&pinctrl_i2c1 { + bootph-all; +}; + +&pinctrl_pmic { + bootph-all; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { + bootph-all; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-all; +}; + &reg_usdhc2_vmmc { u-boot,off-on-delay-us = <20000>; }; @@ -66,7 +82,7 @@ }; &i2c1 { - bootph-pre-ram; + bootph-all; }; &i2c2 { diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index 246826a0d482..9dd2cbc799c3 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -67,40 +67,44 @@ struct i2c_pads_info i2c_pad_info1 = { }, }; -#if CONFIG_IS_ENABLED(POWER_LEGACY) -#define I2C_PMIC 0 +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) int power_init_board(void) { - struct pmic *p; + struct udevice *dev; int ret; - ret = power_pca9450_init(I2C_PMIC, 0x25); - if (ret) - printf("power init failed"); - p = pmic_get("PCA9450"); - pmic_probe(p); + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pmic@25\n"); + return 0; + } + if (ret < 0) + return ret; /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); /* - * increase VDD_SOC to typical value 0.95V before first - * DRAM access, set DVS1 to 0.85v for suspend. + * Increase VDD_SOC to typical value 0.95V before first + * DRAM access, set DVS1 to 0.85V for suspend. * Enable DVS control through PMIC_STBY_REQ and * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ -#ifdef CONFIG_IMX8M_VDD_SOC_850MV - /* set DVS0 to 0.85v for special case*/ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14); -#else - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); -#endif - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV)) + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); - /* Kernel uses OD/OD freq for SOC */ - /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ - pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* + * Kernel uses OD/OD freq for SOC. + * To avoid timing risk from SOC to ARM,increase VDD_ARM to OD + * voltage 0.95V. + */ + + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); return 0; } @@ -135,8 +139,6 @@ void board_init_f(ulong dummy) enable_tzc380(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - power_init_board(); /* DDR initialization */ diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 820dc36e9cdd..0675f0f4f41b 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -7,9 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" CONFIG_SPL_TEXT_BASE=0x920000 @@ -88,8 +85,6 @@ CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y -# CONFIG_SPL_DM_I2C is not set -CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_SUPPORT_EMMC_BOOT=y @@ -110,15 +105,16 @@ CONFIG_PHY_IMX8MQ_USB=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y -CONFIG_SPL_POWER_LEGACY=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y -CONFIG_POWER_PCA9450=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_POWER_I2C=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y -- 2.34.1

2 5

[PATCH] arm: dts: imx8mp-venice-gw73xx: add TPM device
by Tim Harvey 13 Dec '23

13 Dec '23

Add the TPM device found on the GW73xx revision F PCB. This hangs off of SPI2, uses gpio1_10 as a CS and gpio1_11 as RST#. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi | 9 +++++++++ arch/arm/dts/imx8mp-venice-gw73xx.dtsi | 9 ++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi index 70433c073293..4d0e9a1e67c5 100644 --- a/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi @@ -10,6 +10,15 @@ reset-post-delay-us = <300000>; }; +&gpio1 { + tpm_rst { + gpio-hog; + output-high; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "tpm_rst#"; + }; +}; + &gpio4 { dio_1 { gpio-hog; diff --git a/arch/arm/dts/imx8mp-venice-gw73xx.dtsi b/arch/arm/dts/imx8mp-venice-gw73xx.dtsi index 1c05398c862c..88c3c006fa20 100644 --- a/arch/arm/dts/imx8mp-venice-gw73xx.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw73xx.dtsi @@ -95,8 +95,14 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + tpm@1 { + compatible = "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &gpio4 { @@ -327,6 +333,7 @@ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 >; }; -- 2.25.1

2 2

[PATCH] arm: dts: imx8mm-venice-gw73xx: add TPM device
by Tim Harvey 13 Dec '23

13 Dec '23

Add the TPM device found on the GW73xx revision F PCB. This hangs off of SPI2, uses gpio1_10 as a CS and gpio1_11 as RST#. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi | 7 +++++++ arch/arm/dts/imx8mm-venice-gw73xx.dtsi | 10 +++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi index 92e44d4ba96b..31f9d47bced8 100644 --- a/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi @@ -39,6 +39,13 @@ gpios = <9 GPIO_ACTIVE_HIGH>; line-name = "dio1"; }; + + tpm_rst { + gpio-hog; + output-high; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "tpm_rst#"; + }; }; &gpio4 { diff --git a/arch/arm/dts/imx8mm-venice-gw73xx.dtsi b/arch/arm/dts/imx8mm-venice-gw73xx.dtsi index 244ef8d6cc68..7b2130dbdb21 100644 --- a/arch/arm/dts/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw73xx.dtsi @@ -104,8 +104,15 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + + tpm@1 { + compatible = "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &gpio1 { @@ -364,6 +371,7 @@ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 >; }; -- 2.25.1

2 2

[PATCH] imx8mn-var-som: add manufacturer to target description
by Hugo Villeneuve 13 Dec '23

13 Dec '23

From: Hugo Villeneuve <hvilleneuve(a)dimonoff.com> Add Variscite manufacturer to the IMX8MN_VAR_SOM target menu label as the majority of targets include the manufacturer as part of their menu description/label and it helps when looking for a particular manufacturer/board. Signed-off-by: Hugo Villeneuve <hvilleneuve(a)dimonoff.com> --- arch/arm/mach-imx/imx8m/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 3d62d7052e7..5cf862a8eb0 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -249,7 +249,7 @@ config TARGET_PICO_IMX8MQ select IMX8M_LPDDR4 config TARGET_IMX8MN_VAR_SOM - bool "imx8mn_var_som" + bool "Variscite imx8mn_var_som" select BINMAN select IMX8MN select SUPPORT_SPL base-commit: e65b5d35c9116485366bb08138043d51220551da -- 2.39.2

2 2