November 2023 - U-Boot

[PATCH v4 0/5] Qualcomm PMIC fixes
by Caleb Connolly 28 Nov '23

28 Nov '23

This series addresses some long-standing issues with the SPMI arb driver, the PMIC, and the PMIC GPIO. It fixes compatibility with upstream Linux devicetrees, and simplifies pwrkey/resin support by rewriting the pon driver to be a button driver rather than a GPIO driver. Existing users are adjusted to use the new button driver in their oard init code. This series is based on the pinctrl [1] and clock [2] cleanup series. There may be some DTS conflicts applying it standalone. [1]: https://lore.kernel.org/u-boot/20231106-b4-qcom-pinctrl-v2-0-406e8d8689ca@l… [2]: https://lore.kernel.org/u-boot/20231103-b4-qcom-clk-v3-0-8d2d460ece84@linar… --- Changes in v4: * Remove some now unsupported DT binding docs * Fix qcs404 SPMI arb dts * Link to v3: https://lore.kernel.org/r/20231114-b4-qcom-dt-compat-v3-0-88a92f8f00ba@lina… Changes in v3: * Remove now-unneeded header includes in dragonboard{410,820}c-uboot.dtsi * Drop non-standard DTS support from PMIC GPIO driver * Also remove old gpio-keys nodes from starqltechn-uboot.dtsi * Link to v2: https://lore.kernel.org/r/20231108-b4-qcom-dt-compat-v2-0-713233c72948@lina… Changes in v2: * Avoid using non-standard "label" and "linux,code" properties for buttons * Add missing sdm845 DTS parts * Put button driver in drivers/button * Link to v1: https://lore.kernel.org/r/20231106-b4-qcom-dt-compat-v1-0-0ccbb7841241@lina… --- Caleb Connolly (5): gpio: qcom_pmic: fix silent dev_read_addr downcast gpio: qcom_pmic: rework pwrkey driver into a button driver gpio: qcom_pmic: fix support for upstream DT spmi: msm: fix register range names pmic: qcom: dont use dev_read_addr to get USID MAINTAINERS | 1 + arch/arm/dts/dragonboard410c-uboot.dtsi | 11 -- arch/arm/dts/dragonboard410c.dts | 25 +++- arch/arm/dts/dragonboard820c-uboot.dtsi | 12 -- arch/arm/dts/dragonboard820c.dts | 26 ++-- arch/arm/dts/dragonboard845c-uboot.dtsi | 11 -- arch/arm/dts/dragonboard845c.dts | 4 + arch/arm/dts/qcs404-evb.dts | 9 +- arch/arm/dts/sdm845.dtsi | 28 ++-- arch/arm/dts/starqltechn-uboot.dtsi | 10 -- arch/arm/dts/starqltechn.dts | 20 +-- arch/arm/mach-snapdragon/Kconfig | 3 + arch/arm/mach-snapdragon/init_sdm845.c | 45 ++----- board/qualcomm/dragonboard410c/dragonboard410c.c | 31 ++--- board/qualcomm/dragonboard820c/dragonboard820c.c | 29 ++-- doc/device-tree-bindings/gpio/pm8916_gpio.txt | 48 ------- doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt | 94 ------------- doc/device-tree-bindings/spmi/spmi-msm.txt | 26 ---- drivers/button/Kconfig | 9 ++ drivers/button/Makefile | 1 + drivers/button/button-qcom-pmic.c | 165 +++++++++++++++++++++++ drivers/gpio/Kconfig | 3 +- drivers/gpio/qcom_pmic_gpio.c | 146 +++++--------------- drivers/power/pmic/pmic_qcom.c | 13 +- drivers/spmi/spmi-msm.c | 46 +++---- 25 files changed, 341 insertions(+), 475 deletions(-) --- base-commit: d1efa48e205960b15656eb0c13227110895f1cc9 // Caleb (they/them)

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Please pull u-boot-samsung master
by Minkyu Kang 28 Nov '23

28 Nov '23

Dear Tom, The following changes since commit 17e9db18f17b6cad278694d4a61df95e96bdf4f5: Merge tag 'doc-2024-01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi (2023-11-11 09:22:54 -0500) are available in the git repository at: git@source.denx.de:u-boot/custodians/u-boot-samsung.git master for you to fetch changes up to 470682ace1e03a6573d6eef9a00b524d608ddfa7: configs: Remove unneeded SYS_CONFIG_NAME from a*y17lte defconfigs (2023-11-27 18:57:35 +0900) ---------------------------------------------------------------- Sam Protsenko (13): arm: exynos: Include missing CPU header in soc.c arm: exynos: Include missing CPU header in gpio.h watchdog: s5p_wdt: Include missing CPU header exynos: Avoid duplicate reset_cpu with SYSRESET enabled serial: s5p: Fix clk_get_by_index() error code check clk: exynos: Add header guard for clk-pll.h serial: s5p: Remove common.h inclusion serial: s5p: Use livetree API to get "id" property serial: s5p: Use named constants for register values serial: s5p: Improve coding style serial: s5p: Use dev_read_addr_ptr() to get base address board: samsung: Fix SYS_CONFIG_NAME configs in axy17lte Kconfig configs: Remove unneeded SYS_CONFIG_NAME from a*y17lte defconfigs arch/arm/mach-exynos/include/mach/gpio.h | 3 +++ arch/arm/mach-exynos/soc.c | 3 +++ board/samsung/axy17lte/Kconfig | 14 +++--------- configs/a3y17lte_defconfig | 1 - configs/a5y17lte_defconfig | 1 - configs/a7y17lte_defconfig | 1 - drivers/clk/exynos/clk-pll.h | 5 +++++ drivers/serial/serial_s5p.c | 79 +++++++++++++++++++++++++++++++++++++------------------------------- drivers/watchdog/s5p_wdt.c | 1 + Thanks, Minkyu Kang.

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[PATCH v1 0/1] Step up as co-maintainer of Tegra SOC platform
by Svyatoslav Ryhel 28 Nov '23

28 Nov '23

I would like to volunteer as Tegra SOC co-maintainer. Svyatoslav Ryhel (1): MAINTAINERS: Step up as co-maintainer of Tegra SOC platform MAINTAINERS | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) -- 2.39.2

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[PATCH v3 0/5] Qualcomm PMIC fixes
by Caleb Connolly 28 Nov '23

28 Nov '23

This series addresses some long-standing issues with the SPMI arb driver, the PMIC, and the PMIC GPIO. It fixes compatibility with upstream Linux devicetrees, and simplifies pwrkey/resin support by rewriting the pon driver to be a button driver rather than a GPIO driver. Existing users are adjusted to use the new button driver in their oard init code. This series is based on the pinctrl [1] and clock [2] cleanup series. There may be some DTS conflicts applying it standalone. [1]: https://lore.kernel.org/u-boot/20231106-b4-qcom-pinctrl-v2-0-406e8d8689ca@l… [2]: https://lore.kernel.org/u-boot/20231103-b4-qcom-clk-v3-0-8d2d460ece84@linar… --- Changes in v3: * Remove now-unneeded header includes in dragonboard{410,820}c-uboot.dtsi * Drop non-standard DTS support from PMIC GPIO driver * Also remove old gpio-keys nodes from starqltechn-uboot.dtsi * Link to v2: https://lore.kernel.org/r/20231108-b4-qcom-dt-compat-v2-0-713233c72948@lina… Changes in v2: * Avoid using non-standard "label" and "linux,code" properties for buttons * Add missing sdm845 DTS parts * Put button driver in drivers/button * Link to v1: https://lore.kernel.org/r/20231106-b4-qcom-dt-compat-v1-0-0ccbb7841241@lina… --- Caleb Connolly (5): gpio: qcom_pmic: fix silent dev_read_addr downcast gpio: qcom_pmic: rework pwrkey driver into a button driver gpio: qcom_pmic: fix support for upstream DT spmi: msm: fix register range names pmic: qcom: dont use dev_read_addr to get USID MAINTAINERS | 1 + arch/arm/dts/dragonboard410c-uboot.dtsi | 11 -- arch/arm/dts/dragonboard410c.dts | 25 +++- arch/arm/dts/dragonboard820c-uboot.dtsi | 12 -- arch/arm/dts/dragonboard820c.dts | 26 ++-- arch/arm/dts/dragonboard845c-uboot.dtsi | 11 -- arch/arm/dts/dragonboard845c.dts | 4 + arch/arm/dts/qcs404-evb.dts | 2 +- arch/arm/dts/sdm845.dtsi | 28 ++-- arch/arm/dts/starqltechn-uboot.dtsi | 10 -- arch/arm/dts/starqltechn.dts | 20 +-- arch/arm/mach-snapdragon/Kconfig | 3 + arch/arm/mach-snapdragon/init_sdm845.c | 45 ++----- board/qualcomm/dragonboard410c/dragonboard410c.c | 31 ++--- board/qualcomm/dragonboard820c/dragonboard820c.c | 29 ++-- drivers/button/Kconfig | 9 ++ drivers/button/Makefile | 1 + drivers/button/button-qcom-pmic.c | 165 +++++++++++++++++++++++ drivers/gpio/Kconfig | 3 +- drivers/gpio/qcom_pmic_gpio.c | 146 +++++--------------- drivers/power/pmic/pmic_qcom.c | 13 +- drivers/spmi/spmi-msm.c | 46 +++---- 22 files changed, 337 insertions(+), 304 deletions(-) --- base-commit: d1efa48e205960b15656eb0c13227110895f1cc9 // Caleb (they/them)

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[PATCH RESEND 1/2] drivers: watchdog: add andes atcwdt200 support
by Randolph 28 Nov '23

28 Nov '23

This patch adds an implementation of the Andes watchdog ATCWDT200 driver. Signed-off-by: CL Wang <cl634(a)andestech.com> Signed-off-by: Randolph <randolph(a)andestech.com> --- drivers/watchdog/Kconfig | 6 + drivers/watchdog/Makefile | 1 + drivers/watchdog/atcwdt200_wdt.c | 219 +++++++++++++++++++++++++++++++ 3 files changed, 226 insertions(+) create mode 100644 drivers/watchdog/atcwdt200_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 07fc4940e9..6b0f77dd3f 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -130,6 +130,12 @@ config WDT_AT91 Select this to enable Microchip watchdog timer, which can be found on some AT91 devices. +config WDT_ATCWDT200 + bool "Andes watchdog timer support" + depends on WDT + help + Select this to enable Andes ATCWDT200 watchdog timer + config WDT_BCM6345 bool "BCM6345 watchdog timer support" depends on WDT && (ARCH_BMIPS || BCM6856 || \ diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index eef786f5e7..1750ebbb1f 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_WDT_ARM_SMC) += arm_smc_wdt.o obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o +obj-$(CONFIG_WDT_ATCWDT200) += atcwdt200_wdt.o obj-$(CONFIG_WDT_BCM2835) += bcm2835_wdt.o obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o diff --git a/drivers/watchdog/atcwdt200_wdt.c b/drivers/watchdog/atcwdt200_wdt.c new file mode 100644 index 0000000000..dc34013473 --- /dev/null +++ b/drivers/watchdog/atcwdt200_wdt.c @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation. + * + */ + +#include <asm/io.h> +#include <dm.h> +#include <hang.h> +#include <linux/bitops.h> +#include <wdt.h> + +#define NODE_NOT_FOUND 0xFFFFFFFF + +#define WDT_WP_MAGIC 0x5aa5 +#define WDT_RESTART_MAGIC 0xcafe + +/* Control Register */ +#define REG_WDT_ID 0x00 +#define REG_WDT_CFG 0x10 +#define REG_WDT_RS 0x14 +#define REG_WDT_WE 0x18 +#define REG_WDT_STA 0x1C + +#define RST_TIME_OFF 8 +#define RST_TIME_MSK (0x7 << RST_TIME_OFF) +#define RST_CLK_128 (0 << RST_TIME_OFF) +#define RST_CLK_256 (1 << RST_TIME_OFF) +#define RST_CLK_512 (2 << RST_TIME_OFF) +#define RST_CLK_1024 (3 << RST_TIME_OFF) +#define INT_TIME_OFF 4 +#define INT_TIME_MSK (0xf << INT_TIME_OFF) +#define INT_CLK_2_6 (0 << INT_TIME_OFF) /* clk period*2^6 */ +#define INT_CLK_2_8 (1 << INT_TIME_OFF) /* clk period*2^8 */ +#define INT_CLK_2_10 (2 << INT_TIME_OFF) /* clk period*2^10 */ +#define INT_CLK_2_11 (3 << INT_TIME_OFF) /* clk period*2^11 */ +#define INT_CLK_2_12 (4 << INT_TIME_OFF) /* clk period*2^12 */ +#define INT_CLK_2_13 (5 << INT_TIME_OFF) /* clk period*2^13 */ +#define INT_CLK_2_14 (6 << INT_TIME_OFF) /* clk period*2^14 */ +#define INT_CLK_2_15 (7 << INT_TIME_OFF) /* clk period*2^15 */ +#define INT_CLK_2_17 (8 << INT_TIME_OFF) /* clk period*2^17 */ +#define INT_CLK_2_19 (9 << INT_TIME_OFF) /* clk period*2^19 */ +#define INT_CLK_2_21 (10 << INT_TIME_OFF) /* clk period*2^21 */ +#define INT_CLK_2_23 (11 << INT_TIME_OFF) /* clk period*2^23 */ +#define INT_CLK_2_25 (12 << INT_TIME_OFF) /* clk period*2^25 */ +#define INT_CLK_2_27 (13 << INT_TIME_OFF) /* clk period*2^27 */ +#define INT_CLK_2_29 (14 << INT_TIME_OFF) /* clk period*2^29 */ +#define INT_CLK_2_31 (15 << INT_TIME_OFF) /* clk period*2^31 */ +#define INT_CLK_MIN 0x0 +#define INT_CLK_MAX_16B 0x7 +#define INT_CLK_MAX_32B 0xF +#define RST_EN BIT(3) +#define INT_EN BIT(2) +#define CLK_PCLK BIT(1) +#define WDT_EN BIT(0) +#define INT_EXPIRED BIT(0) + +#define INT_TIME_ARRAY 16 +#define RST_TIME_ARRAY 8 + +struct wdt_priv { + void __iomem *base; + u32 wdt_clk_src; + u32 clk_freq; + u8 max_clk; +}; + +static inline u8 atcwdt_get_2_power_of_n(u8 index, u8 type) +{ + u8 div_int[INT_TIME_ARRAY] = {6, 8, 10, 11, 12, 13, 14, 15, 17, 19, 21, 23, 25, 27, 29, 31}; + u8 div_rst[RST_TIME_ARRAY] = {7, 8, 9, 10, 11, 12, 13, 14}; + u8 *pdiv; + + if (type == RST_TIME_ARRAY) + pdiv = div_rst; + else + pdiv = div_int; + + if (index >= type) + index = type - 1; + + return pdiv[index]; +} + +static u8 atwdt_search_msb(u64 freq_ms, u8 type) +{ + u64 result; + u64 freq_sec; + u8 index; + + freq_sec = freq_ms / 1000; + for (index = 0; index < type; index++) { + result = freq_sec >> atcwdt_get_2_power_of_n(index, type); + + if (result <= 1) + break; + } + + return index; +} + +static int atcwdt_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + struct wdt_priv *priv = dev_get_priv(dev); + u64 rst_max_count; + u32 rst_max_time_ms; + u64 rst_time_ms; + u64 int_time_ms; + u8 rst_time; + u8 int_time; + + rst_max_count = 1 << atcwdt_get_2_power_of_n(RST_TIME_ARRAY, RST_TIME_ARRAY); + rst_max_time_ms = (rst_max_count * 1000) / priv->clk_freq; + + if (timeout > rst_max_time_ms) { + int_time_ms = timeout - rst_max_time_ms; + rst_time_ms = rst_max_time_ms; + } else { + int_time_ms = 0; + rst_time_ms = timeout; + } + + rst_time = atwdt_search_msb(rst_time_ms * priv->clk_freq, RST_TIME_ARRAY); + + if (int_time_ms) { + int_time = atwdt_search_msb(int_time_ms * priv->clk_freq, INT_TIME_ARRAY); + if (int_time > priv->max_clk) + int_time = priv->max_clk; + } else { + int_time = 0; + } + + writel(WDT_WP_MAGIC, priv->base + REG_WDT_WE); + writel(((rst_time << RST_TIME_OFF) & RST_TIME_MSK) | ((int_time << INT_TIME_OFF) & + INT_TIME_MSK) | INT_EN | RST_EN | priv->wdt_clk_src | WDT_EN, + priv->base + REG_WDT_CFG); + + return 0; +} + +static int atcwdt_wdt_stop(struct udevice *dev) +{ + struct wdt_priv *priv = dev_get_priv(dev); + + writel(WDT_WP_MAGIC, priv->base + REG_WDT_WE); + writel(0, priv->base + REG_WDT_CFG); + + return 0; +} + +static int atcwdt_wdt_restart(struct udevice *dev) +{ + struct wdt_priv *priv = dev_get_priv(dev); + + writel(WDT_WP_MAGIC, priv->base + REG_WDT_WE); + writel(WDT_RESTART_MAGIC, priv->base + REG_WDT_RS); + setbits_le32(priv->base + REG_WDT_STA, INT_EXPIRED); + + return 0; +} + +static int atcwdt_wdt_expire_now(struct udevice *dev, ulong flags) +{ + atcwdt_wdt_start(dev, 0, 0); + hang(); + + return 0; +} + +static int atcwdt_wdt_probe(struct udevice *dev) +{ + struct wdt_priv *priv = dev_get_priv(dev); + int timer_16bit; + + priv->base = dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EFAULT; + + priv->wdt_clk_src = dev_read_u32_default(dev, "clock-source", NODE_NOT_FOUND); + if (priv->wdt_clk_src == NODE_NOT_FOUND || priv->wdt_clk_src > 1) + priv->wdt_clk_src = CLK_PCLK; + + timer_16bit = dev_read_u32_default(dev, "16bit_timer", NODE_NOT_FOUND); + if (timer_16bit == 1 || timer_16bit == NODE_NOT_FOUND) + priv->max_clk = INT_CLK_MAX_16B; + else + priv->max_clk = INT_CLK_MAX_32B; + + priv->clk_freq = dev_read_u32_default(dev, "clock-frequency", NODE_NOT_FOUND); + if (priv->clk_freq == NODE_NOT_FOUND) { + printf("atcwdt200: Please provide a valid \"clock-frequency\" in DTB\n"); + return -EINVAL; + } + + atcwdt_wdt_stop(dev); + + return 0; +} + +static const struct wdt_ops atcwdt_wdt_ops = { + .start = atcwdt_wdt_start, + .reset = atcwdt_wdt_restart, + .stop = atcwdt_wdt_stop, + .expire_now = atcwdt_wdt_expire_now, +}; + +static const struct udevice_id atcwdt_wdt_ids[] = { + {.compatible = "andestech,atcwdt200"}, + {} +}; + +U_BOOT_DRIVER(atcwdt) = { + .name = "atc_wdt", + .id = UCLASS_WDT, + .probe = atcwdt_wdt_probe, + .of_match = atcwdt_wdt_ids, + .ops = &atcwdt_wdt_ops, + .priv_auto = sizeof(struct wdt_priv), +}; -- 2.34.1

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[PATCH 0/2] board: ti: j721s2: Switch to standard boot
by Neha Malcom Francis 28 Nov '23

28 Nov '23

This series switches J721S2 to standard boot flow. Boot logs: https://gist.github.com/nehamalcom/127019254d49057b5d342f66841bfd3c Neha Malcom Francis (2): board: ti: j721s2: j721s2.env: Add explicit boot_targets configs: j721e_evm_a72_defconfig: Switch to bootstd board/ti/j721s2/j721s2.env | 1 + configs/j721s2_evm_a72_defconfig | 5 +++-- include/configs/j721s2_evm.h | 1 - 3 files changed, 4 insertions(+), 3 deletions(-) -- 2.34.1

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[PATCH v2 1/2] board: samsung: Fix SYS_CONFIG_NAME configs in axy17lte Kconfig
by Sam Protsenko 28 Nov '23

28 Nov '23

There is a couple of issues related to SYS_CONFIG_NAME config in axy17lte Kconfig. 1. The global SYS_CONFIG_NAME in axy17lte Kconfig overrides SYS_CONFIG_NAME for all boards specified after this line in arch/arm/mach-exynos/Kconfig: source "board/samsung/axy17lte/Kconfig" Right now it's the last 'source' line there, so the issue is not reproducible. But once some board is moved or added after this line the next build error will happen: GEN include/autoconf.mk.dep In file included from ./include/common.h:16: include/config.h:3:10: fatal error: configs/exynos78x0-common.h.h: No such file or directory 3 | #include <configs/exynos78x0-common.h.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. That's happening because axy17lte Kconfig defines SYS_CONFIG_NAME option in global namespace (not guarded with any "if TARGET_..."), so it basically rewrites the correct SYS_CONFIG_NAME defined in the hypothetical boards which might appear after axy17lte in mach-exynos Kconfig. 2. Another side of the issue is that SYS_CONFIG_NAME is defined incorrectly in axy17lte Kconfig: config SYS_CONFIG_NAME default "exynos78x0-common.h" The .h extension should not have been specified there. It's leading to a build error, as the generated include file has a double '.h' extension. 3. Each target in axy17lte/Kconfig defines its own SYS_CONFIG_NAME. But all of those in fact incorrect, as corresponding include/configs/<CONFIG_SYS_CONFIG_NAME>.h header files don't exist. 4. The global SYS_CONFIG_NAME pretty much repeats the help description from arch/Kconfig and doc/README.kconfig. Corresponding defconfig files (a*y17lte_defconfig) fix above issues by overriding SYS_CONFIG_NAME and correctly setting it to "exynos78x0-common". Fix all mentioned issues by removing the incorrect global SYS_CONFIG_NAME and instead specifying it (correctly) in SYS_CONFIG_NAME options for each target instead. Signed-off-by: Sam Protsenko <semen.protsenko(a)linaro.org> Fixes: 3e2095e960b4 ("board: samsung: add support for Galaxy A series of 2017 (a5y17lte)") --- Changes in v2: - Don't just remove global SYS_CONFIG_NAME, also fix SYS_CONFIG_NAME for each target in Kconfig board/samsung/axy17lte/Kconfig | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/board/samsung/axy17lte/Kconfig b/board/samsung/axy17lte/Kconfig index a018547ff5d4..64a4ffa7e673 100644 --- a/board/samsung/axy17lte/Kconfig +++ b/board/samsung/axy17lte/Kconfig @@ -1,11 +1,3 @@ -config SYS_CONFIG_NAME - string "Board configuration name" - default "exynos78x0-common.h" - help - This option contains information about board configuration name. - Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header - will be used for board configuration. - if TARGET_A5Y17LTE config SYS_BOARD default "axy17lte" @@ -16,7 +8,7 @@ config SYS_VENDOR default "samsung" config SYS_CONFIG_NAME - default "a5y17lte" + default "exynos78x0-common" config EXYNOS7880 bool "Exynos 7880 SOC support" @@ -33,7 +25,7 @@ config SYS_VENDOR default "samsung" config SYS_CONFIG_NAME - default "a5y17lte" + default "exynos78x0-common" config EXYNOS7880 bool "Exynos 7880 SOC support" @@ -50,7 +42,7 @@ config SYS_VENDOR default "samsung" config SYS_CONFIG_NAME - default "a3y17lte" + default "exynos78x0-common" config EXYNOS7870 bool "Exynos 7870 SOC support" -- 2.39.2

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[PATCH] serial: s5p: Use dev_read_addr_ptr() to get base address
by Sam Protsenko 28 Nov '23

28 Nov '23

As the address read from device tree is being cast to a pointer, it's better to use dev_read_addr_ptr() API for getting that address. The more detailed explanation can be found in commit a12a73b66476 ("drivers: use dev_read_addr_ptr when cast to pointer"). Signed-off-by: Sam Protsenko <semen.protsenko(a)linaro.org> --- drivers/serial/serial_s5p.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index c24d9bca84c9..7d04dcff54fc 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -221,13 +221,11 @@ static int s5p_serial_of_to_plat(struct udevice *dev) { struct s5p_serial_plat *plat = dev_get_plat(dev); const ulong port_type = dev_get_driver_data(dev); - fdt_addr_t addr; - addr = dev_read_addr(dev); - if (addr == FDT_ADDR_T_NONE) + plat->reg = dev_read_addr_ptr(dev); + if (!plat->reg) return -EINVAL; - plat->reg = (struct s5p_uart *)addr; plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1); plat->port_id = dev_read_u8_default(dev, "id", dev_seq(dev)); -- 2.39.2

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[PATCH 0/4] serial: s5p: Cleanups
by Sam Protsenko 28 Nov '23

28 Nov '23

A small collection of cleanup patches for serial_s5p.c driver. Should induce no functional changes. Sam Protsenko (4): serial: s5p: Remove common.h inclusion serial: s5p: Use livetree API to get "id" property serial: s5p: Use named constants for register values serial: s5p: Improve coding style drivers/serial/serial_s5p.c | 71 +++++++++++++++++++++---------------- 1 file changed, 40 insertions(+), 31 deletions(-) -- 2.39.2

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[PATCH 1/1] i2c: Bugfix in i2c_get_chip_by_phandle()
by Philip Oberfichtner 28 Nov '23

28 Nov '23

The "i2cbcdev" sneaked in when implementing this function for the bootcounter use case. Obviously the intention was to use prop_name instead. Fixes: b483552773 (i2c: Implement i2c_get_chip_by_phandle()) Signed-off-by: Philip Oberfichtner <pro(a)denx.de> --- drivers/i2c/i2c-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index d0db25dcc0..3cbd4a81a5 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -428,7 +428,7 @@ int i2c_get_chip_by_phandle(const struct udevice *parent, const char *prop_name, goto err_exit; } - ret = dev_read_u32(parent, "i2cbcdev", &phandle); + ret = dev_read_u32(parent, prop_name, &phandle); if (ret) goto err_exit; -- 2.39.2

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