November 2023 - U-Boot

[PATCH] clk: fix clk_get_rate() always return ulong
by Julien Masson 15 Dec '23

15 Dec '23

When we call clk_get_rate(), we expect to get clock rate value as ulong. In that case we should not use log_ret() macro since it use internally an int. Otherwise we may return an invalid/truncated clock rate value. Signed-off-by: Julien Masson <jmasson(a)baylibre.com> --- drivers/clk/clk-uclass.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 3b5e3f9c86..41dcd14be5 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -488,11 +488,7 @@ ulong clk_get_rate(struct clk *clk) if (!ops->get_rate) return -ENOSYS; - ret = ops->get_rate(clk); - if (ret) - return log_ret(ret); - - return 0; + return ops->get_rate(clk); } struct clk *clk_get_parent(struct clk *clk) -- 2.41.0

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[PATCH] arm64: imx8mp: Inhibit DTC warning on DH i.MX8MP DHCOM rev.100 DTO
by Marek Vasut 15 Dec '23

15 Dec '23

Inhibit DTC warning in imx8mp-dhcom-pdk3-overlay-rev100.dts: " arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dtbo: Warning (reg_format): /fragment@0/__overlay__:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dtbo: Warning (avoid_default_addr_size): /fragment@0/__overlay__: Relying on default #address-cells value arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dtbo: Warning (avoid_default_addr_size): /fragment@0/__overlay__: Relying on default #size-cells value " The DTO overwrites the 'reg' property of an ethernet PHY and is only used on specific combination of old prototype SoM and old prototype PDK3 carrier board, which had incorrectly placed pull resistor, which made the PHY change its MDIO address in that specific combination and which is already fixed on production hardware. The DTO is implemented in this simple manner because if it contained a full MDIO bus node reference to define #address-cells and #size-cells, it would also require a full new copy of the PHY node, i.e. ethernet-phy@5 { ... reg = <5>; ... }, to avoid DTC warnings about mismatch between node unit and reg value. The node unit in SoM DT is ethernet-phy@7 { ... }; . This simpler approach avoids unnecessary duplication without adverse side effects. Reported-by: Fabio Estevam <festevam(a)denx.de> Reported-by: Sean Anderson <seanga2(a)gmail.com> Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: "NXP i.MX U-Boot Team" <uboot-imx(a)nxp.com> Cc: Andreas Geisreiter <ageisreiter(a)dh-electronics.de> Cc: Christoph Niedermaier <cniedermaier(a)dh-electronics.com> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: u-boot(a)dh-electronics.com --- arch/arm/dts/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 66862a70be1..70845c7ac8c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1481,6 +1481,8 @@ targets += $(dtb-y) # Add any required device tree compiler flags here DTC_FLAGS += -a 0x8 +DTC_FLAGS_imx8mp-dhcom-pdk3-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format + PHONY += dtbs dtbs: $(addprefix $(obj)/, $(dtb-y)) @: -- 2.42.0

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[PATCH 0/7] doc: tools: Tidy up toml files for a new release
by Simon Glass 14 Dec '23

14 Dec '23

This series corrects a few problems with the generation of pip packages which showed up during a recent tools release. A new release has been completed for all tools with a new version number of 0.0.6 so this series reflects the changes there. It also updates the documentation URL to use the u-boot.org domain. Simon Glass (7): doc: Update documentation URL u_boot_pylib: Correct readme formatting tools: Keep test_util and patman test files in the pip release u_boot_pylib: Correct files used for pip release tools/make_pip: Add mention of u_boot_pylib in tool list patman: Update the run script tools: Move python tools to version 0.0.6 MAINTAINERS | 2 +- README | 2 +- doc/build/documentation.rst | 2 +- scripts/make_pip.sh | 14 ++++++++++++-- tools/binman/pyproject.toml | 6 +++--- tools/buildman/pyproject.toml | 6 +++--- tools/dtoc/pyproject.toml | 6 +++--- tools/patman/pyproject.toml | 8 ++++---- tools/u_boot_pylib/README.rst | 2 +- tools/u_boot_pylib/pyproject.toml | 9 ++++----- 10 files changed, 33 insertions(+), 24 deletions(-) -- 2.43.0.rc0.421.g78406f8d94-goog

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[PATCH] spi: cadence-quadspi: Fix error message on stuck busy state
by Jan Kiszka 14 Dec '23

14 Dec '23

From: Jan Kiszka <jan.kiszka(a)siemens.com> We are not iterating CQSPI_REG_RETRY, we are waiting 'timeout' ms, since day 1. Signed-off-by: Jan Kiszka <jan.kiszka(a)siemens.com> --- We are unfortunately seeing that message right now, rarely but then prominently... drivers/spi/cadence_qspi_apb.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 9ce2c0f254f..d033184aa46 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -171,8 +171,7 @@ static unsigned int cadence_qspi_wait_idle(void *reg_base) } /* Timeout, still in busy mode. */ - printf("QSPI: QSPI is still busy after poll for %d times.\n", - CQSPI_REG_RETRY); + printf("QSPI: QSPI is still busy after poll for %d ms.\n", timeout); return 0; } -- 2.35.3

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[PATCH] mtd: spi-nor-ids: add support for xtx XT55Q02G
by Bruce Suen 14 Dec '23

14 Dec '23

Add support for XTX XT55Q02G(1.8V,2Gbit). Signed-off-by: Bruce Suen <bruce_suen(a)163.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 4587215984..9aab913356 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -564,6 +564,8 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("xt25q01g", 0x0b601B, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("xt55q02g", 0x0b601C, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, /* adding these wide voltage QSPI flash parts */ { INFO("xt25w512", 0x0b651A, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, -- 2.34.1

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[PATCH v2 0/1] mtd: spinand: add support for ESMT F50x1G41LB
by Igor Prusov 14 Dec '23

14 Dec '23

This series ports ESMT NAND support from Linux. Changes in v2: - Dropped detect procedure rework patch, since similar one was already applied to u-boot in commit b20913e3cb. - Updated NAND_MEMORG values, so that they are correct after mbb parameter was added in 8acaec923b. Igor Prusov (1): mtd: spinand: add support for ESMT F50x1G41LB drivers/mtd/nand/spi/Makefile | 3 +- drivers/mtd/nand/spi/core.c | 1 + drivers/mtd/nand/spi/esmt.c | 137 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 1 + 4 files changed, 141 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/nand/spi/esmt.c -- 2.34.1

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[PATCH v1] drivers: mtd: spi: Add support for GD55LB02GEBIR SPI NOR flash
by Jit Loon Lim 14 Dec '23

14 Dec '23

From: Teik Heng Chong <teik.heng.chong(a)intel.com> Add Support for GigaDevice GD55LB02GEBIR SPI NOR flash as QSPI configuration flash Signed-off-by: Teik Heng Chong <teik.heng.chong(a)intel.com> --- drivers/mtd/spi/spi-nor-ids.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3f8b796789..3ca46330bb 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -200,6 +200,11 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, {INFO("gd55lx02g", 0xc8681C, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + { + INFO("gd55lb02ge", 0xc8671c, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ -- 2.26.2

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[PATCH v1] drivers: spi: Add MT25U01G part number for SPI NOR Flash
by Jit Loon Lim 14 Dec '23

14 Dec '23

MT25QU01 OPN with 4B OPCODE support is currently not supported in source code and the driver reuses the definition for "n25q00a" which has the same silicon ID but is a slower part. Adding mt25u01g definition to the source code to support a faster read response for MT25QU01 QSPI NOR Flash device. Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3ca46330bb..1b2e88cd26 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -311,6 +311,8 @@ const struct flash_info spi_nor_ids[] = { { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + { INFO6("mt25qu01g", 0x20bb21, 0x104400, 64 * 1024, 2048, SECT_4K | USE_FSR | +SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, -- 2.26.2

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[PATCH] drivers: mtd: Add MT25QU128AB params
by seanedmond＠linux.microsoft.com 14 Dec '23

14 Dec '23

From: Godfrey Mwangi <godmwan(a)microsoft.com> Add Micron MT25QU128AB flash. Signed-off-by: Godfrey Mwangi <godmwan(a)microsoft.com> --- drivers/mtd/spi/spi-nor-ids.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 4587215984..a99bb6125b 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -299,6 +299,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) }, { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) }, + { INFO("mt25qu128ab", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, -- 2.40.0

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[PATCH v2] spi: cadence_qspi: Select flash subnode at runtime
by Udit Kumar 14 Dec '23

14 Dec '23

Currently spi driver gets flash parameter from first subnode. Few boards have more than one flash with different parameters and selection of flash is done by on board switch settings. In such case, uboot needs to be recompiled with updated device tree to align with board switch settings. This patch allows to select flash node at runtime. Boards those are supporting multiple flashes needs to implement cadence_qspi_get_subnode function and return correct flash node. Cc: Apurva Nandan <a-nandan(a)ti.com> Signed-off-by: Udit Kumar <u-kumar1(a)ti.com> Reviewed-by: Neha Malcom Francis <n-francis(a)ti.com> --- One of such platform is J721S2 EVM link https://www.ti.com/lit/pdf/spruj69 Fig 3.1, Page 18 has details of two flashes connected with one controller Change log: Changes in v2 - Corrected link in comment - removed extra space - Added Reviewed-by, after addressing v1 feedback - link to v1 https://lore.kernel.org/all/20230907092143.4110817-1-u-kumar1@ti.com/ drivers/spi/cadence_qspi.c | 7 ++++++- drivers/spi/cadence_qspi.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index cc3a54f295..eb7fbf83d0 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -40,6 +40,11 @@ __weak int cadence_qspi_versal_flash_reset(struct udevice *dev) return 0; } +__weak ofnode cadence_qspi_get_subnode(struct udevice *dev) +{ + return dev_read_first_subnode(dev); +} + static int cadence_spi_write_speed(struct udevice *bus, uint hz) { struct cadence_spi_priv *priv = dev_get_priv(bus); @@ -401,7 +406,7 @@ static int cadence_spi_of_to_plat(struct udevice *bus) plat->is_dma = dev_read_bool(bus, "cdns,is-dma"); /* All other parameters are embedded in the child node */ - subnode = dev_read_first_subnode(bus); + subnode = cadence_qspi_get_subnode(bus); if (!ofnode_valid(subnode)) { printf("Error: subnode with SPI flash config missing!\n"); return -ENODEV; diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 1c59d1a9d9..12825f8911 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -304,6 +304,7 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv); int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg); int cadence_qspi_versal_flash_reset(struct udevice *dev); +ofnode cadence_qspi_get_subnode(struct udevice *dev); void cadence_qspi_apb_enable_linear_mode(bool enable); #endif /* __CADENCE_QSPI_H__ */ -- 2.34.1

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